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Diffstat (limited to '')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_e1.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h new file mode 100644 index 0000000..96b4661 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_e1.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_E1_H +#define NEOVERSE_E1_H + +#include <lib/utils_def.h> + +#define NEOVERSE_E1_MIDR U(0x410FD4A0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_E1_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_E1_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ + +#define NEOVERSE_E1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* NEOVERSE_E1_H */ |