diff options
Diffstat (limited to 'plat/amlogic/common/include')
-rw-r--r-- | plat/amlogic/common/include/aml_private.h | 41 | ||||
-rw-r--r-- | plat/amlogic/common/include/plat_macros.S | 71 |
2 files changed, 112 insertions, 0 deletions
diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h new file mode 100644 index 0000000..724f382 --- /dev/null +++ b/plat/amlogic/common/include/aml_private.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AML_PRIVATE_H +#define AML_PRIVATE_H + +#include <stddef.h> +#include <stdint.h> + +/* Utility functions */ +unsigned int plat_calc_core_pos(u_register_t mpidr); +void aml_console_init(void); +void aml_setup_page_tables(void); + +/* MHU functions */ +void aml_mhu_secure_message_start(void); +void aml_mhu_secure_message_send(uint32_t msg); +uint32_t aml_mhu_secure_message_wait(void); +void aml_mhu_secure_message_end(void); +void aml_mhu_secure_init(void); + +/* SCPI functions */ +void aml_scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state, + uint32_t cluster_state, uint32_t css_state); +uint32_t aml_scpi_sys_power_state(uint64_t system_state); +void aml_scpi_jtag_set_state(uint32_t state, uint8_t select); +uint32_t aml_scpi_efuse_read(void *dst, uint32_t base, uint32_t size); +void aml_scpi_unknown_thermal(uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3); +void aml_scpi_upload_scp_fw(uintptr_t addr, size_t size, int send); +uint32_t aml_scpi_get_chip_id(uint8_t *obuff, uint32_t osize); + +/* Peripherals */ +void aml_thermal_unknown(void); +uint64_t aml_efuse_read(void *dst, uint32_t offset, uint32_t size); +uint64_t aml_efuse_user_max(void); + +#endif /* AML_PRIVATE_H */ diff --git a/plat/amlogic/common/include/plat_macros.S b/plat/amlogic/common/include/plat_macros.S new file mode 100644 index 0000000..d620fcf --- /dev/null +++ b/plat/amlogic/common/include/plat_macros.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <drivers/arm/gicv2.h> +#include <platform_def.h> + +.section .rodata.gic_reg_name, "aS" + +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + + /* GICC registers */ + + mov_imm x17, AML_GICC_BASE + + adr x6, gicc_regs + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + bl str_in_crash_buf_print + + /* GICD registers */ + + mov_imm x16, AML_GICD_BASE + + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str + +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + + .endm + +#endif /* PLAT_MACROS_S */ |