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Diffstat (limited to '')
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h new file mode 100644 index 0000000..e939163 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_DMC620_TZC_REGIONS_H +#define SGI_DMC620_TZC_REGIONS_H + +#include <drivers/arm/tzc_dmc620.h> + +#if SPM_MM +#define CSS_SGI_DMC620_TZC_REGIONS_DEF \ + { \ + .region_base = ARM_AP_TZC_DRAM1_BASE, \ + .region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + }, { \ + .region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \ + .region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \ + .sec_attr = TZC_DMC620_REGION_S_NS_RDWR \ + }, { \ + .region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \ + .region_top = ARM_AP_TZC_DRAM1_END, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + } +#else +#define CSS_SGI_DMC620_TZC_REGIONS_DEF \ + { \ + .region_base = ARM_AP_TZC_DRAM1_BASE, \ + .region_top = ARM_AP_TZC_DRAM1_END, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + } +#endif /* SPM_MM */ + +#endif /* SGI_DMC620_TZC_REGIONS_H */ |