diff options
Diffstat (limited to 'plat/arm/css/sgi/include')
| -rw-r--r-- | plat/arm/css/sgi/include/plat_macros.S | 24 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_base_platform_def.h | 300 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h | 36 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_plat.h | 13 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_ras.h | 21 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_sdei.h | 25 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_soc_css_def.h | 47 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_soc_css_def_v2.h | 202 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_soc_platform_def.h | 33 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h | 31 | ||||
| -rw-r--r-- | plat/arm/css/sgi/include/sgi_variant.h | 49 |
11 files changed, 781 insertions, 0 deletions
diff --git a/plat/arm/css/sgi/include/plat_macros.S b/plat/arm/css/sgi/include/plat_macros.S new file mode 100644 index 0000000..521bcc3 --- /dev/null +++ b/plat/arm/css/sgi/include/plat_macros.S @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <css_macros.S> + +/* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * + * There are currently no platform specific regs + * to print. + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h new file mode 100644 index 0000000..c1fadc6 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_BASE_PLATFORM_DEF_H +#define SGI_BASE_PLATFORM_DEF_H + +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/common/arm_def.h> +#include <plat/arm/common/arm_spm_def.h> +#include <plat/arm/css/common/css_def.h> +#include <plat/common/common_def.h> + +#define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \ + PLAT_ARM_CLUSTER_COUNT * \ + CSS_SGI_MAX_CPUS_PER_CLUSTER * \ + CSS_SGI_MAX_PE_PER_CPU) + +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ + +/* Remote chip address offset */ +#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) \ + ((ULL(1) << CSS_SGI_ADDR_BITS_PER_CHIP) * (n)) + +/* + * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. In addition to that, on + * multi-chip platforms, address regions on each of the remote chips are + * also mapped. In BL31, for instance, three address regions on the remote + * chips are accessed - secure ram, css device and soc device regions. + */ +#if defined(IMAGE_BL31) +# if SPM_MM +# define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) +# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) +# define PLAT_SP_IMAGE_MMAP_REGIONS 10 +# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 +# else +# define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) +# define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) +# endif +#elif defined(IMAGE_BL32) +# define PLAT_ARM_MMAP_ENTRIES 8 +# define MAX_XLAT_TABLES 5 +#elif defined(IMAGE_BL2) +# define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1)) + +/* + * MAX_XLAT_TABLES entries need to be doubled because when the address width + * exceeds 40 bits an additional level of translation is required. In case of + * multichip platforms peripherals also fall into address space with width + * > 40 bits + * + */ +# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2)) +#elif !USE_ROMLIB +# define PLAT_ARM_MMAP_ENTRIES 11 +# define MAX_XLAT_TABLES 7 +#else +# define PLAT_ARM_MMAP_ENTRIES 12 +# define MAX_XLAT_TABLES 6 +#endif + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE (64 * 1024) /* 64 KB */ + +/* + * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page + */ + +#if USE_ROMLIB +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 +#else +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. Additional 8KiB space is added per chip in + * order to accommodate the additional level of translation required for "TZC" + * peripheral access which lies in >4TB address space. + * + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((CSS_SGI_CHIP_COUNT - 1) * \ + 0x2000)) +#else +# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \ + 0x2000)) +#endif + +/* + * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is + * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2 + * and BL1-RW. CSS_SGI_BL31_SIZE - is tuned with respect to the actual BL31 + * PROGBITS size which is around 64-68KB at the time this change is being made. + * A buffer of ~35KB is added to account for future expansion of the image, + * making it a total of 100KB. + */ +#define CSS_SGI_BL31_SIZE (100 * 1024) /* 100 KB */ +#define PLAT_ARM_MAX_BL31_SIZE (CSS_SGI_BL31_SIZE + \ + PLAT_ARM_MAX_BL2_SIZE + \ + PLAT_ARM_MAX_BL1_RW_SIZE) + +/* + * Size of cacheable stacks + */ +#if defined(IMAGE_BL1) +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x440 +# endif +#elif defined(IMAGE_BL2) +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif defined(IMAGE_BL2U) +# define PLATFORM_STACK_SIZE 0x400 +#elif defined(IMAGE_BL31) +# if SPM_MM +# define PLATFORM_STACK_SIZE 0x500 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif defined(IMAGE_BL32) +# define PLATFORM_STACK_SIZE 0x440 +#endif + +/* PL011 UART related constants */ +#define SOC_CSS_SEC_UART_BASE UL(0x2A410000) +#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000) +#define SOC_CSS_UART_SIZE UL(0x10000) +#define SOC_CSS_UART_CLK_IN_HZ UL(7372800) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +#define PLAT_ARM_NSTIMER_FRAME_ID 0 + +#define PLAT_ARM_TRUSTED_ROM_BASE 0x0 +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ + +#define PLAT_ARM_NSRAM_BASE 0x06000000 +#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ + +#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) +#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) + +#define CSS_SGI_DEVICE_BASE (0x20000000) +#define CSS_SGI_DEVICE_SIZE (0x20000000) +#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ + CSS_SGI_DEVICE_BASE, \ + CSS_SGI_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \ + MAP_REGION_FLAT( \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_NON_CACHEABLE | MT_RW | MT_SECURE \ + ) + +#define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \ + MAP_REGION_FLAT( \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ + CSS_SGI_DEVICE_BASE, \ + CSS_SGI_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE \ + ) + +#define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \ + MAP_REGION_FLAT( \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ + SOC_CSS_DEVICE_BASE, \ + SOC_CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE \ + ) + +/* Map the secure region for access from S-EL0 */ +#define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_CSS_DEVICE_BASE, \ + SOC_CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE | MT_USER) + +#define PLAT_SP_PRI PLAT_RAS_PRI + +#if SPM_MM && RAS_EXTENSION +/* + * CPER buffer memory of 128KB is reserved and it is placed adjacent to the + * memory shared between EL3 and S-EL0. + */ +#define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ + PLAT_SP_IMAGE_NS_BUF_SIZE) +#define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x20000) +#define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \ + CSS_SGI_SP_CPER_BUF_BASE, \ + CSS_SGI_SP_CPER_BUF_BASE, \ + CSS_SGI_SP_CPER_BUF_SIZE, \ + MT_RW_DATA | MT_NS | MT_USER, \ + PAGE_SIZE) + +/* + * Secure partition stack follows right after the memory space reserved for + * CPER buffer memory. + */ +#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ + PLAT_SP_IMAGE_NS_BUF_SIZE + \ + CSS_SGI_SP_CPER_BUF_SIZE) +#elif SPM_MM +/* + * Secure partition stack follows right after the memory region that is shared + * between EL3 and S-EL0. + */ +#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ + PLAT_SP_IMAGE_NS_BUF_SIZE) +#endif /* SPM_MM && RAS_EXTENSION */ + +/* Platform ID address */ +#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) +#ifndef __ASSEMBLER__ +/* SSC_VERSION related accessors */ +/* Returns the part number of the platform */ +#define GET_SGI_PART_NUM \ + GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) +/* Returns the configuration number of the platform */ +#define GET_SGI_CONFIG_NUM \ + GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) +#endif /* __ASSEMBLER__ */ + +/******************************************************************************* + * Memprotect definitions + ******************************************************************************/ +/* PSCI memory protect definitions: + * This variable is stored in a non-secure flash because some ARM reference + * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT + * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. + */ +#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ + V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +/*Secure Watchdog Constants */ +#define SBSA_SECURE_WDOG_BASE UL(0x2A480000) +#define SBSA_SECURE_WDOG_TIMEOUT UL(100) + +/* Number of SCMI channels on the platform */ +#define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT + +/* + * Mapping definition of the TrustZone Controller for ARM SGI/RD platforms + * where both the DRAM regions are marked for non-secure access. This applies + * to multi-chip platforms. + */ +#define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \ + {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \ + ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \ + ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} + +#if SPM_MM + +/* + * Stand-alone MM logs would be routed via secure UART. Define page table + * entry for secure UART which would be common to all platforms. + */ +#define SOC_PLATFORM_SECURE_UART MAP_REGION_FLAT( \ + SOC_CSS_SEC_UART_BASE, \ + SOC_CSS_UART_SIZE, \ + MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER) + +#endif + +/* SDS ID for unusable CPU MPID list structure */ +#define SDS_ISOLATED_CPU_LIST_ID U(128) + +#endif /* SGI_BASE_PLATFORM_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h new file mode 100644 index 0000000..e939163 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_DMC620_TZC_REGIONS_H +#define SGI_DMC620_TZC_REGIONS_H + +#include <drivers/arm/tzc_dmc620.h> + +#if SPM_MM +#define CSS_SGI_DMC620_TZC_REGIONS_DEF \ + { \ + .region_base = ARM_AP_TZC_DRAM1_BASE, \ + .region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + }, { \ + .region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \ + .region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \ + .sec_attr = TZC_DMC620_REGION_S_NS_RDWR \ + }, { \ + .region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \ + .region_top = ARM_AP_TZC_DRAM1_END, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + } +#else +#define CSS_SGI_DMC620_TZC_REGIONS_DEF \ + { \ + .region_base = ARM_AP_TZC_DRAM1_BASE, \ + .region_top = ARM_AP_TZC_DRAM1_END, \ + .sec_attr = TZC_DMC620_REGION_S_RDWR \ + } +#endif /* SPM_MM */ + +#endif /* SGI_DMC620_TZC_REGIONS_H */ diff --git a/plat/arm/css/sgi/include/sgi_plat.h b/plat/arm/css/sgi/include/sgi_plat.h new file mode 100644 index 0000000..a5fbded --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_plat.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_PLAT_H +#define SGI_PLAT_H + +/* BL31 platform setup common to all SGI based platforms */ +void sgi_bl31_common_platform_setup(void); + +#endif /* SGI_PLAT_H */ diff --git a/plat/arm/css/sgi/include/sgi_ras.h b/plat/arm/css/sgi/include/sgi_ras.h new file mode 100644 index 0000000..e69a684 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_ras.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_RAS_H +#define SGI_RAS_H + +/* + * Mapping the RAS interrupt with SDEI event number and the event + * id used with Standalone MM code + */ +struct sgi_ras_ev_map { + int sdei_ev_num; /* SDEI Event number */ + int intr; /* Physical intr number */ +}; + +int sgi_ras_intr_handler_setup(void); + +#endif /* SGI_RAS_H */ diff --git a/plat/arm/css/sgi/include/sgi_sdei.h b/plat/arm/css/sgi/include/sgi_sdei.h new file mode 100644 index 0000000..f380122 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_sdei.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SDEI_H +#define SGI_SDEI_H + +#if SDEI_SUPPORT + +/* ARM SDEI dynamic shared event numbers */ +#define SGI_SDEI_DS_EVENT_0 U(804) +#define SGI_SDEI_DS_EVENT_1 U(805) + +#define PLAT_ARM_PRIVATE_SDEI_EVENTS \ + SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ + SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ + SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), + +#define PLAT_ARM_SHARED_SDEI_EVENTS + +#endif /* SDEI_SUPPORT */ + +#endif /* SGI_SDEI_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def.h b/plat/arm/css/sgi/include/sgi_soc_css_def.h new file mode 100644 index 0000000..f78b45a --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_soc_css_def.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SOC_CSS_DEF_H +#define SGI_SOC_CSS_DEF_H + +#include <lib/utils_def.h> +#include <plat/arm/board/common/v2m_def.h> +#include <plat/arm/soc/common/soc_css_def.h> +#include <plat/common/common_def.h> + +/* + * Definitions common to all ARM CSSv1-based development platforms + */ + +/* Platform ID address */ +#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x7ffe00e0) + +/* Platform ID related accessors */ +#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f +#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 +#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 + +#ifndef __ASSEMBLER__ + +#include <lib/mmio.h> + +#define BOARD_CSS_GET_PLAT_TYPE(addr) \ + ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ + >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) + +#endif /* __ASSEMBLER__ */ + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* Reserve the last block of flash for PSCI MEM PROTECT flag */ +#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#endif /* SGI_SOC_CSS_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h new file mode 100644 index 0000000..acf31eb --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SOC_CSS_DEF_V2_H +#define SGI_SOC_CSS_DEF_V2_H + +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + +/* + * Definitions common to all ARM CSS SoCs + */ + +/* Following covers ARM CSS SoC Peripherals */ + +#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000) +#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000) + +#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000) +#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000) + +#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000) + +/* Memory controller */ +#define SOC_MEMCNTRL_BASE UL(0x10000000) +#define SOC_MEMCNTRL_SIZE UL(0x10000000) + +/* SoC NIC-400 Global Programmers View (GPV) */ +#define SOC_CSS_NIC400_BASE UL(0x0ED00000) + +#define SOC_CSS_NIC400_USB_EHCI U(0) +#define SOC_CSS_NIC400_TLX_MASTER U(1) +#define SOC_CSS_NIC400_USB_OHCI U(2) +#define SOC_CSS_NIC400_PL354_SMC U(3) +/* + * The apb4_bridge controls access to: + * - the PCIe configuration registers + * - the MMU units for USB, HDLCD and DMA + */ +#define SOC_CSS_NIC400_APB4_BRIDGE U(4) + +/* Non-volatile counters */ +#define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000) +#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) +#define TFW_NVCTR_SIZE U(4) +#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) +#define NTFW_CTR_SIZE U(4) + +/* Keys */ +#define SOC_KEYS_BASE UL(0x0EE80000) +#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) +#define TZ_PUB_KEY_HASH_SIZE U(32) +#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) +#define HU_KEY_SIZE U(16) +#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) +#define END_KEY_SIZE U(32) + +#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_PLATFORM_PERIPH_BASE, \ + SOC_PLATFORM_PERIPH_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#if SPM_MM +/* + * Memory map definition for the platform peripheral memory region that is + * accessible from S-EL0 (with secure user mode access). + */ +#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \ + MAP_REGION_FLAT( \ + SOC_PLATFORM_PERIPH_BASE, \ + SOC_PLATFORM_PERIPH_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE | MT_USER) +#endif + +#define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_SYSTEM_PERIPH_BASE, \ + SOC_SYSTEM_PERIPH_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_MEMCNTRL_BASE, \ + SOC_MEMCNTRL_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \ + MAP_REGION_FLAT( \ + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \ + SOC_MEMCNTRL_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. + */ +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5) +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12) + +/* + * Required platform porting definitions common to all ARM CSS SoCs + */ +/* 2MB used for SCP DDR retraining */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000) + +/* V2M motherboard system registers & offsets */ +#define V2M_SYSREGS_BASE UL(0x0C010000) +#define V2M_SYS_LED U(0x8) + +/* + * V2M sysled bit definitions. The values written to this + * register are defined in arch.h & runtime_svc.h. Only + * used by the primary cpu to diagnose any cold boot issues. + * + * SYS_LED[0] - Security state (S=0/NS=1) + * SYS_LED[2:1] - Exception Level (EL3-EL0) + * SYS_LED[7:3] - Exception Class (Sync/Async & origin) + * + */ +#define V2M_SYS_LED_SS_SHIFT U(0) +#define V2M_SYS_LED_EL_SHIFT U(1) +#define V2M_SYS_LED_EC_SHIFT U(3) + +#define V2M_SYS_LED_SS_MASK U(0x01) +#define V2M_SYS_LED_EL_MASK U(0x03) +#define V2M_SYS_LED_EC_MASK U(0x1f) + +/* NOR Flash */ +#define V2M_FLASH0_BASE UL(0x08000000) +#define V2M_FLASH0_SIZE UL(0x04000000) +#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ + +/* + * The flash can be mapped either as read-only or read-write. + * + * If it is read-write then it should also be mapped as device memory because + * NOR flash programming involves sending a fixed, ordered sequence of commands. + * + * If it is read-only then it should also be mapped as: + * - Normal memory, because reading from NOR flash is transparent, it is like + * reading from RAM. + * - Non-executable by default. If some parts of the flash need to be executable + * then platform code is responsible for re-mapping the appropriate portion + * of it as executable. + */ +#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_RO_DATA | MT_SECURE) + +#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) + +/* Platform ID address */ +#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0) + +/* Platform ID related accessors */ +#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F) +#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00) +#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00) +#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08) +#define BOARD_CSS_PLAT_TYPE_RTL U(0x00) +#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01) +#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02) +#define BOARD_CSS_PLAT_TYPE_FVP U(0x03) + +#ifndef __ASSEMBLER__ + +#include <lib/mmio.h> + +#define BOARD_CSS_GET_PLAT_TYPE(addr) \ + ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ + >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) + +#endif /* __ASSEMBLER__ */ + + +#define MAX_IO_DEVICES U(3) +#define MAX_IO_HANDLES U(4) + +/* Reserve the last block of flash for PSCI MEM PROTECT flag */ +#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#if ARM_GPT_SUPPORT +/* + * Offset of the FIP in the GPT image. BL1 component uses this option + * as it does not load the partition table to get the FIP base + * address. At sector 34 by default (i.e. after reserved sectors 0-33) + * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 + */ +#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 +#endif /* ARM_GPT_SUPPORT */ + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#endif /* SGI_SOC_CSS_DEF_V2_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def.h b/plat/arm/css/sgi/include/sgi_soc_platform_def.h new file mode 100644 index 0000000..3b8d9c6 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_soc_platform_def.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SOC_PLATFORM_DEF_H +#define SGI_SOC_PLATFORM_DEF_H + +#include <plat/arm/board/common/v2m_def.h> +#include <plat/arm/soc/common/soc_css_def.h> +#include <sgi_base_platform_def.h> +#include <sgi_soc_css_def.h> + +/* Map the System registers to access from S-EL0 */ +#define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000) +#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000) +#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \ + CSS_SYSTEMREG_DEVICE_BASE, \ + CSS_SYSTEMREG_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + +/* Map the NOR2 Flash to access from S-EL0 */ +#define CSS_NOR2_FLASH_DEVICE_BASE (0x10000000) +#define CSS_NOR2_FLASH_DEVICE_SIZE (0x04000000) +#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \ + CSS_NOR2_FLASH_DEVICE_BASE, \ + CSS_NOR2_FLASH_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + +#endif /* SGI_SOC_PLATFORM_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h new file mode 100644 index 0000000..20dd682 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SOC_PLATFORM_DEF_V2_H +#define SGI_SOC_PLATFORM_DEF_V2_H + +#include <sgi_base_platform_def.h> +#include <sgi_soc_css_def_v2.h> + +/* Map the System registers to access from S-EL0 */ +#define CSS_SYSTEMREG_DEVICE_BASE (0x0C010000) +#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000) +#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \ + CSS_SYSTEMREG_DEVICE_BASE, \ + CSS_SYSTEMREG_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + +/* Map the NOR2 Flash to access from S-EL0 */ +#define CSS_NOR2_FLASH_DEVICE_BASE (0x001054000000) +#define CSS_NOR2_FLASH_DEVICE_SIZE (0x000004000000) +#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \ + CSS_NOR2_FLASH_DEVICE_BASE, \ + CSS_NOR2_FLASH_DEVICE_SIZE, \ + (MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER)) + +#endif /* SGI_SOC_PLATFORM_DEF_V2_H */ diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h new file mode 100644 index 0000000..223ac3e --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_variant.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_VARIANT_H +#define SGI_VARIANT_H + +/* SSC_VERSION values for SGI575 */ +#define SGI575_SSC_VER_PART_NUM 0x0783 + +/* SID Version values for RD-N1E1-Edge */ +#define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786 +#define RD_E1_EDGE_CONFIG_ID 0x2 + +/* SID Version values for RD-V1 */ +#define RD_V1_SID_VER_PART_NUM 0x078a + +/* SID Version values for RD-N2 */ +#define RD_N2_SID_VER_PART_NUM 0x07B7 + +/* SID Version values for RD-N2 variants */ +#define RD_N2_CFG1_SID_VER_PART_NUM 0x07B6 + +/* SID Version values for RD-V2 */ +#define RD_V2_SID_VER_PART_NUM 0x07F2 +#define RD_V2_CONFIG_ID 0x1 + +/* Structure containing SGI platform variant information */ +typedef struct sgi_platform_info { + unsigned int platform_id; /* Part Number of the platform */ + unsigned int config_id; /* Config Id of the platform */ + unsigned int chip_id; /* Chip Id or Node number */ + unsigned int multi_chip_mode; /* Multi-chip mode availability */ +} sgi_platform_info_t; + +extern sgi_platform_info_t sgi_plat_info; + +/* returns the part number of the platform*/ +unsigned int plat_arm_sgi_get_platform_id(void); + +/* returns the configuration id of the platform */ +unsigned int plat_arm_sgi_get_config_id(void); + +/* returns true if operating in multi-chip configuration */ +unsigned int plat_arm_sgi_get_multi_chip_mode(void); + +#endif /* SGI_VARIANT_H */ |