diff options
Diffstat (limited to 'plat/brcm/board/stingray/include')
22 files changed, 2185 insertions, 0 deletions
diff --git a/plat/brcm/board/stingray/include/bl33_info.h b/plat/brcm/board/stingray/include/bl33_info.h new file mode 100644 index 0000000..1dac48c --- /dev/null +++ b/plat/brcm/board/stingray/include/bl33_info.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BL33_INFO_H +#define BL33_INFO_H + +/* Increase version number each time this file is modified */ +#define BL33_INFO_VERSION 4 + +struct chip_info { + unsigned int chip_id; + unsigned int rev_id; +}; + +struct boot_time_info { + unsigned int bl1_start; + unsigned int bl1_end; + unsigned int bl2_start; + unsigned int bl2_end; + unsigned int bl31_start; + unsigned int bl31_end; + unsigned int bl32_start; + unsigned int bl32_end; + unsigned int bl33_start; + unsigned int bl33_prompt; + unsigned int bl33_end; +}; + +struct bl33_info { + unsigned int version; + struct chip_info chip; + struct boot_time_info boot_time_info; +}; + +#endif diff --git a/plat/brcm/board/stingray/include/board_info.h b/plat/brcm/board/stingray/include/board_info.h new file mode 100644 index 0000000..8901259 --- /dev/null +++ b/plat/brcm/board/stingray/include/board_info.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_INFO_H +#define BOARD_INFO_H + +#define IHOST_REG_INTEGRATED 0 +#define IHOST_REG_EXT_PROGRAMMABLE 1 +#define IHOST_REG_EXT_FIXED 2 + +#if defined(IHOST_REG_TYPE) + #if ((IHOST_REG_TYPE != IHOST_REG_INTEGRATED) && \ + (IHOST_REG_TYPE != IHOST_REG_EXT_PROGRAMMABLE) && \ + (IHOST_REG_TYPE != IHOST_REG_EXT_FIXED)) + #error "IHOST_REG_TYPE not valid" + #endif +#else + #define IHOST_REG_TYPE IHOST_REG_INTEGRATED +#endif + +#define VDDC_REG_INTEGRATED 0 +#define VDDC_REG_EXT_PROGRAMMABLE 1 +#define VDDC_REG_EXT_FIXED 2 + +#if defined(VDDC_REG_TYPE) + #if ((VDDC_REG_TYPE != VDDC_REG_INTEGRATED) && \ + (VDDC_REG_TYPE != VDDC_REG_EXT_PROGRAMMABLE) && \ + (VDDC_REG_TYPE != VDDC_REG_EXT_FIXED)) + #error "VDDC_REG_TYPE not valid" + #endif +#else + #define VDDC_REG_TYPE VDDC_REG_INTEGRATED +#endif + +#endif diff --git a/plat/brcm/board/stingray/include/crmu_def.h b/plat/brcm/board/stingray/include/crmu_def.h new file mode 100644 index 0000000..ebc2bb6 --- /dev/null +++ b/plat/brcm/board/stingray/include/crmu_def.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CRMU_DEF_H +#define CRMU_DEF_H + +#define CRMU_REGS_BASE 0x66410000 +/* 32 kB IDRAM */ +#define CRMU_IDRAM_BASE_ADDR CRMU_REGS_BASE +#define CRMU_IDRAM_SIZE 0x8000 +/* 4 kB Scratch RAM */ +#define CRMU_SRAM_BASE (CRMU_IDRAM_BASE_ADDR + CRMU_IDRAM_SIZE) +#define CRMU_SRAM_SIZE 0x1000 + +#define CRMU_RESERVED_SPACE 0x3000 +#define CRMU_CORE_BASE (CRMU_SRAM_BASE + CRMU_SRAM_SIZE + \ + CRMU_RESERVED_SPACE) + +#define CRMU_SHARED_SRAM_BASE CRMU_SRAM_BASE +#define CRMU_SHARED_SRAM_SIZE 0x200 +#define CRMU_CFG_BASE (CRMU_SHARED_SRAM_BASE + \ + CRMU_SHARED_SRAM_SIZE) + +#define CRMU_PWR_GOOD_STATUS CRMU_CORE_BASE +#define CRMU_PWR_GOOD_STATUS__BBL_POWER_GOOD 0 +#define CRMU_ISO_CELL_CONTROL (CRMU_CORE_BASE + 0x4) +#define CRMU_ISO_CELL_CONTROL__CRMU_ISO_PDBBL 16 +#define CRMU_ISO_CELL_CONTROL__CRMU_ISO_PDBBL_TAMPER 24 +#define CRMU_SPRU_SOURCE_SEL_STAT (CRMU_CORE_BASE + 0xc) +#define CRMU_SPRU_SOURCE_SEL_STAT__SPRU_SOURCE_SELECT 0 +#define BSTI_BASE (CRMU_CORE_BASE + 0x28) +#define BSTI_CONTROL_OFFSET BSTI_BASE +#define BSTI_COMMAND_OFFSET (BSTI_BASE + 0x4) + +#define OCOTP_REGS_BASE (CRMU_CORE_BASE + 0x400) + +#define CRMU_TCI_BASE (CRMU_CORE_BASE + 0x800) +#define CRMU_SWREG_STATUS_ADDR (CRMU_TCI_BASE + 0x0c) +#define CRMU_CHIP_OTPC_STATUS (CRMU_TCI_BASE + 0x10) +#define CRMU_CHIP_OTPC_STATUS__OTP_BISR_LOAD_DONE 19 +#define CRMU_BISR_PDG_MASK (CRMU_TCI_BASE + 0x4c) +#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST0 2 +#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST1 3 +#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST2 4 +#define CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST3 0 +#define CRMU_POWER_POLL (CRMU_TCI_BASE + 0x60) +#define CRMU_OTP_STATUS CRMU_POWER_POLL +#define CRMU_OTP_STATUS_BIT 1 +#define CRMU_DDR_PHY_AON_CTRL (CRMU_TCI_BASE + 0x64) +#define CRMU_DDRPHY2_HW_RESETN_R BIT(21) +#define CRMU_DDRPHY2_PWROKIN_PHY_R BIT(20) +#define CRMU_DDRPHY2_PWRONIN_PHY_R BIT(19) +#define CRMU_DDRPHY2_ISO_PHY_DFI_R BIT(18) +#define CRMU_DDRPHY2_ISO_PHY_REGS_R BIT(17) +#define CRMU_DDRPHY2_ISO_PHY_PLL_R BIT(16) +#define CRMU_DDRPHY1_HW_RESETN_R BIT(13) +#define CRMU_DDRPHY1_PWROKIN_PHY_R BIT(12) +#define CRMU_DDRPHY1_PWRONIN_PHY_R BIT(11) +#define CRMU_DDRPHY1_ISO_PHY_DFI_R BIT(10) +#define CRMU_DDRPHY1_ISO_PHY_REGS_R BIT(9) +#define CRMU_DDRPHY1_ISO_PHY_PLL_R BIT(8) +#define CRMU_DDRPHY0_HW_RESETN_R BIT(5) +#define CRMU_DDRPHY0_PWROKIN_PHY_R BIT(4) +#define CRMU_DDRPHY0_PWRONIN_PHY_R BIT(3) +#define CRMU_DDRPHY0_ISO_PHY_DFI_R BIT(2) +#define CRMU_DDRPHY0_ISO_PHY_REGS_R BIT(1) +#define CRMU_DDRPHY0_ISO_PHY_PLL_R BIT(0) +#define CRMU_EMEM_RESET_N_R BIT(16) +#define CRMU_EMEM_PRESET_N_R BIT(0) +#define CRMU_SWREG_CTRL_ADDR (CRMU_TCI_BASE + 0x6c) +#define CRMU_AON_CTRL1 (CRMU_TCI_BASE + 0x70) +#define CRMU_AON_CTRL1__LCPLL1_ISO_IN 18 +#define CRMU_AON_CTRL1__LCPLL1_PWRON_LDO 19 +#define CRMU_AON_CTRL1__LCPLL1_PWR_ON 20 +#define CRMU_AON_CTRL1__LCPLL0_ISO_IN 21 +#define CRMU_AON_CTRL1__LCPLL0_PWRON_LDO 22 +#define CRMU_AON_CTRL1__LCPLL0_PWR_ON 23 +#define CRMU_PCIE_LCPLL_PWR_ON_SHIFT 29 +#define CRMU_PCIE_LCPLL_PWR_ON_MASK BIT(CRMU_PCIE_LCPLL_PWR_ON_SHIFT) +#define CRMU_PCIE_LCPLL_PWRON_LDO_SHIFT 28 +#define CRMU_PCIE_LCPLL_PWRON_LDO_MASK BIT(CRMU_PCIE_LCPLL_PWRON_LDO_SHIFT) +#define CRMU_PCIE_LCPLL_ISO_IN_SHIFT 27 +#define CRMU_PCIE_LCPLL_ISO_IN_MASK BIT(CRMU_PCIE_LCPLL_ISO_IN_SHIFT) +#define CRMU_MASTER_AXI_ARUSER_CONFIG (CRMU_TCI_BASE + 0x74) +#define CRMU_MASTER_AXI_AWUSER_CONFIG (CRMU_TCI_BASE + 0x78) +#define CRMU_DDR_PHY_AON_CTRL_1 (CRMU_TCI_BASE + 0x8c) + +#define CDRU_BASE_ADDR (CRMU_CORE_BASE + 0x1000) +#define CDRU_MISC_RESET_CONTROL CDRU_BASE_ADDR +#define CDRU_MISC_RESET_CONTROL_TS_RESET_N 16 +#define CDRU_MISC_RESET_CONTROL__CDRU_USBSS_RESET_N 14 +#define CDRU_MISC_RESET_CONTROL__CDRU_SATA_RESET_N_R 15 +#define CDRU_MISC_RESET_CONTROL__CDRU_MHB_RESET_N_R 13 +#define CDRU_MISC_RESET_CONTROL__CDRU_PCIE_RESET_N_R 3 +#define CDRU_MISC_RESET_CONTROL__CDRU_PM_RESET_N_R 2 +#define CDRU_MISC_RESET_CONTROL__CDRU_NITRO_RESET_N_R 1 + +#define CDRU_PROC_EVENT_CLEAR (CDRU_BASE_ADDR + 0x48) +#define CDRU_PROC_EVENT_CLEAR__IH0_CDRU_STANDBYWFIL2 0 +#define CDRU_PROC_EVENT_CLEAR__IH0_CDRU_STANDBYWFI 3 +#define CDRU_PROC_EVENT_CLEAR__IH1_CDRU_STANDBYWFIL2 5 +#define CDRU_PROC_EVENT_CLEAR__IH1_CDRU_STANDBYWFI 8 +#define CDRU_PROC_EVENT_CLEAR__IH2_CDRU_STANDBYWFIL2 10 +#define CDRU_PROC_EVENT_CLEAR__IH2_CDRU_STANDBYWFI 13 +#define CDRU_PROC_EVENT_CLEAR__IH3_CDRU_STANDBYWFIL2 15 +#define CDRU_PROC_EVENT_CLEAR__IH3_CDRU_STANDBYWFI 18 + +#define CDRU_CHIP_STRAP_CTRL (CDRU_BASE_ADDR + 0x50) +#define CDRU_CHIP_STRAP_CTRL__SOFTWARE_OVERRIDE 31 + +#define CDRU_CHIP_IO_PAD_CONTROL (CDRU_BASE_ADDR + 0x58) +#define CDRU_CHIP_IO_PAD_CONTROL__CDRU_IOMUX_FORCE_PDN_R 8 +#define CDRU_CHIP_IO_PAD_CONTROL__CDRU_IOMUX_FORCE_PAD_IN_R 0 + +#define CDRU_CHIP_STRAP_DATA_LSW (CDRU_BASE_ADDR + 0x5c) +#define CDRU_CHIP_STRAP_DATA_LSW__BISR_BYPASS_MODE 18 +#define CDRU_CHIP_STRAP_DATA_LSW__NIC_MODE_MASK BIT(8) +#define CDRU_CHIP_STRAP_DATA_LSW_PAD_USB_MODE BIT(26) + +#define CDRU_CHIP_STRAP_DATA (CDRU_BASE_ADDR + 0x5c) +#define CDRU_DDR0_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xb8) +#define CDRU_DDR1_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xbc) +#define CDRU_DDR2_CONTROL_OFFSET (CDRU_BASE_ADDR + 0xc0) +#define CRMU_SW_POR_RESET_CTRL (CDRU_BASE_ADDR + 0x100) + +#define CDRU_GENPLL2_CONTROL1 (CDRU_BASE_ADDR + 0x1b0) +#define CDRU_GENPLL2_CONTROL1__CHNL6_FS4_CLK BIT(11) +#define CDRU_GENPLL5_CONTROL1 (CDRU_BASE_ADDR + 0x24c) +#define CDRU_GENPLL5_CONTROL1__CHNL0_DME_CLK BIT(6) +#define CDRU_GENPLL5_CONTROL1__CHNL1_CRYPTO_AE_CLK BIT(7) +#define CDRU_GENPLL5_CONTROL1__CHNL2_RAID_AE_CLK BIT(8) + +#define CDRU_NITRO_CONTROL (CDRU_BASE_ADDR + 0x2c4) +#define CDRU_NITRO_CONTROL__CDRU_NITRO_SEC_MODE_R 20 +#define CDRU_NITRO_CONTROL__CDRU_NITRO_SEC_OVERRIDE_R 16 + +#define CDRU_MISC_CLK_ENABLE_CONTROL (CDRU_BASE_ADDR + 0x2c8) +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM2_CLK_EN_R 11 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM1_CLK_EN_R 10 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_EMEM0_CLK_EN_R 9 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SATA_CLK_EN_R 8 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_USBSS_CLK_EN_R 7 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_MHB_CLK_EN_R 6 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_HSLS_CLK_EN_R 5 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SCR_CLK_EN_R 4 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_FS4_CLK_EN_R 3 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_PCIE_CLK_EN_R 2 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_PM_CLK_EN_R 1 +#define CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_NITRO_CLK_EN_R 0 + +#define CDRU_CCN_REGISTER_CONTROL_1 (CDRU_BASE_ADDR + 0x324) +#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM0_BIT 6 +#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM1_BIT 5 +#define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_EMEM2_BIT 4 + +#define CDRU_CHIP_TOP_SPARE_REG0 (CDRU_BASE_ADDR + 0x378) +#define CDRU_CHIP_TOP_SPARE_REG1 (CDRU_BASE_ADDR + 0x37c) + +#define CENTRAL_TIMER_BASE (CRMU_CORE_BASE + 0x5000) +#define CENTRAL_TIMER_CTRL (CENTRAL_TIMER_BASE + 0x0) +#define CENTRAL_TIMER_GET_L (CENTRAL_TIMER_BASE + 0x4) +#define CENTRAL_TIMER_GET_L0 (CENTRAL_TIMER_BASE + 0x8) /* SCR STM */ +#define CENTRAL_TIMER_GET_L1 (CENTRAL_TIMER_BASE + 0xC) /* FS STM */ +#define CENTRAL_TIMER_GET_L2 (CENTRAL_TIMER_BASE + 0x10) /* iHost0 */ +#define CENTRAL_TIMER_GET_L3 (CENTRAL_TIMER_BASE + 0x14) /* iHost1 */ +#define CENTRAL_TIMER_GET_L4 (CENTRAL_TIMER_BASE + 0x18) /* iHost2 */ +#define CENTRAL_TIMER_GET_L5 (CENTRAL_TIMER_BASE + 0x1C) /* iHost3 */ +#define CENTRAL_TIMER_GET_H (CENTRAL_TIMER_BASE + 0x28) +#define CENTRAL_TIMER_SAT_TMR_ENA (CENTRAL_TIMER_BASE + 0x34) +#define CENTRAL_TIMER_GET_IHOST_ENA_BASE (CENTRAL_TIMER_GET_L2) + +#define CRMU_WDT_REGS_BASE (CRMU_CORE_BASE + 0x6000) + +#define CRMU_MAIL_BOX0 (CRMU_CORE_BASE + 0x8024) +#define CRMU_MAIL_BOX1 (CRMU_CORE_BASE + 0x8028) +#define CRMU_READ_MAIL_BOX0 (CRMU_CORE_BASE + 0x802c) +#define CRMU_READ_MAIL_BOX1 (CRMU_CORE_BASE + 0x8030) +#define AP_TO_SCP_MAILBOX1 CRMU_MAIL_BOX1 +#define SCP_TO_AP_MAILBOX1 CRMU_READ_MAIL_BOX1 +#define CRMU_IHOST_POWER_CONFIG (CRMU_CORE_BASE + 0x8038) +#define CRMU_RESET_EVENT_LOG (CRMU_CORE_BASE + 0x8064) +#define CRMU_SOFT_RESET_CTRL (CRMU_CORE_BASE + 0x8090) +#define CRMU_SOFT_RESET_CTRL__SOFT_PWR_UP_RST 0 +#define CRMU_SOFT_RESET_CTRL__SOFT_SYS_RST 1 +#define CRMU_SPARE_REG_0 (CRMU_CORE_BASE + 0x80b8) +#define CRMU_SPARE_REG_1 (CRMU_CORE_BASE + 0x80bc) +#define CRMU_SPARE_REG_2 (CRMU_CORE_BASE + 0x80c0) +#define CRMU_SPARE_REG_3 (CRMU_CORE_BASE + 0x80c4) +#define CRMU_SPARE_REG_4 (CRMU_CORE_BASE + 0x80c8) +#define CRMU_SPARE_REG_5 (CRMU_CORE_BASE + 0x80cc) +#define CRMU_CORE_ADDR_RANGE0_LOW (CRMU_CORE_BASE + 0x8c30) +#define CRMU_CORE_ADDR_RANGE1_LOW (CRMU_CORE_BASE + 0x8c38) +#define CRMU_CORE_ADDR_RANGE2_LOW (CRMU_CORE_BASE + 0x8c40) +#define CRMU_IHOST_SW_PERSISTENT_REG0 (CRMU_CORE_BASE + 0x8c54) +#define CRMU_IHOST_SW_PERSISTENT_REG1 (CRMU_CORE_BASE + 0x8c58) +#define CRMU_IHOST_SW_PERSISTENT_REG2 (CRMU_CORE_BASE + 0x8c5c) +#define CRMU_IHOST_SW_PERSISTENT_REG3 (CRMU_CORE_BASE + 0x8c60) +#define CRMU_IHOST_SW_PERSISTENT_REG4 (CRMU_CORE_BASE + 0x8c64) +#define CRMU_IHOST_SW_PERSISTENT_REG5 (CRMU_CORE_BASE + 0x8c68) +#define CRMU_IHOST_SW_PERSISTENT_REG6 (CRMU_CORE_BASE + 0x8c6c) +#define CRMU_IHOST_SW_PERSISTENT_REG7 (CRMU_CORE_BASE + 0x8c70) +#define CRMU_BBL_AUTH_CHECK (CRMU_CORE_BASE + 0x8c78) +#define CRMU_SOTP_NEUTRALIZE_ENABLE (CRMU_CORE_BASE + 0x8c84) +#define CRMU_IHOST_SW_PERSISTENT_REG8 (CRMU_CORE_BASE + 0x8c88) +#define CRMU_IHOST_SW_PERSISTENT_REG9 (CRMU_CORE_BASE + 0x8c8c) +#define CRMU_IHOST_SW_PERSISTENT_REG10 (CRMU_CORE_BASE + 0x8c90) +#define CRMU_IHOST_SW_PERSISTENT_REG11 (CRMU_CORE_BASE + 0x8c94) + +#define CNT_CONTROL_BASE (CRMU_CORE_BASE + 0x9000) +#define CNTCR (CNT_CONTROL_BASE) +#define CNTCR__EN BIT(0) + +#define SPRU_BBL_WDATA (CRMU_CORE_BASE + 0xa000) +#define SPRU_BBL_CMD (CRMU_CORE_BASE + 0xa004) +#define SPRU_BBL_CMD__IND_SOFT_RST_N 10 +#define SPRU_BBL_CMD__IND_WR 11 +#define SPRU_BBL_CMD__BBL_ADDR_R 0 +#define SPRU_BBL_CMD__IND_RD 12 +#define SPRU_BBL_CMD__BBL_ADDR_R 0 +#define SPRU_BBL_STATUS (CRMU_CORE_BASE + 0xa008) +#define SPRU_BBL_STATUS__ACC_DONE 0 +#define SPRU_BBL_RDATA (CRMU_CORE_BASE + 0xa00c) + +#endif /* CRMU_DEF_H */ diff --git a/plat/brcm/board/stingray/include/ddr_init.h b/plat/brcm/board/stingray/include/ddr_init.h new file mode 100644 index 0000000..0c135b1 --- /dev/null +++ b/plat/brcm/board/stingray/include/ddr_init.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDR_INIT_H +#define DDR_INIT_H + +#include <fru.h> + +#pragma weak ddr_initialize +#pragma weak ddr_secure_region_config +#pragma weak ddr_info_save +#pragma weak get_active_ddr_channel +#pragma weak is_warmboot + +void ddr_initialize(struct ddr_info *ddr) +{ +} + +void ddr_secure_region_config(uint64_t start, uint64_t end) +{ +} + +void ddr_info_save(void) +{ +} + +unsigned char get_active_ddr_channel(void) +{ + return 0; +} + +static inline unsigned int is_warmboot(void) +{ + return 0; +} +#endif diff --git a/plat/brcm/board/stingray/include/fsx.h b/plat/brcm/board/stingray/include/fsx.h new file mode 100644 index 0000000..c52ff0a --- /dev/null +++ b/plat/brcm/board/stingray/include/fsx.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSX_H +#define FSX_H + +#include <stdbool.h> + +typedef enum FSX_TYPE { + eFS4_RAID, + eFS4_CRYPTO, + eFS6_PKI, +} eFSX_TYPE; + +void fsx_init(eFSX_TYPE fsx_type, + unsigned int ring_count, + unsigned int dme_count, + unsigned int ae_count, + unsigned int start_stream_id, + unsigned int msi_dev_id, + uintptr_t idm_io_control_direct, + uintptr_t idm_reset_control, + uintptr_t base, + uintptr_t dme_base); + +void fsx_meminit(const char *name, + uintptr_t idm_io_control_direct, + uintptr_t idm_io_status); + +void fs4_disable_clocks(bool disable_sram, + bool disable_crypto, + bool disable_raid); + +#endif /* FSX_H */ diff --git a/plat/brcm/board/stingray/include/ihost_pm.h b/plat/brcm/board/stingray/include/ihost_pm.h new file mode 100644 index 0000000..83493ab --- /dev/null +++ b/plat/brcm/board/stingray/include/ihost_pm.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IHOST_PM +#define IHOST_PM + +#include <stdint.h> + +#define CLUSTER_POWER_ON 0x1 +#define CLUSTER_POWER_OFF 0x0 + +void ihost_power_on_cluster(u_register_t mpidr); +void ihost_power_on_secondary_core(u_register_t mpidr, uint64_t rvbar); +void ihost_enable_satellite_timer(unsigned int cluster_id); + +#endif diff --git a/plat/brcm/board/stingray/include/iommu.h b/plat/brcm/board/stingray/include/iommu.h new file mode 100644 index 0000000..e7b2985 --- /dev/null +++ b/plat/brcm/board/stingray/include/iommu.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IOMMU_H +#define IOMMU_H + +enum iommu_domain { + PCIE_PAXC, + DOMAIN_CRMU, +}; + +void arm_smmu_create_identity_map(enum iommu_domain dom); +void arm_smmu_reserve_secure_cntxt(void); +void arm_smmu_enable_secure_client_port(void); + +#endif /* IOMMU_H */ diff --git a/plat/brcm/board/stingray/include/ncsi.h b/plat/brcm/board/stingray/include/ncsi.h new file mode 100644 index 0000000..04dd640 --- /dev/null +++ b/plat/brcm/board/stingray/include/ncsi.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NCSI_H +#define NCSI_H + +/* + * There are 10 registers for NCSI IO drivers. + */ +#define NITRO_NCSI_IOPAD_CONTROL_NUM 10 +#define NITRO_NCSI_IOPAD_CONTROL_BASE 0x60e05080 + +/* + * NCSI IO Drive strength + * 000 - Drives 2mA + * 001 - Drives 4mA + * 010 - Drives 6mA + * 011 - Drives 8mA + * 100 - Drives 10mA + * 101 - Drives 12mA + * 110 - Drives 14mA + * 111 - Drives 16mA + */ +#define PAD_SELX_VALUE(selx) ((selx) << 1) +#define PAD_SELX_MASK (0x7 << 1) + +void brcm_stingray_ncsi_init(void); + +#endif diff --git a/plat/brcm/board/stingray/include/paxb.h b/plat/brcm/board/stingray/include/paxb.h new file mode 100644 index 0000000..c64c8a6 --- /dev/null +++ b/plat/brcm/board/stingray/include/paxb.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PAXB_H +#define PAXB_H + +/* total number of PCIe cores */ +#define NUM_OF_SR_PCIE_CORES 8 +#define NUM_OF_NS3Z_PCIE_CORES 1 + +/* + * List of PCIe core and PAXB wrapper memory power registers + */ +#define PCIE_CORE_BASE 0x40000800 +#define PCIE_CORE_SOFT_RST_CFG_BASE (PCIE_CORE_BASE + 0x40) +#define PCIE_CORE_SOFT_RST 0x1 +#define PCIE_CORE_ISO_CFG_BASE (PCIE_CORE_BASE + 0x54) +#define PCIE_CORE_MEM_ISO 0x2 +#define PCIE_CORE_ISO 0x1 + +#define PCIE_CORE_MEM_PWR_BASE (PCIE_CORE_BASE + 0x58) +#define PCIE_PAXB_MEM_PWR_BASE (PCIE_CORE_BASE + 0x5c) +#define PCIE_CORE_PMI_CFG_BASE (PCIE_CORE_BASE + 0x64) +#define PCIE_CORE_RESERVED_CFG (PCIE_CORE_BASE + 0x6c) +#define PCIE_CORE_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x74) +#define PCIE_PAXB_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x78) +#define PCIE_CORE_PWR_OFFSET 0x100 + +#define SR_A0_DEVICE_ID 0xd713 +#define SR_B0_DEVICE_ID 0xd714 +/* TODO: Modify device ID once available */ +#define NS3Z_DEVICE_ID 0xd715 + +/* FIXME: change link speed to GEN3 when it's ready */ +#define GEN1_LINK_SPEED 1 +#define GEN2_LINK_SPEED 2 +#define GEN3_LINK_SPEED 3 + +typedef struct { + uint32_t type; + uint32_t device_id; + uint32_t pipemux_idx; + uint32_t num_cores; + int (*pipemux_init)(void); + int (*phy_init)(void); + int (*core_needs_enable)(unsigned int core_idx); + unsigned int (*get_link_width)(unsigned int core_idx); + unsigned int (*get_link_speed)(void); +} paxb_cfg; + +enum paxb_type { + PAXB_SR, + PAXB_NS3Z, +}; + +extern const paxb_cfg *paxb; + +#ifdef USE_PAXB +void paxb_init(void); +void paxb_rc_cfg_write(unsigned int core_idx, unsigned int where, + uint32_t val); +unsigned int paxb_rc_cfg_read(unsigned int core_idx, unsigned int where); +int pcie_core_needs_enable(unsigned int core_idx); +const paxb_cfg *paxb_get_sr_config(void); +#else +static inline void paxb_init(void) +{ +} +#endif + +#endif /* PAXB_H */ diff --git a/plat/brcm/board/stingray/include/paxc.h b/plat/brcm/board/stingray/include/paxc.h new file mode 100644 index 0000000..ae1af2e --- /dev/null +++ b/plat/brcm/board/stingray/include/paxc.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PAXC_H +#define PAXC_H + +#ifdef USE_PAXC +void paxc_init(void); +void paxc_mhb_ns_init(void); +#else +static inline void paxc_init(void) +{ +} + +static inline void paxc_mhb_ns_init(void) +{ +} +#endif + +#endif /* PAXC_H */ diff --git a/plat/brcm/board/stingray/include/plat_macros.S b/plat/brcm/board/stingray/include/plat_macros.S new file mode 100644 index 0000000..dccd54a --- /dev/null +++ b/plat/brcm/board/stingray/include/plat_macros.S @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +/* --------------------------------------------- + * The below required platform porting macro + * prints out relevant registers whenever an + * unhandled exception is taken in BL31. + * --------------------------------------------- + */ +.macro plat_crash_print_regs + nop +.endm + +/* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31. + * --------------------------------------------- + */ +.macro plat_print_gic_regs + nop + /*TBD-STINGRAY*/ +.endm + +/* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL3-1. + * ------------------------------------------------ + */ +.macro plat_print_interconnect_regs + nop + /*TBD-STINGRAY*/ +.endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/brcm/board/stingray/include/platform_def.h b/plat/brcm/board/stingray/include/platform_def.h new file mode 100644 index 0000000..4742124 --- /dev/null +++ b/plat/brcm/board/stingray/include/platform_def.h @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2015-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <plat/common/common_def.h> + +#include <brcm_def.h> +#include "sr_def.h" +#include <cmn_plat_def.h> + +/* + * Most platform porting definitions provided by included headers + */ +#define PLAT_BRCM_SCP_TZC_DRAM1_SIZE ULL(0x0) + +/* + * Required by standard platform porting definitions + */ +#define PLATFORM_CLUSTER0_CORE_COUNT 2 +#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_CLUSTER2_CORE_COUNT 2 +#define PLATFORM_CLUSTER3_CORE_COUNT 2 + +#define BRCM_SYSTEM_COUNT 1 +#define BRCM_CLUSTER_COUNT 4 + +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ + PLATFORM_CLUSTER1_CORE_COUNT+ \ + PLATFORM_CLUSTER2_CORE_COUNT+ \ + PLATFORM_CLUSTER3_CORE_COUNT) + +#define PLAT_NUM_PWR_DOMAINS (BRCM_SYSTEM_COUNT + \ + BRCM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 + +/* TBD-STINGRAY */ +#define CACHE_WRITEBACK_SHIFT 6 +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* TBD-STINGRAY */ +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 + +#define BL1_PLATFORM_STACK_SIZE 0x3300 +#define BL2_PLATFORM_STACK_SIZE 0xc000 +#define BL11_PLATFORM_STACK_SIZE 0x2b00 +#define DEFAULT_PLATFORM_STACK_SIZE 0x400 +#if IMAGE_BL1 +# define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE +#else +#if IMAGE_BL2 +#ifdef USE_BL1_RW +# define PLATFORM_STACK_SIZE BL2_PLATFORM_STACK_SIZE +#else +# define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE +#endif +#else +#if IMAGE_BL11 +# define PLATFORM_STACK_SIZE BL11_PLATFORM_STACK_SIZE +#else +# define PLATFORM_STACK_SIZE DEFAULT_PLATFORM_STACK_SIZE +#endif +#endif +#endif + +#define PLAT_BRCM_TRUSTED_SRAM_BASE 0x66D00000 +#define PLAT_BRCM_TRUSTED_SRAM_SIZE 0x00040000 + +#ifdef RUN_BL1_FROM_QSPI /* BL1 XIP from QSPI */ +# define PLAT_BRCM_TRUSTED_ROM_BASE QSPI_BASE_ADDR +#elif RUN_BL1_FROM_NAND /* BL1 XIP from NAND */ +# define PLAT_BRCM_TRUSTED_ROM_BASE NAND_BASE_ADDR +#else /* BL1 executed in ROM */ +# define PLAT_BRCM_TRUSTED_ROM_BASE ROM_BASE_ADDR +#endif +#define PLAT_BRCM_TRUSTED_ROM_SIZE 0x00040000 + +/******************************************************************************* + * BL1 specific defines. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_BRCM_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_BRCM_TRUSTED_ROM_BASE \ + + PLAT_BRCM_TRUSTED_ROM_SIZE) + +/* + * Put BL1 RW at the beginning of the Trusted SRAM. + */ +#define BL1_RW_BASE (BRCM_BL_RAM_BASE) +#define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000) + +#define BL11_RW_BASE BL1_RW_LIMIT +#define BL11_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ + PLAT_BRCM_TRUSTED_SRAM_SIZE) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +#if RUN_BL2_FROM_QSPI /* BL2 XIP from QSPI */ +#define BL2_BASE QSPI_BASE_ADDR +#define BL2_LIMIT (BL2_BASE + 0x40000) +#define BL2_RW_BASE BL1_RW_LIMIT +#define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ + PLAT_BRCM_TRUSTED_SRAM_SIZE) +#elif RUN_BL2_FROM_NAND /* BL2 XIP from NAND */ +#define BL2_BASE NAND_BASE_ADDR +#define BL2_LIMIT (BL2_BASE + 0x40000) +#define BL2_RW_BASE BL1_RW_LIMIT +#define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ + PLAT_BRCM_TRUSTED_SRAM_SIZE) +#else +#define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) +#define BL2_LIMIT (BRCM_BL_RAM_BASE + BRCM_BL_RAM_SIZE) +#endif + +/* + * BL1 persistent area in internal SRAM + * This area will increase as more features gets into BL1 + */ +#define BL1_PERSISTENT_DATA_SIZE 0x2000 + +/* To reduce BL2 runtime footprint, we can re-use some BL1_RW area */ +#define BL1_RW_RECLAIM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \ + BL1_PERSISTENT_DATA_SIZE) + +/******************************************************************************* + * BL3-1 specific defines. + ******************************************************************************/ +/* Max Size of BL31 (in DRAM) */ +#define PLAT_BRCM_MAX_BL31_SIZE 0x30000 + +#ifdef USE_DDR +#define BL31_BASE BRCM_AP_TZC_DRAM1_BASE + +#define BL31_LIMIT (BRCM_AP_TZC_DRAM1_BASE + \ + PLAT_BRCM_MAX_BL31_SIZE) +#else +/* Put BL3-1 at the end of external on-board SRAM connected as NOR flash */ +#define BL31_BASE (NOR_BASE_ADDR + NOR_SIZE - \ + PLAT_BRCM_MAX_BL31_SIZE) + +#define BL31_LIMIT (NOR_BASE_ADDR + NOR_SIZE) +#endif + +#define SECURE_DDR_END_ADDRESS BL31_LIMIT + +#ifdef NEED_SCP_BL2 +#define SCP_BL2_BASE BL31_BASE +#define PLAT_MAX_SCP_BL2_SIZE 0x9000 +#define PLAT_SCP_COM_SHARED_MEM_BASE (CRMU_SHARED_SRAM_BASE) +/* dummy defined */ +#define PLAT_BRCM_MHU_BASE 0x0 +#endif + +#define SECONDARY_CPU_SPIN_BASE_ADDR BRCM_SHARED_RAM_BASE + +/* Generic system timer counter frequency */ +#ifndef SYSCNT_FREQ +#define SYSCNT_FREQ (125 * 1000 * 1000) +#endif + +/* + * Enable the BL32 definitions, only when optee os is selected as secure + * payload (BL32). + */ +#ifdef SPD_opteed +/* + * Reserved Memory Map : SHMEM & TZDRAM. + * + * +--------+----------+ 0x8D000000 + * | SHMEM (NS) | 16MB + * +-------------------+ 0x8E000000 + * | | TEE_RAM(S)| 4MB + * + TZDRAM +----------+ 0x8E400000 + * | | TA_RAM(S) | 12MB + * +-------------------+ 0x8F000000 + * | BL31 Binary (S) | 192KB + * +-------------------+ 0x8F030000 + */ + +#define BL32_VA_SIZE (4 * 1024 * 1024) +#define BL32_BASE (0x8E000000) +#define BL32_LIMIT (BL32_BASE + BL32_VA_SIZE) +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE BL32_VA_SIZE +#endif + +#ifdef SPD_opteed + #define SECURE_DDR_BASE_ADDRESS BL32_BASE +#else + #define SECURE_DDR_BASE_ADDRESS BL31_BASE +#endif +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ + +#define MAX_XLAT_TABLES 7 + +#define PLAT_BRCM_MMAP_ENTRIES 10 + +#define MAX_MMAP_REGIONS (PLAT_BRCM_MMAP_ENTRIES + \ + BRCM_BL_REGIONS) + +#ifdef USE_DDR +#ifdef BL33_OVERRIDE_LOAD_ADDR +#define PLAT_BRCM_NS_IMAGE_OFFSET BL33_OVERRIDE_LOAD_ADDR +#else +/* + * BL3-3 image starting offset. + * Putting start of DRAM as of now. + */ +#define PLAT_BRCM_NS_IMAGE_OFFSET 0x80000000 +#endif /* BL33_OVERRIDE_LOAD_ADDR */ +#else +/* + * BL3-3 image starting offset. + * Putting start of external on-board SRAM as of now. + */ +#define PLAT_BRCM_NS_IMAGE_OFFSET NOR_BASE_ADDR +#endif /* USE_DDR */ +/****************************************************************************** + * Required platform porting definitions common to all BRCM platforms + *****************************************************************************/ + +#define MAX_IO_DEVICES 5 +#define MAX_IO_HANDLES 6 + +#define PRIMARY_CPU 0 + +/* GIC Parameter */ +#define PLAT_BRCM_GICD_BASE GIC500_BASE +#define PLAT_BRCM_GICR_BASE (GIC500_BASE + 0x200000) + +/* Define secure interrupt as per Group here */ +#define PLAT_BRCM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SPI_0, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +#define PLAT_BRCM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ + GIC_INTR_CFG_EDGE), \ + +/* + *CCN 502 related constants. + */ +#define PLAT_BRCM_CLUSTER_COUNT 4 /* Number of RN-F Masters */ +#define PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP CLUSTER0_NODE_ID, CLUSTER1_NODE_ID, CLUSTER2_NODE_ID, CLUSTER3_NODE_ID +#define CCN_SIZE 0x1000000 +#define CLUSTER0_NODE_ID 1 +#define CLUSTER1_NODE_ID 7 +#define CLUSTER2_NODE_ID 9 +#define CLUSTER3_NODE_ID 15 + +#endif diff --git a/plat/brcm/board/stingray/include/platform_sotp.h b/plat/brcm/board/stingray/include/platform_sotp.h new file mode 100644 index 0000000..0389f38 --- /dev/null +++ b/plat/brcm/board/stingray/include/platform_sotp.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_SOTP_H +#define PLATFORM_SOTP_H + +#define SOTP_DEVICE_SECURE_CFG0_ROW 17 +#define SOTP_DEVICE_SECURE_CFG1_ROW 18 +#define SOTP_DEVICE_SECURE_CFG2_ROW 19 +#define SOTP_DEVICE_SECURE_CFG3_ROW 20 +#define SOTP_BRCM_SOFTWARE_CFG0_ROW 21 +#define SOTP_BRCM_SOFTWARE_CFG1_ROW 22 +#define SOTP_BRCM_SOFTWARE_CFG2_ROW 23 +#define SOTP_BRCM_SOFTWARE_CFG3_ROW 24 +#define SOTP_CUSTOMER_ID_CFG0_ROW 25 +#define SOTP_CUSTOMER_ID_CFG1_ROW 26 +#define SOTP_CUSTOMER_ID_CFG2_ROW 27 +#define SOTP_CUSTOMER_ID_CFG3_ROW 28 +#define SOTP_CUSTOMER_DEV_CFG0_ROW 29 +#define SOTP_CUSTOMER_DEV_CFG1_ROW 30 +#define SOTP_CUSTOMER_DEV_CFG2_ROW 31 +#define SOTP_CUSTOMER_DEV_CFG3_ROW 32 +#define SOTP_DAUTH_ROW 33 +#define SOTP_K_HMAC_ROW 45 +#define SOTP_K_AES_ROW 57 +#define SOTP_NVCOUNTER_ROW 69 + +#define SOTP_BRCM_CFG_ECC_ERROR_MASK 0x100000 +#define SOTP_DAUTH_ECC_ERROR_MASK 0x800000 +#define SOTP_K_HMAC_ECC_ERROR_MASK 0x1000000 +#define SOTP_K_AES_ECC_ERROR_MASK 0x2000000 + +#endif diff --git a/plat/brcm/board/stingray/include/platform_usb.h b/plat/brcm/board/stingray/include/platform_usb.h new file mode 100644 index 0000000..5b5309f --- /dev/null +++ b/plat/brcm/board/stingray/include/platform_usb.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2019 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_USB_H +#define PLATFORM_USB_H + +#include <platform_def.h> + +#define USB3_DRD BIT(0U) +#define USB3H_USB2DRD BIT(1U) + +extern const unsigned int xhc_portsc_reg_offset[MAX_USB_PORTS]; + +void xhci_phy_init(void); + +#endif /* PLATFORM_USB_H */ diff --git a/plat/brcm/board/stingray/include/scp_cmd.h b/plat/brcm/board/stingray/include/scp_cmd.h new file mode 100644 index 0000000..806ef56 --- /dev/null +++ b/plat/brcm/board/stingray/include/scp_cmd.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_CMD_H +#define SCP_SMD_H + +#include <stdint.h> + +typedef struct { + int cmd; + int completed; + int ret; +} crmu_response_t; + + +#define SCP_CMD_MASK 0xffff +#define SCP_CMD_DEFAULT_TIMEOUT_US 1000 +#define SCP_CMD_SCP_BOOT_TIMEOUT_US 5000 + +int scp_send_cmd(uint32_t cmd, uint32_t param, uint32_t timeout); + +#endif diff --git a/plat/brcm/board/stingray/include/scp_utils.h b/plat/brcm/board/stingray/include/scp_utils.h new file mode 100644 index 0000000..c39b18c --- /dev/null +++ b/plat/brcm/board/stingray/include/scp_utils.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_UTILS_H +#define SCP_UTILS_H + +#include <common/bl_common.h> +#include <lib/mmio.h> + +#include <m0_cfg.h> + +int plat_bcm_bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info); + +bool is_crmu_alive(void); +bool bcm_scp_issue_sys_reset(void); + +#define SCP_READ_CFG(cfg) mmio_read_32(CRMU_CFG_BASE + \ + offsetof(M0CFG, cfg)) +#define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \ + offsetof(M0CFG, cfg), value) + +#define SCP_READ_CFG16(cfg) mmio_read_16(CRMU_CFG_BASE + \ + offsetof(M0CFG, cfg)) +#define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \ + offsetof(M0CFG, cfg), value) + +#define SCP_READ_CFG8(cfg) mmio_read_8(CRMU_CFG_BASE + \ + offsetof(M0CFG, cfg)) +#define SCP_WRITE_CFG8(cfg, value) mmio_write_8(CRMU_CFG_BASE + \ + offsetof(M0CFG, cfg), value) +#endif diff --git a/plat/brcm/board/stingray/include/sdio.h b/plat/brcm/board/stingray/include/sdio.h new file mode 100644 index 0000000..e08904e --- /dev/null +++ b/plat/brcm/board/stingray/include/sdio.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SDIO_H +#define SDIO_H + +#include <stdbool.h> + +#define SR_IPROC_SDIO0_CFG_BASE 0x689006e4 +#define SR_IPROC_SDIO0_SID_BASE 0x68900b00 +#define SR_IPROC_SDIO0_PAD_BASE 0x68a4017c +#define SR_IPROC_SDIO0_IOCTRL_BASE 0x68e02408 + +#define SR_IPROC_SDIO1_CFG_BASE 0x68900734 +#define SR_IPROC_SDIO1_SID_BASE 0x68900b08 +#define SR_IPROC_SDIO1_PAD_BASE 0x68a401b4 +#define SR_IPROC_SDIO1_IOCTRL_BASE 0x68e03408 + +#define NS3Z_IPROC_SDIO0_CFG_BASE 0x68a20540 +#define NS3Z_IPROC_SDIO0_SID_BASE 0x68900b00 +#define NS3Z_IPROC_SDIO0_TP_OUT_SEL 0x68a20308 +#define NS3Z_IPROC_SDIO0_PAD_BASE 0x68a20500 +#define NS3Z_IPROC_SDIO0_IOCTRL_BASE 0x68e02408 + +#define PHY_BYPASS BIT(14) +#define LEGACY_EN BIT(31) +#define PHY_DISABLE (LEGACY_EN | PHY_BYPASS) + +#define NS3Z_IPROC_SDIO1_CFG_BASE 0x68a30540 +#define NS3Z_IPROC_SDIO1_SID_BASE 0x68900b08 +#define NS3Z_IPROC_SDIO1_PAD_BASE 0x68a30500 +#define NS3Z_IPROC_SDIO1_IOCTRL_BASE 0x68e03408 + +#define ICFG_SDIO_CAP0 0x10 +#define ICFG_SDIO_CAP1 0x14 +#define ICFG_SDIO_STRAPSTATUS_0 0x0 +#define ICFG_SDIO_STRAPSTATUS_1 0x4 +#define ICFG_SDIO_STRAPSTATUS_2 0x8 +#define ICFG_SDIO_STRAPSTATUS_3 0xc +#define ICFG_SDIO_STRAPSTATUS_4 0x18 + +#define ICFG_SDIO_SID_ARADDR 0x0 +#define ICFG_SDIO_SID_AWADDR 0x4 + +#define ICFG_SDIOx_CAP0__SLOT_TYPE_MASK 0x3 +#define ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT 27 +#define ICFG_SDIOx_CAP0__INT_MODE_SHIFT 26 +#define ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT 25 +#define ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT 24 +#define ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT 23 +#define ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT 22 +#define ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT 21 +#define ICFG_SDIOx_CAP0__SDMA_SHIFT 20 +#define ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT 19 +#define ICFG_SDIOx_CAP0__ADMA2_SHIFT 18 +#define ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT 17 +#define ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_MASK 0x3 +#define ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT 15 +#define ICFG_SDIOx_CAP0__BASE_CLK_FREQ_MASK 0xff +#define ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT 7 +#define ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT 6 +#define ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_MASK 0x3f +#define ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT 0 + +#define ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT 22 +#define ICFG_SDIOx_CAP1__SPI_MODE_SHIFT 21 +#define ICFG_SDIOx_CAP1__CLK_MULT_MASK 0xff +#define ICFG_SDIOx_CAP1__CLK_MULT_SHIFT 13 +#define ICFG_SDIOx_CAP1__RETUNING_MODE_MASK 0x3 +#define ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT 11 +#define ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT 10 +#define ICFG_SDIOx_CAP1__TIME_RETUNE_MASK 0xf +#define ICFG_SDIOx_CAP1__TIME_RETUNE_SHIFT 6 +#define ICFG_SDIOx_CAP1__DRIVER_D_SHIFT 5 +#define ICFG_SDIOx_CAP1__DRIVER_C_SHIFT 4 +#define ICFG_SDIOx_CAP1__DRIVER_A_SHIFT 3 +#define ICFG_SDIOx_CAP1__DDR50_SHIFT 2 +#define ICFG_SDIOx_CAP1__SDR104_SHIFT 1 +#define ICFG_SDIOx_CAP1__SDR50_SHIFT 0 + +#ifdef USE_DDR +#define SDIO_DMA 1 +#else +#define SDIO_DMA 0 +#endif + +#define SDIO0_CAP0_CFG \ + (0x1 << ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT) \ + | (0x0 << ICFG_SDIOx_CAP0__INT_MODE_SHIFT) \ + | (0x0 << ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT) \ + | (SDIO_DMA << ICFG_SDIOx_CAP0__SDMA_SHIFT) \ + | (SDIO_DMA << ICFG_SDIOx_CAP0__ADMA2_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT) \ + | (0x2 << ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT) \ + | (0xc8 << ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT) \ + | (0x30 << ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT) + +#define SDIO0_CAP1_CFG \ + (0x1 << ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__SPI_MODE_SHIFT)\ + | (0x0 << ICFG_SDIOx_CAP1__CLK_MULT_SHIFT)\ + | (0x2 << ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT)\ + | (0x0 << ICFG_SDIOx_CAP1__DRIVER_D_SHIFT)\ + | (0x0 << ICFG_SDIOx_CAP1__DRIVER_C_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__DRIVER_A_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__DDR50_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__SDR104_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__SDR50_SHIFT) + +#define SDIO1_CAP0_CFG \ + (0x0 << ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT) \ + | (0x0 << ICFG_SDIOx_CAP0__INT_MODE_SHIFT) \ + | (0x0 << ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT) \ + | (SDIO_DMA << ICFG_SDIOx_CAP0__SDMA_SHIFT) \ + | (SDIO_DMA << ICFG_SDIOx_CAP0__ADMA2_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT) \ + | (0x2 << ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT) \ + | (0xc8 << ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT) \ + | (0x1 << ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT) \ + | (0x30 << ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT) + +#define SDIO1_CAP1_CFG \ + (0x1 << ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__SPI_MODE_SHIFT)\ + | (0x0 << ICFG_SDIOx_CAP1__CLK_MULT_SHIFT)\ + | (0x2 << ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT)\ + | (0x0 << ICFG_SDIOx_CAP1__DRIVER_D_SHIFT)\ + | (0x0 << ICFG_SDIOx_CAP1__DRIVER_C_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__DRIVER_A_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__DDR50_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__SDR104_SHIFT)\ + | (0x1 << ICFG_SDIOx_CAP1__SDR50_SHIFT) + +#define PAD_SDIO_CLK 0x4 +#define PAD_SDIO_DATA0 0x8 +#define PAD_SDIO_DATA1 0xc +#define PAD_SDIO_DATA2 0x10 +#define PAD_SDIO_DATA3 0x14 +#define PAD_SDIO_DATA4 0x18 +#define PAD_SDIO_DATA5 0x1c +#define PAD_SDIO_DATA6 0x20 +#define PAD_SDIO_DATA7 0x24 +#define PAD_SDIO_CMD 0x28 + +/* 12mA Drive strength*/ +#define PAD_SDIO_SELX (0x5 << 1) +#define PAD_SDIO_SRC (1 << 0) +#define PAD_SDIO_MASK (0xF << 0) +#define PAD_SDIO_VALUE (PAD_SDIO_SELX | PAD_SDIO_SRC) + +/* + * SDIO_PRESETVAL0 + * + * Each 13 Bit filed consists: + * drivestrength - 12:11 + * clkgensel - b10 + * sdkclkfreqsel - 9:0 + * Field Bit(s) Description + * ============================================================ + * SDR25_PRESET 25:13 Preset Value for SDR25 + * SDR50_PRESET 12:0 Preset Value for SDR50 + */ +#define SDIO_PRESETVAL0 0x01005001 + +/* + * SDIO_PRESETVAL1 + * + * Each 13 Bit filed consists: + * drivestrength - 12:11 + * clkgensel - b10 + * sdkclkfreqsel - 9:0 + * Field Bit(s) Description + * ============================================================ + * SDR104_PRESET 25:13 Preset Value for SDR104 + * SDR12_PRESET 12:0 Preset Value for SDR12 + */ +#define SDIO_PRESETVAL1 0x03000004 + +/* + * SDIO_PRESETVAL2 + * + * Each 13 Bit filed consists: + * drivestrength - 12:11 + * clkgensel - b10 + * sdkclkfreqsel - 9:0 + * Field Bit(s) Description + * ============================================================ + * HIGH_SPEED_PRESET 25:13 Preset Value for High Speed + * INIT_PRESET 12:0 Preset Value for Initialization + */ +#define SDIO_PRESETVAL2 0x010040FA + +/* + * SDIO_PRESETVAL3 + * + * Each 13 Bit filed consists: + * drivestrength - 12:11 + * clkgensel - b10 + * sdkclkfreqsel - 9:0 + * Field Bit(s) Description + * ============================================================ + * DDR50_PRESET 25:13 Preset Value for DDR50 + * DEFAULT_PRESET 12:0 Preset Value for Default Speed + */ +#define SDIO_PRESETVAL3 0x01004004 + +/* + * SDIO_PRESETVAL4 + * + * Field Bit(s) Description + * ============================================================ + * FORCE_USE_IP_TUNE_CLK 30 Force use IP clock + * TUNING_COUNT 29:24 Tuning count + * OVERRIDE_1P8V 23:16 + * OVERRIDE_3P3V 15:8 + * OVERRIDE_3P0V 7:0 + */ +#define SDIO_PRESETVAL4 0x20010101 + +#define SDIO_SID_SHIFT 5 + +typedef struct { + uintptr_t cfg_base; + uintptr_t sid_base; + uintptr_t io_ctrl_base; + uintptr_t pad_base; +} SDIO_CFG; + +void brcm_stingray_sdio_init(void); + +#endif /* SDIO_H */ diff --git a/plat/brcm/board/stingray/include/sr_def.h b/plat/brcm/board/stingray/include/sr_def.h new file mode 100644 index 0000000..277836e --- /dev/null +++ b/plat/brcm/board/stingray/include/sr_def.h @@ -0,0 +1,624 @@ +/* + * Copyright (c) 2016-2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SR_DEF_H +#define SR_DEF_H + +#ifndef __ASSEMBLER__ +#include <lib/mmio.h> +#endif + +#include <common/interrupt_props.h> +#include <drivers/arm/gic_common.h> + +#include <crmu_def.h> + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define BRCM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) + +#define MHB_BASE_ADDR 0x60000000 +#define PLAT_BRCM_CCN_BASE 0x61000000 +#define CORESIGHT_BASE_ADDR 0x62000000 +#define SMMU_BASE 0x64000000 + +/* memory map entries*/ +/* Grouping block device for bigger MMU region */ +/* covers MHB, CNN, coresight, GIC, MMU, APB, CRMU */ +#define PERIPH0_BASE MHB_BASE_ADDR +#define PERIPH0_SIZE 0x06d00000 + +#define PERIPH1_BASE 0x66d80000 +#define PERIPH1_SIZE 0x00f80000 + +#define HSLS_BASE_ADDR 0x68900000 +#define HSLS_SIZE 0x04500000 + +#define GIC500_BASE 0x63c00000 +#define GIC500_SIZE 0x400000 + +/******************************************************************************* + * CCN related constants + ******************************************************************************/ +#define OLY_MN_REGISTERS_NODE0_SECURE_ACCESS (PLAT_BRCM_CCN_BASE + 0x0) + +#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x880500) + +/* Used for acceleration of coherent ordered writes */ +#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WUO BIT(4) +/* Wait for completion of requests at RN-I */ +#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WFC BIT(3) + +/* + * Forces all reads from the RN-I to be sent with the request order bit set + * and this ensures ordered allocation of read data buffers in the RN-I + */ +#define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_RQO BIT(5) + +#define OLY_RNI3PDVM_REGISTERS_NODE14_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x8e0500) + +/* Wait for completion of requests at RN-I */ +#define OLY_RNI3PDVM_REGISTERS_NODE14_AUX_CTL_WFC BIT(3) + +#define OLY_HNI_REGISTERS_NODE0_POS_CONTROL (PLAT_BRCM_CCN_BASE + 0x80000) +#define POS_CONTROL_HNI_POS_EN BIT(0) + +#define OLY_HNI_REGISTERS_NODE0_PCIERC_RNI_NODEID_LIST \ + (PLAT_BRCM_CCN_BASE + 0x80008) +/* PAXB and PAXC connected to 8th Node */ +#define SR_RNI_PCIE_CONNECTED BIT(8) +/* PAXB connected to 6th Node */ +#define SRP_RNI_PCIE_CONNECTED BIT(6) + +#define OLY_HNI_REGISTERS_NODE0_SA_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x80500) +#define SA_AUX_CTL_POS_EARLY_WR_COMP_EN BIT(5) +#define SA_AUX_CTL_SER_DEVNE_WR BIT(9) + +/******************************************************************************* + * Coresight related constants + ******************************************************************************/ +#define CORESIGHT_BASE_ADDR 0x62000000 + +#define IHOST0_BASE 0x66000000 +#define IHOST_ADDR_SPACE 0x2000 + +/******************************************************************************* + * SCR related constants + ******************************************************************************/ +#define SCR_BASE 0x6600a000 +#define SCR_ARCACHE_OFFSET 4 +#define SCR_ARCACHE_MASK (0x3 << SCR_ARCACHE_OFFSET) +#define SCR_AWCACHE_OFFSET 6 +#define SCR_AWCACHE_MASK (0x3 << SCR_AWCACHE_OFFSET) +#define SCR_AXCACHE_CONFIG_MASK (SCR_ARCACHE_MASK | SCR_AWCACHE_MASK) +#define SCR_TBUX_AXCACHE_CONFIG ((0x1 << SCR_AWCACHE_OFFSET) | \ + (0x1 << SCR_ARCACHE_OFFSET)) + +#define SCR_REGS_SCR_SOFT_RESET (SCR_BASE + 0x1c) +#define SCR_REGS_GIC_SOFT_RESET BIT(0) + +#define SCR_GPV_BASE 0x66100000 +#define SCR_NOC_SECURITY0 (SCR_GPV_BASE + 0x08) +#define SCR_NOC_DDR_REGISTER_ACCESS (SCR_GPV_BASE + 0x30) + +/******************************************************************************* + * MEMC and DDR related constants + ******************************************************************************/ +#define DDR0_CONTROL_ROOT 0x66200000 +#define EMEM_SS_CFG_0_ROOT 0x66202000 +#define EMEM_SYS_IF_0_ROOT 0x66204000 +#define DDR_PHY0_ROOT 0x66240000 + +#define DDR1_CONTROL_ROOT 0x66280000 +#define EMEM_SS_CFG_1_ROOT 0x66282000 +#define EMEM_SYS_IF_1_ROOT 0x66284000 +#define DDR_PHY1_ROOT 0x662c0000 + +#define DDR2_CONTROL_ROOT 0x66300000 +#define EMEM_SS_CFG_2_ROOT 0x66302000 +#define EMEM_SYS_IF_2_ROOT 0x66304000 +#define DDR_PHY2_ROOT 0x66340000 + +/******************************************************************************* + * TZC400 related constants + ******************************************************************************/ +#define TZC_400_BASE 0x66d84000 + +/******************************************************************************* + * FS4 related constants + ******************************************************************************/ +#define FS4_SRAM_IDM_IO_CONTROL_DIRECT 0x66d8a408 + +#define FS4_CRYPTO_IDM_IO_CONTROL_DIRECT 0x66d8e408 +#define FS4_CRYPTO_IDM_RESET_CONTROL 0x66d8e800 +#define FS4_CRYPTO_BASE 0x67000000 +#define FS4_CRYPTO_DME_BASE (FS4_CRYPTO_BASE + 0x280000) + +#define FS4_RAID_IDM_IO_CONTROL_DIRECT 0x66d8f408 +#define FS4_RAID_IDM_IO_STATUS 0x66d8f500 +#define FS4_RAID_IDM_RESET_CONTROL 0x66d8f800 +#define FS4_RAID_BASE 0x67400000 +#define FS4_RAID_DME_BASE (FS4_RAID_BASE + 0x280000) + +#define FS4_CRYPTO_GPV_BASE 0x67300000 +#define FS4_RAID_GPV_BASE 0x67700000 + +#define FS6_PKI_BASE 0x67400000 +#define FS6_PKI_DME_BASE 0x66D90000 + +#define TZC400_FS_SRAM_ROOT 0x66d84000 +#define GATE_KEEPER_OFFSET 0x8 +#define REGION_ATTRIBUTES_0_OFFSET 0x110 +#define REGION_ID_ACCESS_0_OFFSET 0x114 + +#define NIC400_FS_NOC_ROOT 0x66e00000 +#define NIC400_FS_NOC_SECURITY2_OFFSET 0x10 +#define NIC400_FS_NOC_SECURITY4_OFFSET 0x18 +#define NIC400_FS_NOC_SECURITY7_OFFSET 0x24 + +/******************************************************************************* + * SATA PHY related constants + ******************************************************************************/ +#define SATA_BASE 0x67d00000 + +/******************************************************************************* + * USB related constants + ******************************************************************************/ +#define USB_BASE 0x68500000 +#define USB_SIZE 0x00400000 +#define XHC_BASE (USB_BASE + 0x11000) +#define MAX_USB_PORTS 3 + +/******************************************************************************* + * HSLS related constants + ******************************************************************************/ +#define IPROC_ROOT 0x68900000 +#define HSLS_ICFG_REGS_BASE IPROC_ROOT +#define HSLS_IDM_REGS_BASE 0x68e00000 +#define HSLS_MODE_SEL_CONTROL 0x68a40000 +#define HSLS_TZPC_BASE 0x68b40000 +#define HSLS_GPV_BASE 0x6cd00000 + +/******************************************************************************* + * Chip ID related constants + ******************************************************************************/ +#define ICFG_CHIP_ID HSLS_ICFG_REGS_BASE +#define CHIP_ID_SR 0xd730 +#define CHIP_ID_NS3Z 0xe56d +#define CHIP_ID_MASK 0xf000 +#define ICFG_CHIP_REVISION_ID (HSLS_ICFG_REGS_BASE + 0x4) +#define PLAT_CHIP_ID_GET (mmio_read_32(ICFG_CHIP_ID)) +#define PLAT_CHIP_REV_GET (mmio_read_32(ICFG_CHIP_REVISION_ID)) + +/******************************************************************************* + * CMIC MII (MDIO) related constant + ******************************************************************************/ +#define PLAT_CMIC_MIIM_BASE 0x68920000U + +/******************************************************************************* + * Timers related constants + ******************************************************************************/ +/* ChipcommonG_tim0_TIM_TIMER1Load 0x68930000 */ +#define SP804_TIMER0_BASE 0x68930000 +#define SP804_TIMER1_BASE 0x68940000 +#define SP804_TIMER0_TIMER_VAL_REG_OFFSET 0x4 +#define SP804_TIMER0_CLKMULT 2 +#define SP804_TIMER0_CLKDIV 25 + +/******************************************************************************* + * GPIO related constants + ******************************************************************************/ +#define IPROC_GPIO_NS_BASE 0x689d0000 +#define IPROC_GPIO_S_BASE 0x68b00000 +#define IPROC_GPIO_NR 151 +#define GPIO_S_CNTRL_REG 0x68b60000 + +/******************************************************************************* + * I2C SMBUS related constants + ******************************************************************************/ +#define SMBUS0_REGS_BASE 0x689b0000 +#define SMBUS1_REGS_BASE 0x689e0000 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define ChipcommonG_UART0_UART_RBR_THR_DLL 0x68a00000 +#define ChipcommonG_UART1_UART_RBR_THR_DLL 0x68a10000 +#define ChipcommonG_UART2_UART_RBR_THR_DLL 0x68a20000 +#define ChipcommonG_UART3_UART_RBR_THR_DLL 0x68a30000 + +#define UART0_BASE_ADDR ChipcommonG_UART0_UART_RBR_THR_DLL +#define UART1_BASE_ADDR ChipcommonG_UART1_UART_RBR_THR_DLL +#define UART2_BASE_ADDR ChipcommonG_UART2_UART_RBR_THR_DLL +#define UART3_BASE_ADDR ChipcommonG_UART3_UART_RBR_THR_DLL + +#define UART_SPR_OFFSET 0x1c /* Scratch Pad Register */ + +#define LOG_LEVEL_REGISTER CRMU_SPARE_REG_3 +#define GET_LOG_LEVEL() (mmio_read_32(LOG_LEVEL_REGISTER)) +#define SET_LOG_LEVEL(x) (mmio_write_32(LOG_LEVEL_REGISTER, x)) + +#define IO_RETRY_REGISTER CRMU_SPARE_REG_4 + +#define DWC_UART_REFCLK (25 * 1000 * 1000) +#define DWC_UART_REFCLK_DIV 16 +/* Baud rate in emulation will vary based on setting of 25MHz SCLK */ +#define DWC_UART_BAUDRATE 115200 + +#define BRCM_CRASH_CONSOLE_BASE UART1_BASE_ADDR +#define BRCM_CRASH_CONSOLE_REFCLK DWC_UART_REFCLK +#define BRCM_CRASH_CONSOLE_BAUDRATE DWC_UART_BAUDRATE + +#ifdef BOARD_CONSOLE_UART +#define PLAT_BRCM_BOOT_UART_BASE BOARD_CONSOLE_UART +#else +#define PLAT_BRCM_BOOT_UART_BASE UART1_BASE_ADDR +#endif +#define CONSOLE_UART_ID ((PLAT_BRCM_BOOT_UART_BASE >> 16) & 0x3) + +#define PLAT_BRCM_BOOT_UART_CLK_IN_HZ DWC_UART_REFCLK +#define BRCM_CONSOLE_BAUDRATE DWC_UART_BAUDRATE + +#define PLAT_BRCM_BL31_RUN_UART_BASE PLAT_BRCM_BOOT_UART_BASE +#define PLAT_BRCM_BL31_RUN_UART_CLK_IN_HZ PLAT_BRCM_BOOT_UART_CLK_IN_HZ + +/******************************************************************************* + * IOMUX related constants + ******************************************************************************/ +#define HSLS_IOPAD_BASE HSLS_MODE_SEL_CONTROL +#define MODE_SEL_CONTROL_FSEL_MASK 0x7 +#define MODE_SEL_CONTROL_FSEL_MODE0 0x0 +#define MODE_SEL_CONTROL_FSEL_MODE1 0x1 +#define MODE_SEL_CONTROL_FSEL_MODE2 0x2 +#define MODE_SEL_CONTROL_FSEL_MODE3 0x3 +#define MODE_SEL_CONTROL_FSEL_DEBUG 0x4 +#define IPROC_IOPAD_MODE_BASE (HSLS_MODE_SEL_CONTROL + 0x29c) +#define UART0_SIN_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x4a8) +#define UART0_SOUT_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x4ac) +#define UART1_SIN_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3b8) +#define UART1_SOUT_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3bc) +#define UARTx_SIN_MODE_SEL_CONTROL_FSEL 0 +#define UARTx_SOUT_MODE_SEL_CONTROL_FSEL 0 + +/******************************************************************************* + * PKA constants + ******************************************************************************/ +#define ICFG_PKA_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xac0) +#define ICFG_PKA_MEM_PWR_CTRL__POWERONIN BIT(0) +#define ICFG_PKA_MEM_PWR_CTRL__POWEROKIN BIT(1) +#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONIN BIT(2) +#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKIN BIT(3) +#define ICFG_PKA_MEM_PWR_CTRL__POWERONOUT BIT(4) +#define ICFG_PKA_MEM_PWR_CTRL__POWEROKOUT BIT(5) +#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONOUT BIT(6) +#define ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKOUT BIT(7) +#define ICFG_PKA_MEM_PWR_CTRL__ISO BIT(8) + +/******************************************************************************* + * RNG constants + ******************************************************************************/ +#define RNG_BASE_ADDR 0x68b20000 + +/******************************************************************************* + * Trusted Watchdog constants + ******************************************************************************/ +#define ARM_SP805_TWDG_BASE 0x68b30000 +#define ARM_SP805_TWDG_CLK_HZ ((25 * 1000 * 1000) / 2) +/* + * The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) + */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + +/******************************************************************************* + * SOTP related constants + ******************************************************************************/ +#define SOTP_REGS_OTP_BASE 0x68b50000 +#define SOTP_CHIP_CTRL (SOTP_REGS_OTP_BASE + 0x4c) +#define SOTP_CLEAR_SYSCTRL_ALL_MASTER_NS 0 + +/******************************************************************************* + * DMAC/PL330 related constants + ******************************************************************************/ +#define DMAC_M0_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x408) +#define BOOT_MANAGER_NS BIT(25) +#define DMAC_M0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x800) +#define ICFG_DMAC_CONFIG_0 (HSLS_ICFG_REGS_BASE + 0x190) +#define ICFG_DMAC_CONFIG_1 (HSLS_ICFG_REGS_BASE + 0x194) +#define ICFG_DMAC_CONFIG_2 (HSLS_ICFG_REGS_BASE + 0x198) +#define BOOT_PERIPHERAL_NS 0xffffffff +#define ICFG_DMAC_CONFIG_3 (HSLS_ICFG_REGS_BASE + 0x19c) +#define BOOT_IRQ_NS 0x0000ffff +#define ICFG_DMAC_SID_ARADDR_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf0) +#define ICFG_DMAC_SID_AWADDR_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf4) +#define ICFG_DMAC_MEM_PWR_CTRL__POWERONIN BIT(0) +#define ICFG_DMAC_MEM_PWR_CTRL__POWEROKIN BIT(1) +#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONIN BIT(2) +#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKIN BIT(3) +#define ICFG_DMAC_MEM_PWR_CTRL__POWERONOUT BIT(4) +#define ICFG_DMAC_MEM_PWR_CTRL__POWEROKOUT BIT(5) +#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONOUT BIT(6) +#define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKOUT BIT(7) +#define ICFG_DMAC_MEM_PWR_CTRL__ISO BIT(8) +#define ICFG_DMAC_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xadc) + +/******************************************************************************* + * PNOR related constants + ******************************************************************************/ +#define PNOR_ICFG_BASE (HSLS_ICFG_REGS_BASE + 0x780) +#define PNOR_ICFG_CS_0 PNOR_ICFG_BASE +#define PNOR_ICFG_CS_1 (PNOR_ICFG_BASE + 0x4) +#define PNOR_ICFG_CS_2 (PNOR_ICFG_BASE + 0x8) +#define PNOR_ICFG_CS_x_MASK0_MASK 0xff +#define PNOR_ICFG_CS_x_MASK0_SHIFT 8 +#define PNOR_ICFG_CS_x_MATCH0_MASK 0xff +#define PNOR_ICFG_CS_x_MATCH0_SHIFT 0 + +#define PNOR_IDM_BASE (HSLS_IDM_REGS_BASE + 0xb000) +#define PNOR_IDM_IO_CONTROL_DIRECT (PNOR_IDM_BASE + 0x408) +#define PNOR_IDM_IO_RESET_CONTROL (PNOR_IDM_BASE + 0x800) + +#define PNOR_REG_BASE 0x68c50000 +#define PNOR_REG_DIRECT_CMD (PNOR_REG_BASE + 0x010) +#define PNOR_REG_SET_CYCLES (PNOR_REG_BASE + 0x014) +#define PNOR_REG_SET_OPMODE (PNOR_REG_BASE + 0x018) +#define PNOR_REG_REFRESH_0 (PNOR_REG_BASE + 0x020) +#define PNOR_REG_PERIPH_ID0 (PNOR_REG_BASE + 0xfe0) +#define PNOR_REG_PERIPH_ID1 (PNOR_REG_BASE + 0xfe4) +#define PNOR_REG_PERIPH_ID2 (PNOR_REG_BASE + 0xfe8) +#define PNOR_REG_PERIPH_ID3 (PNOR_REG_BASE + 0xfec) +#define PNOR_REG_PERIPH_IDx_MASK 0xff + +/******************************************************************************* + * NAND related constants + ******************************************************************************/ +#define NAND_FLASH_REVISION 0x68c60000 +#define NAND_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0xa408) +#define NAND_IDM_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xa800) + +/******************************************************************************* + * eMMC related constants + ******************************************************************************/ +#define PLAT_SD_MAX_READ_LENGTH 0x400 + +#define SDIO0_EMMCSDXC_SYSADDR 0x68cf1000 +#define SDIO_IDM0_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x2408) +#define SDIO_IDM1_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x3408) +#define SDIO_IDM0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x2800) +#define ICFG_SDIO0_BASE (HSLS_ICFG_REGS_BASE + 0x6e4) +#define ICFG_SDIO1_BASE (HSLS_ICFG_REGS_BASE + 0x734) +#define ICFG_SDIO0_CAP0 (ICFG_SDIO0_BASE + 0x10) +#define ICFG_SDIO0_CAP1 (ICFG_SDIO0_BASE + 0x14) +#define ICFG_SDIO0_SID (HSLS_ICFG_REGS_BASE + 0xb00) +#define ICFG_SDIO1_SID (HSLS_ICFG_REGS_BASE + 0xb08) + +/******************************************************************************* + * Bootstrap related constants + ******************************************************************************/ +#define ROM_S0_IDM_IO_STATUS (HSLS_IDM_REGS_BASE + 0x9500) + +/******************************************************************************* + * ROM related constants + ******************************************************************************/ +#define ROM_BASE_ADDR 0x6ce00000 +#define ROM_VERSION_STRING_ADDR (ROM_BASE_ADDR + 0x28000) +#define ROM_BUILD_MESSAGE_ADDR (ROM_BASE_ADDR + 0x28018) + +/******************************************************************************* + * Boot source peripheral related constants + ******************************************************************************/ +#define QSPI_CTRL_BASE_ADDR 0x68c70000 +#define QSPI_BASE_ADDR 0x70000000 +#define QSPI_SIZE 0x08000000 +#define NOR_BASE_ADDR 0x74000000 +#define NOR_SIZE 0x04000000 +#define NAND_BASE_ADDR 0x78000000 +#define NAND_SIZE 0x08000000 + +#define QSPI_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xc800) + +#define APBR_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xe800) +#define APBS_IDM_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xf800) + +#define APBX_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x10408) +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_WDOG_SCLK_SEL 2 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM0_SCLK_SEL 4 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM1_SCLK_SEL 6 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM2_SCLK_SEL 8 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM3_SCLK_SEL 10 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM4_SCLK_SEL 12 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM5_SCLK_SEL 13 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM6_SCLK_SEL 14 +#define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM7_SCLK_SEL 15 + +#define APBY_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x11408) +#define APBY_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0 +#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART0_SCLK_SEL 2 +#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART1_SCLK_SEL 4 +#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART2_SCLK_SEL 6 +#define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART3_SCLK_SEL 8 + +#define APBZ_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x12408) +#define APBZ_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0 +#define APBZ_IDM_IDM_IO_CONTROL_DIRECT_WDOG_SCLK_SEL 2 + +/******************************************************************************* + * Stingray memory map related constants + ******************************************************************************/ + +/* The last 4KB of Trusted SRAM are used as shared memory */ +#define BRCM_SHARED_RAM_SIZE 0x0 +#define BRCM_SHARED_RAM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \ + PLAT_BRCM_TRUSTED_SRAM_SIZE - \ + BRCM_SHARED_RAM_SIZE) + +/* Reserve 4 KB to store error logs in BL2 */ +#define BCM_ELOG_BL2_SIZE 0x00001000 +#define BCM_ELOG_BL2_BASE BL1_RW_LIMIT + +/* The remaining Trusted SRAM is used to load the BL images */ +#define BRCM_BL_RAM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE) +#define BRCM_BL_RAM_SIZE (PLAT_BRCM_TRUSTED_SRAM_SIZE - \ + BRCM_SHARED_RAM_SIZE) + +/* DDR Address where TMON temperature values are written */ +#define TMON_SHARED_DDR_ADDRESS 0x8f100000 + +/* Reserve 4 kB to pass data to BL33 */ +#define BL33_SHARED_DDR_BASE 0x8f102000 +#define BL33_SHARED_DDR_SIZE 0x1000 + +/* Default AP error logging base addr */ +#ifndef ELOG_AP_UART_LOG_BASE +#define ELOG_AP_UART_LOG_BASE 0x8f110000 +#endif + +/* Reserve 16 to store error logs in BL31 */ +#define BCM_ELOG_BL31_BASE ELOG_AP_UART_LOG_BASE +#define BCM_ELOG_BL31_SIZE 0x4000 + +/******************************************************************************* + * Non-secure DDR Map + ******************************************************************************/ +#define BRCM_DRAM1_BASE ULL(0x80000000) +#define BRCM_DRAM1_SIZE ULL(0x10000000) +#define BRCM_DRAM2_BASE ULL(0x880000000) +#define BRCM_DRAM2_SIZE ULL(0x780000000) +#define BRCM_DRAM3_BASE ULL(0x8800000000) +#define BRCM_DRAM3_SIZE ULL(0x7800000000) +#define BRCM_SHARED_DRAM_BASE BL33_SHARED_DDR_BASE +#define BRCM_SHARED_DRAM_SIZE BL33_SHARED_DDR_SIZE +#define BRCM_EXT_SRAM_BASE ULL(0x74000000) +#define BRCM_EXT_SRAM_SIZE ULL(0x4000000) + +/* Priority levels for platforms */ +#define PLAT_RAS_PRI 0x10 +#define PLAT_SDEI_CRITICAL_PRI 0x60 +#define PLAT_SDEI_NORMAL_PRI 0x70 + +/* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 */ +#define BRCM_IRQ_SEC_SGI_0 14 +#define BRCM_IRQ_SEC_SGI_1 15 + +/* RTC periodic interrupt */ +#define BRCM_IRQ_SEC_SPI_0 49 + +/* + * Macros for local power states in SR platforms encoded by State-ID field + * within the power-state parameter. + */ + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN 0 + +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET 1 + +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF 2 + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF + +/* ChiMP-related constants */ + +#define NITRO_TZPC_TZPCDECPROT0clr 0x60c01808 +#define NITRO_TZPC_TZPCDECPROT0clr__DECPROT0_chimp_m_clr_R 1 + +#define NIC400_NITRO_CHIMP_S_IDM_IO_CONTROL_DIRECT 0x60e00408 + +#define CHIMP_INDIRECT_ADDR_MASK 0x3fffff +#define CHIMP_INDIRECT_BASE 0x60800000 + +#define CHIMP_REG_ECO_RESERVED 0x3042400 + +#define CHIMP_FLASH_ACCESS_DONE_BIT 2 + +/* indicate FRU table programming is done successfully */ +#define CHIMP_FRU_PROG_DONE_BIT 9 + +#define CHIMP_REG_CTRL_BPE_MODE_REG 0x0 +#define CHIMP_REG_CTRL_BPE_STAT_REG 0x4 +#define CHIMP_REG_CTRL_FSTBOOT_PTR_REG 0x8 +#define CHIMP_REG_CHIMP_REG_CTRL_BPE_MODE_REG__cm3_rst_L 1 +#define CHIMP_REG_CHIMP_REG_CTRL_BPE_MODE_REG__cm3_rst_R 1 +#define CHIMP_REG_CTRL_BASE 0x3040000 +#define CHIMP_FAST_BOOT_MODE_BIT 2 +#define CHIMP_REG_CHIMP_APE_SCPAD 0x3300000 +#define CHIMP_REG_CHIMP_SCPAD 0x3100000 + +/* Chimp health status offset in scratch pad ram */ +#define CHIMP_HEALTH_STATUS_OFFSET 0x8 +/* + * If not in NIC mode then FASTBOOT can be enabled. + * "Not in NIC mode" means that FORCE_FASTBOOT is set + * and a valid (1 or 2) fastboot type is specified. + * + * Three types of fastboot are supported: + * 0 = No fastboot. Boots Nitro/ChiMP and lets ROM loader + * initialize ChiMP from NVRAM (QSPI). + * + * 1 = Jump in place (need a flat image) + * This is intended to speedup Nitro FW boot on Palladium, + * can be used with a real chip as well. + * 2 = Jump normally with decompression + * Modus operandi for a real chip. Works also on Palladium + * Note: image decompressing takes time on Palladium. + * 3 = No fastboot support. No ChiMP bringup + * (use only for AP debug or for ChiMP's deferred setup). + */ +#define CHIMP_FASTBOOT_JUMP_DECOMPRESS 2 +#define CHIMP_FASTBOOT_JUMP_IN_PLACE 1 +#define CHIMP_FASTBOOT_NITRO_RESET 0 +/* + * Definitions for a non-Nitro access + * to QSPI PAD after the handshake + */ +#define QSPI_HOLD_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3e8) +#define QSPI_WP_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3ec) +#define QSPI_SCK_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f0) +#define QSPI_CS_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f4) +#define QSPI_MOSI_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f8) +#define QSPI_MISO_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3fc) + +/******************************************************************************* + * Stream IDs for different blocks of SR + * block_id for different blocks is as follows: + * PCIE : 0x0 + * PAXC : 0x1 + * FS4 : 0x2 + * Rest of the masters(includes MHB via RNI): 0x3 + ******************************************************************************/ +#define SR_SID_VAL(block_id, subblock_id, device_num) ((block_id << 13) | \ + (subblock_id << 11) | \ + (device_num)) + +#define CRMU_STREAM_ID SR_SID_VAL(0x3, 0x0, 0x7) +#define CRMU_SID_SHIFT 5 + +#define DMAC_STREAM_ID SR_SID_VAL(0x3, 0x0, 0x0) +#define DMAC_SID_SHIFT 5 + +/* DDR SHMOO Values defines */ +#define IDRAM_SHMOO_VALUES_ADDR CRMU_IDRAM_BASE_ADDR +#define DDR_SHMOO_VALUES_ADDR 0x8f103000 +#define SHMOO_SIZE_PER_CHANNEL 0x1000 + +#endif /* SR_DEF_H */ diff --git a/plat/brcm/board/stingray/include/sr_utils.h b/plat/brcm/board/stingray/include/sr_utils.h new file mode 100644 index 0000000..b3fc735 --- /dev/null +++ b/plat/brcm/board/stingray/include/sr_utils.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SR_UTILS_H +#define SR_UTILS_H + +#include <lib/mmio.h> + +#include <chip_id.h> +#include <cmn_plat_util.h> +#include <sr_def.h> + +static inline void brcm_stingray_set_qspi_mux(int enable_ap) +{ + mmio_write_32(QSPI_HOLD_N_MODE_SEL_CONTROL, enable_ap); + mmio_write_32(QSPI_WP_N_MODE_SEL_CONTROL, enable_ap); + mmio_write_32(QSPI_SCK_MODE_SEL_CONTROL, enable_ap); + mmio_write_32(QSPI_CS_N_MODE_SEL_CONTROL, enable_ap); + mmio_write_32(QSPI_MOSI_MODE_SEL_CONTROL, enable_ap); + mmio_write_32(QSPI_MISO_MODE_SEL_CONTROL, enable_ap); +} + +static inline void brcm_stingray_set_straps(uint32_t boot_source) +{ + /* Enable software strap override */ + mmio_setbits_32(CDRU_CHIP_STRAP_CTRL, + BIT(CDRU_CHIP_STRAP_CTRL__SOFTWARE_OVERRIDE)); + + /* set straps to the next boot source */ + mmio_clrsetbits_32(CDRU_CHIP_STRAP_DATA, + BOOT_SOURCE_MASK, + boot_source); + + /* Disable software strap override */ + mmio_clrbits_32(CDRU_CHIP_STRAP_CTRL, + BIT(CDRU_CHIP_STRAP_CTRL__SOFTWARE_OVERRIDE)); +} + +#endif diff --git a/plat/brcm/board/stingray/include/swreg.h b/plat/brcm/board/stingray/include/swreg.h new file mode 100644 index 0000000..6e971ce --- /dev/null +++ b/plat/brcm/board/stingray/include/swreg.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SWREG_H +#define SWREG_H + +/* default voltage if no valid OTP */ +#define VDDC_CORE_DEF_VOLT 910000 /* 0.91v */ +#define IHOST_DEF_VOLT 940000 /* 0.94v */ + +#define B0_VDDC_CORE_DEF_VOLT 950000 /* 0.95v */ +#define B0_IHOST_DEF_VOLT 950000 /* 0.95v */ +#define B0_DDR_VDDC_DEF_VOLT 1000000 /* 1v */ + +#define SWREG_IHOST1_DIS 4 +#define SWREG_IHOST1_REG_RESETB 5 +#define SWREG_IHOST1_PMU_STABLE 2 + +enum sw_reg { + DDR_VDDC = 1, + IHOST03, + IHOST12, + IHOST_ARRAY, + DDRIO_SLAVE, + VDDC_CORE, + VDDC1, + DDRIO_MASTER +}; + +int set_swreg(enum sw_reg reg_id, uint32_t micro_volts); +int swreg_firmware_update(void); + +#endif diff --git a/plat/brcm/board/stingray/include/timer_sync.h b/plat/brcm/board/stingray/include/timer_sync.h new file mode 100644 index 0000000..1f15bb0 --- /dev/null +++ b/plat/brcm/board/stingray/include/timer_sync.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TIMER_SYNC_H +#define TIMER_SYNC_H + +void brcm_timer_sync_init(void); + +#endif diff --git a/plat/brcm/board/stingray/include/usb_phy.h b/plat/brcm/board/stingray/include/usb_phy.h new file mode 100644 index 0000000..7d83182 --- /dev/null +++ b/plat/brcm/board/stingray/include/usb_phy.h @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2017 - 2021, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef USB_PHY_H +#define USB_PHY_H + +#include <stdint.h> + +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> + +#include <platform_def.h> + +#define DRDU2_U2PLL_NDIV_FRAC_OFFSET 0x0U + +#define DRDU2_U2PLL_NDIV_INT 0x4U + +#define DRDU2_U2PLL_CTRL 0x8U +#define DRDU2_U2PLL_LOCK BIT(6U) +#define DRDU2_U2PLL_RESETB BIT(5U) +#define DRDU2_U2PLL_PDIV_MASK 0xFU +#define DRDU2_U2PLL_PDIV_OFFSET 1U +#define DRDU2_U2PLL_SUSPEND_EN BIT(0U) + +#define DRDU2_PHY_CTRL 0x0CU +#define DRDU2_U2IDDQ BIT(30U) +#define DRDU2_U2SOFT_RST_N BIT(29U) +#define DRDU2_U2PHY_ON_FLAG BIT(22U) +#define DRDU2_U2PHY_PCTL_MASK 0xFFFFU +#define DRDU2_U2PHY_PCTL_OFFSET 6U +#define DRDU2_U2PHY_RESETB BIT(5U) +#define DRDU2_U2PHY_ISO BIT(4U) +#define DRDU2_U2AFE_BG_PWRDWNB BIT(3U) +#define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U) +#define DRDU2_U2AFE_LDO_PWRDWNB BIT(1U) +#define DRDU2_U2CTRL_CORERDY BIT(0U) + +#define DRDU2_STRAP_CTRL 0x18U +#define DRDU2_FORCE_HOST_MODE BIT(5U) +#define DRDU2_FORCE_DEVICE_MODE BIT(4U) +#define BDC_USB_STP_SPD_MASK 0x7U +#define BDC_USB_STP_SPD_OFFSET 0U + +#define DRDU2_PWR_CTRL 0x1CU +#define DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I BIT(2U) +#define DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I BIT(1U) + +#define DRDU2_SOFT_RESET_CTRL 0x20U +#define DRDU2_BDC_AXI_SOFT_RST_N BIT(0U) + +#define USB3H_U2PLL_NDIV_FRAC 0x4U + +#define USB3H_U2PLL_NDIV_INT 0x8U + +#define USB3H_U2PLL_CTRL 0xCU +#define USB3H_U2PLL_LOCK BIT(6U) +#define USB3H_U2PLL_RESETB BIT(5U) +#define USB3H_U2PLL_PDIV_MASK 0xFU +#define USB3H_U2PLL_PDIV_OFFSET 1U + +#define USB3H_U2PHY_CTRL 0x10U +#define USB3H_U2PHY_ON_FLAG 22U +#define USB3H_U2PHY_PCTL_MASK 0xFFFFU +#define USB3H_U2PHY_PCTL_OFFSET 6U +#define USB3H_U2PHY_IDDQ BIT(29U) +#define USB3H_U2PHY_RESETB BIT(5U) +#define USB3H_U2PHY_ISO BIT(4U) +#define USB3H_U2AFE_BG_PWRDWNB BIT(3U) +#define USB3H_U2AFE_PLL_PWRDWNB BIT(2U) +#define USB3H_U2AFE_LDO_PWRDWNB BIT(1U) +#define USB3H_U2CTRL_CORERDY BIT(0U) + +#define USB3H_U3PHY_CTRL 0x14U +#define USB3H_U3SOFT_RST_N BIT(30U) +#define USB3H_U3MDIO_RESETB_I BIT(29U) +#define USB3H_U3POR_RESET_I BIT(28U) +#define USB3H_U3PHY_PCTL_MASK 0xFFFFU +#define USB3H_U3PHY_PCTL_OFFSET 2U +#define USB3H_U3PHY_RESETB BIT(1U) + +#define USB3H_U3PHY_PLL_CTRL 0x18U +#define USB3H_U3PLL_REFCLK_MASK 0x7U +#define USB3H_U3PLL_REFCLK_OFFSET 4U +#define USB3H_U3PLL_SS_LOCK BIT(3U) +#define USB3H_U3PLL_SEQ_START BIT(2U) +#define USB3H_U3SSPLL_SUSPEND_EN BIT(1U) +#define USB3H_U3PLL_RESETB BIT(0U) + +#define USB3H_PWR_CTRL 0x28U +#define USB3H_PWR_CTRL_OVERRIDE_I_R 4U +#define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN BIT(11U) +#define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN BIT(10U) + +#define USB3H_SOFT_RESET_CTRL 0x2CU +#define USB3H_XHC_AXI_SOFT_RST_N BIT(1U) + +#define USB3H_PHY_PWR_CTRL 0x38U +#define USB3H_DISABLE_USB30_P0 BIT(2U) +#define USB3H_DISABLE_EUSB_P1 BIT(1U) +#define USB3H_DISABLE_EUSB_P0 BIT(0U) + + +#define DRDU3_U2PLL_NDIV_FRAC 0x4U + +#define DRDU3_U2PLL_NDIV_INT 0x8U + +#define DRDU3_U2PLL_CTRL 0xCU +#define DRDU3_U2PLL_LOCK BIT(6U) +#define DRDU3_U2PLL_RESETB BIT(5U) +#define DRDU3_U2PLL_PDIV_MASK 0xFU +#define DRDU3_U2PLL_PDIV_OFFSET 1U + +#define DRDU3_U2PHY_CTRL 0x10U +#define DRDU3_U2PHY_IDDQ BIT(29U) +#define DRDU3_U2PHY_ON_FLAG BIT(22U) +#define DRDU3_U2PHY_PCTL_MASK 0xFFFFU +#define DRDU3_U2PHY_PCTL_OFFSET 6U +#define DRDU3_U2PHY_RESETB BIT(5U) +#define DRDU3_U2PHY_ISO BIT(4U) +#define DRDU3_U2AFE_BG_PWRDWNB BIT(3U) +#define DRDU3_U2AFE_PLL_PWRDWNB BIT(2U) +#define DRDU3_U2AFE_LDO_PWRDWNB BIT(1U) +#define DRDU3_U2CTRL_CORERDY BIT(0U) + +#define DRDU3_U3PHY_CTRL 0x14U +#define DRDU3_U3XHC_SOFT_RST_N BIT(31U) +#define DRDU3_U3BDC_SOFT_RST_N BIT(30U) +#define DRDU3_U3MDIO_RESETB_I BIT(29U) +#define DRDU3_U3POR_RESET_I BIT(28U) +#define DRDU3_U3PHY_PCTL_MASK 0xFFFFU +#define DRDU3_U3PHY_PCTL_OFFSET 2U +#define DRDU3_U3PHY_RESETB BIT(1U) + +#define DRDU3_U3PHY_PLL_CTRL 0x18U +#define DRDU3_U3PLL_REFCLK_MASK 0x7U +#define DRDU3_U3PLL_REFCLK_OFFSET 4U +#define DRDU3_U3PLL_SS_LOCK BIT(3U) +#define DRDU3_U3PLL_SEQ_START BIT(2U) +#define DRDU3_U3SSPLL_SUSPEND_EN BIT(1U) +#define DRDU3_U3PLL_RESETB BIT(0U) + +#define DRDU3_STRAP_CTRL 0x28U +#define BDC_USB_STP_SPD_MASK 0x7U +#define BDC_USB_STP_SPD_OFFSET 0U +#define BDC_USB_STP_SPD_SS 0x0U +#define BDC_USB_STP_SPD_HS 0x2U + +#define DRDU3_PWR_CTRL 0x2cU +#define DRDU3_U2PHY_DFE_SWITCH_PWROKIN BIT(12U) +#define DRDU3_U2PHY_DFE_SWITCH_PWRONIN BIT(11U) +#define DRDU3_PWR_CTRL_OVERRIDE_I_R 4U + +#define DRDU3_SOFT_RESET_CTRL 0x30U +#define DRDU3_XHC_AXI_SOFT_RST_N BIT(1U) +#define DRDU3_BDC_AXI_SOFT_RST_N BIT(0U) + +#define DRDU3_PHY_PWR_CTRL 0x3cU +#define DRDU3_DISABLE_USB30_P0 BIT(2U) +#define DRDU3_DISABLE_EUSB_P1 BIT(1U) +#define DRDU3_DISABLE_EUSB_P0 BIT(0U) + +#define PLL_REFCLK_PAD 0x0U +#define PLL_REFCLK_25MHZ 0x1U +#define PLL_REFCLK_96MHZ 0x2U +#define PLL_REFCLK_INTERNAL 0x3U +/* USB PLL lock time out for 10 ms */ +#define PLL_LOCK_RETRY_COUNT 10000U + + +#define U2PLL_NDIV_INT_VAL 0x13U +#define U2PLL_NDIV_FRAC_VAL 0x1005U +#define U2PLL_PDIV_VAL 0x1U +/* + * Using external FSM + * BIT-3:2: device mode; mode is not effect + * BIT-1: soft reset active low + */ +#define U2PHY_PCTL_VAL 0x0003U +/* Non-driving signal low */ +#define U2PHY_PCTL_NON_DRV_LOW 0x0002U +#define U3PHY_PCTL_VAL 0x0006U + +#define MAX_NR_PORTS 3U + +#define USB3H_DRDU2_PHY 1U +#define DRDU3_PHY 2U + +#define USB_HOST_MODE 1U +#define USB_DEV_MODE 2U + +#define USB3SS_PORT 0U +#define DRDU2_PORT 1U +#define USB3HS_PORT 2U + +#define DRD3SS_PORT 0U +#define DRD3HS_PORT 1U + +#define SR_USB_PHY_COUNT 2U + +#define DRDU3_PIPE_CTRL 0x68500000U +#define DRDU3H_XHC_REGS_CPLIVER 0x68501000U +#define USB3H_PIPE_CTRL 0x68510000U +#define DRD2U3H_XHC_REGS_CPLIVER 0x68511000U +#define DRDU2_U2PLL_NDIV_FRAC 0x68520000U + +#define AXI_DEBUG_CTRL 0x68500038U +#define AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(12U) + +#define USB3H_DEBUG_CTRL 0x68510034U +#define USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(7U) + +typedef struct _usb_phy_port usb_phy_port_t; + +typedef struct { + uint32_t drdu2reg; + uint32_t usb3hreg; + uint32_t drdu3reg; + uint32_t phy_id; + uint32_t ports_enabled; + uint32_t initialized; + usb_phy_port_t *phy_port; +} usb_phy_t; + +struct _usb_phy_port { + uint32_t port_id; + uint32_t mode; + uint32_t enabled; + usb_phy_t *p; +}; + +struct u2_phy_ext_fsm { + uint32_t pll_ctrl_reg; + uint32_t phy_ctrl_reg; + uint32_t phy_iddq; + uint32_t pwr_ctrl_reg; + uint32_t pwr_okin; + uint32_t pwr_onin; +}; + +#endif /* USB_PHY_H */ |