diff options
Diffstat (limited to 'plat/hisilicon/poplar/include')
| -rw-r--r-- | plat/hisilicon/poplar/include/hi3798cv200.h | 105 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/plat_macros.S | 10 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/plat_private.h | 37 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/platform_def.h | 171 | ||||
| -rw-r--r-- | plat/hisilicon/poplar/include/poplar_layout.h | 132 |
5 files changed, 455 insertions, 0 deletions
diff --git a/plat/hisilicon/poplar/include/hi3798cv200.h b/plat/hisilicon/poplar/include/hi3798cv200.h new file mode 100644 index 0000000..e31f4b3 --- /dev/null +++ b/plat/hisilicon/poplar/include/hi3798cv200.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef HI3798CV200_H +#define HI3798CV200_H + +#include <lib/utils_def.h> + +/* PL011 */ +#define PL011_UART0_BASE (0xF8B00000) +#define PL011_BAUDRATE (115200) +#define PL011_UART0_CLK_IN_HZ (75000000) + +/* Sys Counter */ +#define SYS_COUNTER_FREQ_IN_TICKS (24000000) +#define SYS_COUNTER_FREQ_IN_MHZ (24) + +/* Timer */ +#define SEC_TIMER0_BASE (0xF8008000) +#define TIMER00_LOAD (SEC_TIMER0_BASE + 0x000) +#define TIMER00_VALUE (SEC_TIMER0_BASE + 0x004) +#define TIMER00_CONTROL (SEC_TIMER0_BASE + 0x008) +#define TIMER00_BGLOAD (SEC_TIMER0_BASE + 0x018) + +#define SEC_TIMER2_BASE (0xF8009000) +#define TIMER20_LOAD (SEC_TIMER2_BASE + 0x000) +#define TIMER20_VALUE (SEC_TIMER2_BASE + 0x004) +#define TIMER20_CONTROL (SEC_TIMER2_BASE + 0x008) +#define TIMER20_BGLOAD (SEC_TIMER2_BASE + 0x018) + +/* GPIO */ +#define GPIO_MAX (13) +#define GPIO_BASE(x) (x != 5 ? \ + 0xf820000 + x * 0x1000 : 0xf8004000) + +/* SCTL */ +#define REG_BASE_SCTL (0xF8000000) +#define REG_SC_GEN12 (0x00B0) + +/* CRG */ +#define REG_BASE_CRG (0xF8A22000) +#define REG_CPU_LP (0x48) +#define REG_CPU_RST (0x50) +#define REG_PERI_CRG39 (0x9C) +#define REG_PERI_CRG40 (0xA0) + +/* MCI */ +#define REG_BASE_MCI (0xF9830000) +#define MCI_CDETECT (0x50) +#define MCI_VERID (0x6C) +#define MCI_VERID_VALUE (0x5342250A) +#define MCI_VERID_VALUE2 (0x5342270A) + +/* EMMC */ +#define REG_EMMC_PERI_CRG REG_PERI_CRG40 +#define REG_SDCARD_PERI_CRG REG_PERI_CRG39 +#define EMMC_CLK_MASK (0x7 << 8) +#define EMMC_SRST_REQ (0x1 << 4) +#define EMMC_CKEN (0x1 << 1) +#define EMMC_BUS_CKEN (0x1 << 0) +#define EMMC_CLK_100M (0 << 8) +#define EMMC_CLK_50M (1 << 8) +#define EMMC_CLK_25M (2 << 8) + +#define EMMC_DESC_SIZE U(0x00100000) /* 1MB */ +#define EMMC_INIT_PARAMS(base) \ + { .bus_width = MMC_BUS_WIDTH_8, \ + .clk_rate = 25 * 1000 * 1000, \ + .desc_base = (base), \ + .desc_size = EMMC_DESC_SIZE, \ + .flags = MMC_FLAG_CMD23, \ + .reg_base = REG_BASE_MCI, \ + } + +/* GIC-400 */ +#define GICD_BASE (0xF1001000) +#define GICC_BASE (0xF1002000) +#define GICR_BASE (0xF1000000) + +/* FIQ platform related define */ +#define HISI_IRQ_SEC_SGI_0 8 +#define HISI_IRQ_SEC_SGI_1 9 +#define HISI_IRQ_SEC_SGI_2 10 +#define HISI_IRQ_SEC_SGI_3 11 +#define HISI_IRQ_SEC_SGI_4 12 +#define HISI_IRQ_SEC_SGI_5 13 +#define HISI_IRQ_SEC_SGI_6 14 +#define HISI_IRQ_SEC_SGI_7 15 +#define HISI_IRQ_SEC_PPI_0 29 +#define HISI_IRQ_SEC_TIMER0 60 +#define HISI_IRQ_SEC_TIMER1 50 +#define HISI_IRQ_SEC_TIMER2 52 +#define HISI_IRQ_SEC_TIMER3 88 +#define HISI_IRQ_SEC_AXI 110 + +/* Watchdog */ +#define HISI_WDG0_BASE (0xF8A2C000) + +#define HISI_TZPC_BASE (0xF8A80000) +#define HISI_TZPC_SEC_ATTR_CTRL (HISI_TZPC_BASE + 0x10) + +#endif /* HI3798CV200_H */ diff --git a/plat/hisilicon/poplar/include/plat_macros.S b/plat/hisilicon/poplar/include/plat_macros.S new file mode 100644 index 0000000..82d10c1 --- /dev/null +++ b/plat/hisilicon/poplar/include/plat_macros.S @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +.section .rodata.gic_reg_name, "aS" + .macro plat_crash_print_regs + nop + .endm diff --git a/plat/hisilicon/poplar/include/plat_private.h b/plat/hisilicon/poplar/include/plat_private.h new file mode 100644 index 0000000..a34f138 --- /dev/null +++ b/plat/hisilicon/poplar/include/plat_private.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +#include <common/bl_common.h> + +#include "hi3798cv200.h" + +void plat_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit, + unsigned long coh_start, + unsigned long coh_limit); + +void plat_configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit, + unsigned long coh_start, + unsigned long coh_limit); + +void plat_io_setup(void); + +unsigned int poplar_calc_core_pos(u_register_t mpidr); + +void poplar_gic_driver_init(void); +void poplar_gic_init(void); +void poplar_gic_cpuif_enable(void); +void poplar_gic_pcpu_init(void); + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h new file mode 100644 index 0000000..ce0fbbc --- /dev/null +++ b/plat/hisilicon/poplar/include/platform_def.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + +#include "hi3798cv200.h" +#include "poplar_layout.h" /* BL memory region sizes, etc */ + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define POPLAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define POPLAR_CRASH_UART_BASE PL011_UART0_BASE +#define POPLAR_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ +#define POPLAR_CONSOLE_BAUDRATE PL011_BAUDRATE + +/* Generic platform constants */ +#define PLATFORM_STACK_SIZE (0x800) + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" +#define BOOT_EMMC_NAME "l-loader.bin" + +#define PLATFORM_CACHE_LINE_SIZE (64) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) + +/* IO framework user */ +#define MAX_IO_DEVICES (4) +#define MAX_IO_HANDLES (4) +#define MAX_IO_BLOCK_DEVICES U(2) + +/* Memory size options */ +#define POPLAR_DRAM_SIZE_1G 0 +#define POPLAR_DRAM_SIZE_2G 1 + +/* Memory map related constants */ +#define DDR_BASE (0x00000000) + +#if (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_2G) +#define DDR_SIZE (0x80000000) +#elif (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_1G) +#define DDR_SIZE (0x40000000) +#else +#error "Currently unsupported POPLAR_DRAM_SIZE_ID value" +#endif + +#define DEVICE_BASE (0xF0000000) +#define DEVICE_SIZE (0x0F000000) + +#define TEE_SEC_MEM_BASE (0x70000000) +#define TEE_SEC_MEM_SIZE (0x10000000) + +/* Memory location options for TSP */ +#define POPLAR_SRAM_ID 0 +#define POPLAR_DRAM_ID 1 + +/* + * DDR for OP-TEE (26MB from 0x02400000 -0x04000000) is divided in several + * regions: + * - Secure DDR (default is the top 16MB) used by OP-TEE + * - Non-secure DDR (4MB) reserved for OP-TEE's future use + * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature + * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) + */ +#define DDR_SEC_SIZE 0x01000000 +#define DDR_SEC_BASE 0x03000000 + +/* + * BL3-2 specific defines. + */ + +/* + * The TSP currently executes from TZC secured area of DRAM. + */ +#define BL32_DRAM_BASE 0x03000000 +#define BL32_DRAM_LIMIT 0x04000000 + +#ifdef SPD_opteed +/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ +#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ +#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */ +#endif + +#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID) +#define TSP_SEC_MEM_BASE BL32_DRAM_BASE +#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) +#define BL32_BASE BL32_DRAM_BASE +#define BL32_LIMIT BL32_DRAM_LIMIT +#elif (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_SRAM_ID) +#error "SRAM storage of TSP payload is currently unsupported" +#else +#error "Currently unsupported POPLAR_TSP_LOCATION_ID value" +#endif + +/* BL32 is mandatory in AArch32 */ +#ifdef __aarch64__ +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ +#endif + +#define POPLAR_EMMC_DATA_BASE U(0x02200000) +#define POPLAR_EMMC_DATA_SIZE EMMC_DESC_SIZE +#define POPLAR_EMMC_DESC_BASE (POPLAR_EMMC_DATA_BASE + POPLAR_EMMC_DATA_SIZE) +#define POPLAR_EMMC_DESC_SIZE EMMC_DESC_SIZE + +#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000 + +/* Page table and MMU setup constants */ +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES (4) +#define MAX_MMAP_REGIONS (16) + +#define CACHE_WRITEBACK_SHIFT (6) +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* Power states */ +#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1) +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) + +/* Interrupt controller */ +#define POPLAR_GICD_BASE GICD_BASE +#define POPLAR_GICC_BASE GICC_BASE + +#define POPLAR_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define POPLAR_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/hisilicon/poplar/include/poplar_layout.h b/plat/hisilicon/poplar/include/poplar_layout.h new file mode 100644 index 0000000..03047f9 --- /dev/null +++ b/plat/hisilicon/poplar/include/poplar_layout.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef POPLAR_LAYOUT_H +#define POPLAR_LAYOUT_H + +/* + * Boot memory layout definitions for the HiSilicon Poplar board + */ + +/* + * When Poplar is powered on, boot ROM verifies the initial content of + * boot media, loads it into low memory, and begins executing it + * in 32-bit mode. The image loaded is "l-loader.bin", which contains + * a small amount code along with an embedded ARM Trusted Firmware + * BL1 image. The main purpose of "l-loader" is to prepare the + * processor to execute the BL1 image in 64-bit mode, and to trigger + * that execution. + * + * Also embedded in "l-loader.bin" is a FIP image that contains + * other ARM Trusted Firmware images: BL2; BL31; and for BL33, + * U-Boot. When BL1 executes, it unpacks the BL2 image from the FIP + * image into a region of memory set aside to hold it. Similarly, + * BL2 unpacks BL31 into memory reserved for it, and unpacks U-Boot + * into high memory. + * + * Because the BL1 code is embedded in "l-loader", its base address + * in memory is derived from the base address of the "l-loader" + * text section, together with an offset. Memory space for BL2 is + * reserved immediately following BL1, and memory space is reserved + * for BL31 after that. ARM Trusted Firmware requires each of these + * memory regions to be aligned on page boundaries, so the size of + * each region is a multiple of a page size (ending in 000). Note + * that ARM Trusted Firmware requires the read-only and read-write + * regions of memory used for BL1 to be defined separately. + * + * --------------------- + * | (unused memory) | + * +-------------------+ - - - - - + * | (l-loader text) | \ + * +-------------------+ \ + * | BL1 (read-only) | \ \ + * |- - - - - - - - - -| | | + * | BL1 (read-write) | | | + * +-------------------+ > BL Memory | + * | Reserved for BL2 | | > "l-loader.bin" image + * +-------------------+ | | + * | Reserved for BL31 | / | + * +-------------------+ | + * . . . / + * +-------------------+ / + * | FIP | / + * +-------------------+ - - - - - + * . . . + * | (unused memory) | + * . . . + * +-------------------+ + * |Reserved for U-Boot| + * +-------------------+ + * . . . + * | (unused memory) | + * --------------------- + * + * The size of each of these regions is defined below. The base + * address of the "l-loader" TEXT section and the offset of the BL1 + * image within that serve as anchors for defining the positions of + * all other regions. The FIP is placed in a section of its own. + * + * A "BASE" is the memory address of the start of a region; a "LIMIT" + * marks its end. A "SIZE" is the size of a region (in bytes). An + * "OFFSET" is an offset to the start of a region relative to the + * base of the "l-loader" TEXT section (also a multiple of page size). + */ +#define LLOADER_TEXT_BASE 0x02001000 /* page aligned */ +#define BL1_OFFSET 0x0000D000 /* page multiple */ +#define FIP_BASE 0x02040000 + +/* + * FIP_BASE_EMMC = 0x40000 - 0x1000 + * = fip.bin offset - l-loader text offset + * in l-loader.bin + */ +#define FIP_BASE_EMMC 0x0003f000 + +#define BL1_RO_SIZE 0x00008000 /* page multiple */ +#define BL1_RW_SIZE 0x00008000 /* page multiple */ +#define BL1_SIZE (BL1_RO_SIZE + BL1_RW_SIZE) +#define BL2_SIZE 0x0000d000 /* page multiple */ +#define BL31_SIZE 0x00014000 +#if !POPLAR_RECOVERY +/* + * emmc partition1 4096KB + * - l-loader.bin 1984KB + * |- l-loader + bl1.bin 256KB + * |- fip.bin 1728KB (0x001b0000) + * - u-boot persistent data 64KB + * - uefi persistent data 2048KB + */ +#define FIP_SIZE 0x001b0000 /* absolute max */ +#else +/* + * same as above, but bootrom can only load an image (l-loader.bin) of + * 1024KB max, so after deducting the size of l-loader + bl1.bin (256KB), + * that leaves 768KB (0x000c0000) for fip.bin + */ +#define FIP_SIZE 0x000c0000 /* absolute max */ +#endif + + /* BL1_OFFSET */ /* (Defined above) */ +#define BL1_BASE (LLOADER_TEXT_BASE + BL1_OFFSET) +#define BL1_LIMIT (BL1_BASE + BL1_SIZE) + +#define BL1_RO_OFFSET (BL1_OFFSET) +#define BL1_RO_BASE (LLOADER_TEXT_BASE + BL1_RO_OFFSET) +#define BL1_RO_LIMIT (BL1_RO_BASE + BL1_RO_SIZE) + +#define BL1_RW_OFFSET (BL1_RO_OFFSET + BL1_RO_SIZE) +#define BL1_RW_BASE (LLOADER_TEXT_BASE + BL1_RW_OFFSET) +#define BL1_RW_LIMIT (BL1_RW_BASE + BL1_RW_SIZE) + +#define BL2_OFFSET (BL1_OFFSET + BL1_SIZE) +#define BL2_BASE (LLOADER_TEXT_BASE + BL2_OFFSET) +#define BL2_LIMIT (BL2_BASE + BL2_SIZE) + +#define BL31_OFFSET (BL2_OFFSET + BL2_SIZE) +#define BL31_BASE (LLOADER_TEXT_BASE + BL31_OFFSET) +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +#endif /* POPLAR_LAYOUT_H */ |