diff options
Diffstat (limited to 'plat/imx/imx7/common')
| -rw-r--r-- | plat/imx/imx7/common/imx7.mk | 112 | ||||
| -rw-r--r-- | plat/imx/imx7/common/imx7_bl2_el3_common.c | 198 | ||||
| -rw-r--r-- | plat/imx/imx7/common/imx7_bl2_mem_params_desc.c | 81 | ||||
| -rw-r--r-- | plat/imx/imx7/common/imx7_helpers.S | 59 | ||||
| -rw-r--r-- | plat/imx/imx7/common/imx7_image_load.c | 24 | ||||
| -rw-r--r-- | plat/imx/imx7/common/imx7_rotpk.S | 15 | ||||
| -rw-r--r-- | plat/imx/imx7/common/imx7_trusted_boot.c | 36 |
7 files changed, 525 insertions, 0 deletions
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk new file mode 100644 index 0000000..f4f5bfc --- /dev/null +++ b/plat/imx/imx7/common/imx7.mk @@ -0,0 +1,112 @@ +# +# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Architecture +$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)) + +TF_CFLAGS += -mfpu=neon +ASFLAGS += -mfpu=neon + +# Platform +PLAT_INCLUDES := -Idrivers/imx/uart \ + -Iplat/imx/common/include \ + -Iplat/imx/imx7/include \ + -Idrivers/imx/timer \ + -Idrivers/imx/usdhc \ + -Iinclude/common/tbbr + +# Translation tables library +include lib/xlat_tables_v2/xlat_tables.mk + +BL2_SOURCES += common/desc_image_load.c \ + drivers/delay_timer/delay_timer.c \ + drivers/mmc/mmc.c \ + drivers/io/io_block.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + drivers/imx/timer/imx_gpt.c \ + drivers/imx/uart/imx_uart.c \ + drivers/imx/uart/imx_crash_uart.S \ + lib/aarch32/arm32_aeabi_divmod.c \ + lib/aarch32/arm32_aeabi_divmod_a32.S \ + lib/cpus/aarch32/cortex_a7.S \ + lib/optee/optee_utils.c \ + plat/imx/common/imx_aips.c \ + plat/imx/common/imx_caam.c \ + plat/imx/common/imx_clock.c \ + plat/imx/common/imx_csu.c \ + plat/imx/common/imx_io_mux.c \ + plat/imx/common/imx_snvs.c \ + plat/imx/common/imx_wdog.c \ + plat/imx/common/imx7_clock.c \ + plat/imx/imx7/common/imx7_bl2_mem_params_desc.c \ + plat/imx/imx7/common/imx7_bl2_el3_common.c \ + plat/imx/imx7/common/imx7_helpers.S \ + plat/imx/imx7/common/imx7_image_load.c \ + plat/imx/common/imx_io_storage.c \ + plat/imx/common/aarch32/imx_uart_console.S \ + ${XLAT_TABLES_LIB_SRCS} + +ifneq (${TRUSTED_BOARD_BOOT},0) + +include drivers/auth/mbedtls/mbedtls_crypto.mk +include drivers/auth/mbedtls/mbedtls_x509.mk + +AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot_common.c + +BL2_SOURCES += ${AUTH_SOURCES} \ + plat/common/tbbr/plat_tbbr.c \ + plat/imx/imx7/common/imx7_trusted_boot.c \ + plat/imx/imx7/common/imx7_rotpk.S \ + drivers/auth/tbbr/tbbr_cot_bl2.c + +ROT_KEY = $(BUILD_PLAT)/rot_key.pem +ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin + +$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) +$(eval $(call MAKE_LIB_DIRS)) + +$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH) + +certificates: $(ROT_KEY) + +$(ROT_KEY): | $(BUILD_PLAT) + @echo " OPENSSL $@" + @if [ ! -f $(ROT_KEY) ]; then \ + ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \ + fi + +$(ROTPK_HASH): $(ROT_KEY) + @echo " OPENSSL $@" + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null +endif + +# Add the build options to pack BLx images and kernel device tree +# in the FIP if the platform requires. +ifneq ($(BL2),) +$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) +endif +ifneq ($(BL32_EXTRA1),) +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) +endif +ifneq ($(BL32_EXTRA2),) +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) +endif +ifneq ($(HW_CONFIG),) +$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config)) +endif + +# Verify build config +# ------------------- + +ifeq (${ARCH},aarch64) + $(error Error: AArch64 not supported on i.mx7) +endif diff --git a/plat/imx/imx7/common/imx7_bl2_el3_common.c b/plat/imx/imx7/common/imx7_bl2_el3_common.c new file mode 100644 index 0000000..4e5028c --- /dev/null +++ b/plat/imx/imx7/common/imx7_bl2_el3_common.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <platform_def.h> + +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/desc_image_load.h> +#include <drivers/mmc.h> +#include <lib/xlat_tables/xlat_mmu_helpers.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <lib/mmio.h> +#include <lib/optee_utils.h> +#include <lib/utils.h> + +#include <imx_aips.h> +#include <imx_caam.h> +#include <imx_clock.h> +#include <imx_csu.h> +#include <imx_gpt.h> +#include <imx_uart.h> +#include <imx_snvs.h> +#include <imx_wdog.h> +#include <imx7_def.h> + +#ifndef AARCH32_SP_OPTEE +#error "Must build with OPTEE support included" +#endif + +uintptr_t plat_get_ns_image_entrypoint(void) +{ + return IMX7_UBOOT_BASE; +} + +static uint32_t imx7_get_spsr_for_bl32_entry(void) +{ + return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, + DISABLE_ALL_EXCEPTIONS); +} + +static uint32_t imx7_get_spsr_for_bl33_entry(void) +{ + return SPSR_MODE32(MODE32_svc, + plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); +} + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); + bl_mem_params_node_t *hw_cfg_mem_params = NULL; + + bl_mem_params_node_t *pager_mem_params = NULL; + bl_mem_params_node_t *paged_mem_params = NULL; + + assert(bl_mem_params); + + switch (image_id) { + case BL32_IMAGE_ID: + pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); + assert(pager_mem_params); + + paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); + assert(paged_mem_params); + + err = parse_optee_header(&bl_mem_params->ep_info, + &pager_mem_params->image_info, + &paged_mem_params->image_info); + if (err != 0) + WARN("OPTEE header parse error.\n"); + + /* + * When ATF loads the DTB the address of the DTB is passed in + * arg2, if an hw config image is present use the base address + * as DTB address an pass it as arg2 + */ + hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); + + bl_mem_params->ep_info.args.arg0 = + bl_mem_params->ep_info.args.arg1; + bl_mem_params->ep_info.args.arg1 = 0; + if (hw_cfg_mem_params) + bl_mem_params->ep_info.args.arg2 = + hw_cfg_mem_params->image_info.image_base; + else + bl_mem_params->ep_info.args.arg2 = 0; + bl_mem_params->ep_info.args.arg3 = 0; + bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl32_entry(); + break; + + case BL33_IMAGE_ID: + /* AArch32 only core: OP-TEE expects NSec EP in register LR */ + pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); + assert(pager_mem_params); + pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; + + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = imx7_get_spsr_for_bl33_entry(); + break; + + default: + /* Do nothing in default case */ + break; + } + + return err; +} + +void bl2_el3_plat_arch_setup(void) +{ + /* Setup the MMU here */ +} + +static void imx7_setup_system_counter(void) +{ + unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; + + /* Set the frequency table index to our target frequency */ + write_cntfrq(freq); + + /* Enable system counter @ frequency table index 0, halt on debug */ + mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN); +} + +static void imx7_setup_wdog_clocks(void) +{ + uint32_t wdog_en_bits = (uint32_t)WDOG_DEFAULT_CLK_SELECT; + + imx_clock_set_wdog_clk_root_bits(wdog_en_bits); + imx_clock_enable_wdog(0); + imx_clock_enable_wdog(1); + imx_clock_enable_wdog(2); + imx_clock_enable_wdog(3); +} + + +/* + * bl2_el3_early_platform_setup() + * MMU off + */ +void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) +{ + static console_t console; + int console_scope = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME; + + /* Initialize common components */ + imx_aips_init(); + imx_csu_init(); + imx_snvs_init(); + imx_gpt_ops_init(GPT1_BASE_ADDR); + imx_clock_init(); + imx7_setup_system_counter(); + imx7_setup_wdog_clocks(); + + /* Platform specific setup */ + imx7_platform_setup(arg1, arg2, arg3, arg4); + + /* Init UART, clock should be enabled in imx7_platform_setup() */ + console_imx_uart_register(PLAT_IMX7_BOOT_UART_BASE, + PLAT_IMX7_BOOT_UART_CLK_IN_HZ, + PLAT_IMX7_CONSOLE_BAUDRATE, + &console); + console_set_scope(&console, console_scope); + + /* Open handles to persistent storage */ + plat_imx_io_setup(); + + /* Setup higher-level functionality CAAM, RTC etc */ + imx_caam_init(); + imx_wdog_init(); + + /* Print out the expected memory map */ + VERBOSE("\tOPTEE 0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT); + VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); + VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); + VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX_FIP_BASE, IMX_FIP_LIMIT); + VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT); + VERBOSE("\tDTB 0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT); + VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT); +} + +/* + * bl2_platform_setup() + * MMU on - enabled by bl2_el3_plat_arch_setup() + */ +void bl2_platform_setup(void) +{ +} diff --git a/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c new file mode 100644 index 0000000..f9b2983 --- /dev/null +++ b/plat/imx/imx7/common/imx7_bl2_mem_params_desc.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#include <common/bl_common.h> +#include <common/desc_image_load.h> +#include <plat/common/platform.h> + +static bl_mem_params_node_t bl2_mem_params_descs[] = { + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL32_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, + image_info_t, 0), + + .image_info.image_base = IMX7_OPTEE_BASE, + .image_info.image_max_size = IMX7_OPTEE_SIZE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + { + .image_id = BL32_EXTRA1_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, + image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = IMX7_OPTEE_BASE, + .image_info.image_max_size = IMX7_OPTEE_SIZE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + { + /* This is a zero sized image so we don't set base or size */ + .image_id = BL32_EXTRA2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + NON_SECURE | EXECUTABLE), + # ifdef PRELOADED_BL33_BASE + .ep_info.pc = PRELOADED_BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_SKIP_LOADING), + # else + .ep_info.pc = BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = IMX7_UBOOT_BASE, + .image_info.image_max_size = IMX7_UBOOT_SIZE, + # endif /* PRELOADED_BL33_BASE */ + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs); diff --git a/plat/imx/imx7/common/imx7_helpers.S b/plat/imx/imx7/common/imx7_helpers.S new file mode 100644 index 0000000..661fd29 --- /dev/null +++ b/plat/imx/imx7/common/imx7_helpers.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) Linaro 2018-2019 Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <assert_macros.S> +#include <platform_def.h> +#include <imx_hab.h> + + .globl platform_mem_init + .globl plat_get_my_entrypoint + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + .globl plat_panic_handler + + /* --------------------------------------------- + * int plat_mem_init(void) + * Function to initialize memory. + * The HAB hands off the DDR controller already + * setup and ready to use. + * Implement the mandatory function as a NOP + * --------------------------------------------- + */ +func platform_mem_init + bx lr +endfunc platform_mem_init + +func plat_get_my_entrypoint + mov r0, #0 + bx lr +endfunc plat_get_my_entrypoint + +func plat_crash_console_init + mov_imm r0, PLAT_IMX7_BOOT_UART_BASE + mov_imm r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ + mov_imm r2, PLAT_IMX7_CONSOLE_BAUDRATE + b imx_crash_uart_init +endfunc plat_crash_console_init + +func plat_crash_console_putc + mov_imm r1, PLAT_IMX7_BOOT_UART_BASE + b imx_crash_uart_putc +endfunc plat_crash_console_putc + +func plat_crash_console_flush + /* Placeholder */ + mov r0, #0 + bx lr +endfunc plat_crash_console_flush + +func plat_panic_handler + mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE + ldr r3, [r3, #0] + blx r3 +endfunc plat_panic_handler diff --git a/plat/imx/imx7/common/imx7_image_load.c b/plat/imx/imx7/common/imx7_image_load.c new file mode 100644 index 0000000..c3e47b9 --- /dev/null +++ b/plat/imx/imx7/common/imx7_image_load.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/bl_common.h> +#include <common/desc_image_load.h> +#include <plat/common/platform.h> + +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/plat/imx/imx7/common/imx7_rotpk.S b/plat/imx/imx7/common/imx7_rotpk.S new file mode 100644 index 0000000..8bd53c2 --- /dev/null +++ b/plat/imx/imx7/common/imx7_rotpk.S @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global imx7_rotpk_hash + .global imx7_rotpk_hash_end +imx7_rotpk_hash: + /* DER header */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* SHA256 */ + .incbin ROTPK_HASH +imx7_rotpk_hash_end: diff --git a/plat/imx/imx7/common/imx7_trusted_boot.c b/plat/imx/imx7/common/imx7_trusted_boot.c new file mode 100644 index 0000000..cd27128 --- /dev/null +++ b/plat/imx/imx7/common/imx7_trusted_boot.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat/common/platform.h> + +extern char imx7_rotpk_hash[], imx7_rotpk_hash_end[]; + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + *key_ptr = imx7_rotpk_hash; + *key_len = imx7_rotpk_hash_end - imx7_rotpk_hash; + *flags = ROTPK_IS_HASH; + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = 0; + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + return get_mbedtls_heap_helper(heap_addr, heap_size); +} |