diff options
Diffstat (limited to 'plat/imx/imx8m/imx8mm/include')
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/gpc_reg.h | 129 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/imx8mm_private.h | 15 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/imx_sec_def.h | 216 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/platform_def.h | 176 |
4 files changed, 536 insertions, 0 deletions
diff --git a/plat/imx/imx8m/imx8mm/include/gpc_reg.h b/plat/imx/imx8m/imx8mm/include/gpc_reg.h new file mode 100644 index 0000000..1a4eae5 --- /dev/null +++ b/plat/imx/imx8m/imx8mm/include/gpc_reg.h @@ -0,0 +1,129 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef GPC_REG_H +#define GPC_REG_H + +#define LPCR_A53_BSC 0x0 +#define LPCR_A53_BSC2 0x108 +#define LPCR_A53_AD 0x4 +#define LPCR_M4 0x8 +#define SLPCR 0x14 +#define MST_CPU_MAPPING 0x18 +#define MLPCR 0x20 +#define PGC_ACK_SEL_A53 0x24 +#define IMR1_CORE0_A53 0x30 +#define IMR1_CORE1_A53 0x40 +#define IMR1_CORE2_A53 0x1C0 +#define IMR1_CORE3_A53 0x1D0 +#define IMR1_CORE0_M4 0x50 +#define SLT0_CFG 0xB0 +#define GPC_PU_PWRHSK 0x1FC +#define PGC_CPU_0_1_MAPPING 0xEC +#define CPU_PGC_UP_TRG 0xF0 +#define PU_PGC_UP_TRG 0xF8 +#define CPU_PGC_DN_TRG 0xFC +#define PU_PGC_DN_TRG 0x104 +#define LPS_CPU1 0x114 +#define A53_CORE0_PGC 0x800 +#define A53_PLAT_PGC 0x900 +#define PLAT_PGC_PCR 0x900 +#define NOC_PGC_PCR 0xa40 +#define PGC_SCU_TIMING 0x910 + +#define MASK_DSM_TRIGGER_A53 BIT(31) +#define IRQ_SRC_A53_WUP BIT(30) +#define IRQ_SRC_A53_WUP_SHIFT 30 +#define IRQ_SRC_C1 BIT(29) +#define IRQ_SRC_C0 BIT(28) +#define IRQ_SRC_C3 BIT(23) +#define IRQ_SRC_C2 BIT(22) +#define CPU_CLOCK_ON_LPM BIT(14) +#define A53_CLK_ON_LPM BIT(14) +#define MASTER0_LPM_HSK BIT(6) +#define MASTER1_LPM_HSK BIT(7) +#define MASTER2_LPM_HSK BIT(8) + +#define L2PGE BIT(31) +#define EN_L2_WFI_PDN BIT(5) +#define EN_PLAT_PDN BIT(4) + +#define SLPCR_EN_DSM BIT(31) +#define SLPCR_RBC_EN BIT(30) +#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17) +#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16) +#define SLPCR_VSTBY BIT(2) +#define SLPCR_SBYOS BIT(1) +#define SLPCR_BYPASS_PMIC_READY BIT(0) +#define SLPCR_RBC_COUNT_SHIFT 24 +#define SLPCR_STBY_COUNT_SHFT 3 + +#define A53_DUMMY_PDN_ACK BIT(15) +#define A53_DUMMY_PUP_ACK BIT(31) +#define A53_PLAT_PDN_ACK BIT(2) +#define A53_PLAT_PUP_ACK BIT(18) +#define NOC_PDN_SLT_CTRL BIT(10) +#define NOC_PUP_SLT_CTRL BIT(11) +#define NOC_PGC_PDN_ACK BIT(3) +#define NOC_PGC_PUP_ACK BIT(19) + +#define PLAT_PUP_SLT_CTRL BIT(9) +#define PLAT_PDN_SLT_CTRL BIT(8) + +#define SLT_PLAT_PDN BIT(8) +#define SLT_PLAT_PUP BIT(9) + +#define MASTER1_MAPPING BIT(1) +#define MASTER2_MAPPING BIT(2) + +#define MIPI_PWR_REQ BIT(0) +#define PCIE_PWR_REQ BIT(1) +#define OTG1_PWR_REQ BIT(2) +#define OTG2_PWR_REQ BIT(3) +#define HSIOMIX_PWR_REQ BIT(4) +#define DDRMIX_PWR_REQ BIT(5) +#define GPU2D_PWR_REQ BIT(6) +#define GPUMIX_PWR_REQ BIT(7) +#define VPUMIX_PWR_REQ BIT(8) +#define GPU3D_PWR_REQ BIT(9) +#define DISPMIX_PWR_REQ BIT(10) +#define VPU_G1_PWR_REQ BIT(11) +#define VPU_G2_PWR_REQ BIT(12) +#define VPU_H1_PWR_REQ BIT(13) + +#define DDRMIX_ADB400_SYNC BIT(2) +#define HSIOMIX_ADB400_SYNC (0x3 << 5) +#define DISPMIX_ADB400_SYNC BIT(7) +#define VPUMIX_ADB400_SYNC BIT(8) +#define GPU3D_ADB400_SYNC BIT(9) +#define GPU2D_ADB400_SYNC BIT(10) +#define GPUMIX_ADB400_SYNC BIT(11) +#define DDRMIX_ADB400_ACK BIT(20) +#define HSIOMIX_ADB400_ACK (0x3 << 23) +#define DISPMIX_ADB400_ACK BIT(25) +#define VPUMIX_ADB400_ACK BIT(26) +#define GPU3D_ADB400_ACK BIT(27) +#define GPU2D_ADB400_ACK BIT(28) +#define GPUMIX_ADB400_ACK BIT(29) + +#define MIPI_PGC 0xc00 +#define PCIE_PGC 0xc40 +#define OTG1_PGC 0xc80 +#define OTG2_PGC 0xcc0 +#define HSIOMIX_PGC 0xd00 +#define DDRMIX_PGC 0xd40 +#define GPU2D_PGC 0xd80 +#define GPUMIX_PGC 0xdc0 +#define VPUMIX_PGC 0xe00 +#define GPU3D_PGC 0xe40 +#define DISPMIX_PGC 0xe80 +#define VPU_G1_PGC 0xec0 +#define VPU_G2_PGC 0xf00 +#define VPU_H1_PGC 0xf40 + +#define IRQ_IMR_NUM U(4) + +#endif /* GPC_REG_H */ diff --git a/plat/imx/imx8m/imx8mm/include/imx8mm_private.h b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h new file mode 100644 index 0000000..5e0ef97 --- /dev/null +++ b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX8MM_PRIVATE_H +#define IMX8MM_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_imx_io_setup(void); + +#endif /* IMX8MM_PRIVATE_H */ diff --git a/plat/imx/imx8m/imx8mm/include/imx_sec_def.h b/plat/imx/imx8m/imx8mm/include/imx_sec_def.h new file mode 100644 index 0000000..6215983 --- /dev/null +++ b/plat/imx/imx8m/imx8mm/include/imx_sec_def.h @@ -0,0 +1,216 @@ +/* + * Copyright 2020-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX_SEC_DEF_H +#define IMX_SEC_DEF_H + +/* RDC MDA index */ +enum rdc_mda_idx { + RDC_MDA_A53 = 0, + RDC_MDA_M4 = 1, + RDC_MDA_PCIE_CTRL1 = 2, + RDC_MDA_SDMA3p = 3, + RDC_MDA_VPU_Decoders = 4, + RDC_MDA_LCDIF = 5, + RDC_MDA_CSI1 = 6, + RDC_MDA_SDMA3b = 7, + RDC_MDA_Coresight = 8, + RDC_MDA_DAP = 9, + RDC_MDA_CAAM = 10, + RDC_MDA_SDMA1p = 11, + RDC_MDA_SDMA1b = 12, + RDC_MDA_APBHDMA = 13, + RDC_MDA_NAND = 14, + RDC_MDA_uSDHC1 = 15, + RDC_MDA_uSDHC2 = 16, + RDC_MDA_uSDHC3 = 17, + RDC_MDA_GPU = 18, + RDC_MDA_USB1 = 19, + RDC_MDA_USB2 = 20, + RDC_MDA_TESTPORT = 21, + RDC_MDA_ENET1_TX = 22, + RDC_MDA_ENET1_RX = 23, + RDC_MDA_SDMA2p = 24, + RDC_MDA_SDMA2b = 24, + RDC_MDA_SDMA2_to_SPBA2 = 24, + RDC_MDA_SDMA3_to_SPBA2 = 25, + RDC_MDA_SDMA1_to_SPBA1 = 26, +}; + +/* RDC Peripherals index */ +enum rdc_pdap_idx { + RDC_PDAP_GPIO2 = 1, + RDC_PDAP_GPIO3 = 2, + RDC_PDAP_GPIO4 = 3, + RDC_PDAP_GPIO5 = 4, + RDC_PDAP_ANA_TSENSOR = 6, + RDC_PDAP_ANA_OSC = 7, + RDC_PDAP_WDOG1 = 8, + RDC_PDAP_WDOG2 = 9, + RDC_PDAP_WDOG3 = 10, + RDC_PDAP_SDMA3 = 11, + RDC_PDAP_SDMA2 = 12, + RDC_PDAP_GPT1 = 13, + RDC_PDAP_GPT2 = 14, + RDC_PDAP_GPT3 = 15, + RDC_PDAP_ROMCP = 17, + RDC_PDAP_IOMUXC = 19, + RDC_PDAP_IOMUXC_GPR = 20, + RDC_PDAP_OCOTP_CTRL = 21, + RDC_PDAP_ANA_PLL = 22, + RDC_PDAP_SNVS_HP = 23, + RDC_PDAP_CCM = 24, + RDC_PDAP_SRC = 25, + RDC_PDAP_GPC = 26, + RDC_PDAP_SEMAPHORE1 = 27, + RDC_PDAP_SEMAPHORE2 = 28, + RDC_PDAP_RDC = 29, + RDC_PDAP_CSU = 30, + RDC_PDAP_LCDIF = 32, + RDC_PDAP_MIPI_DSI = 33, + RDC_PDAP_CSI = 34, + RDC_PDAP_MIPI_CSI = 35, + RDC_PDAP_USB1 = 36, + RDC_PDAP_PWM1 = 38, + RDC_PDAP_PWM2 = 39, + RDC_PDAP_PWM3 = 40, + RDC_PDAP_PWM4 = 41, + RDC_PDAP_System_Counter_RD = 42, + RDC_PDAP_System_Counter_CMP = 43, + RDC_PDAP_System_Counter_CTRL = 44, + RDC_PDAP_GPT6 = 46, + RDC_PDAP_GPT5 = 47, + RDC_PDAP_GPT4 = 48, + RDC_PDAP_TZASC = 56, + RDC_PDAP_USB2 = 59, + RDC_PDAP_PERFMON1 = 60, + RDC_PDAP_PERFMON2 = 61, + RDC_PDAP_PLATFORM_CTRL = 62, + RDC_PDAP_QoSC = 63, + RDC_PDAP_I2C1 = 66, + RDC_PDAP_I2C2 = 67, + RDC_PDAP_I2C3 = 68, + RDC_PDAP_I2C4 = 69, + RDC_PDAP_UART4 = 70, + RDC_PDAP_MU_A = 74, + RDC_PDAP_MU_B = 75, + RDC_PDAP_SEMAPHORE_HS = 76, + RDC_PDAP_SAI1 = 78, + RDC_PDAP_SAI2 = 79, + RDC_PDAP_SAI3 = 80, + RDC_PDAP_SAI5 = 82, + RDC_PDAP_SAI6 = 83, + RDC_PDAP_uSDHC1 = 84, + RDC_PDAP_uSDHC2 = 85, + RDC_PDAP_uSDHC3 = 86, + RDC_PDAP_PCIE_PHY1 = 88, + RDC_PDAP_SPBA2 = 90, + RDC_PDAP_QSPI = 91, + RDC_PDAP_SDMA1 = 93, + RDC_PDAP_ENET1 = 94, + RDC_PDAP_SPDIF1 = 97, + RDC_PDAP_eCSPI1 = 98, + RDC_PDAP_eCSPI2 = 99, + RDC_PDAP_eCSPI3 = 100, + RDC_PDAP_MICFIL = 101, + RDC_PDAP_UART1 = 102, + RDC_PDAP_UART3 = 104, + RDC_PDAP_UART2 = 105, + RDC_PDAP_SPDIF2 = 106, + RDC_PDAP_SPBA1 = 111, + RDC_PDAP_CAAM = 114, +}; + +enum csu_csl_idx { + CSU_CSL_GPIO1 = 0, + CSU_CSL_GPIO2 = 1, + CSU_CSL_GPIO3 = 2, + CSU_CSL_GPIO4 = 3, + CSU_CSL_GPIO5 = 4, + CSU_CSL_ANA_TSENSOR = 6, + CSU_CSL_ANA_OSC = 7, + CSU_CSL_WDOG1 = 8, + CSU_CSL_WDOG2 = 9, + CSU_CSL_WDOG3 = 10, + CSU_CSL_SDMA2 = 12, + CSU_CSL_GPT1 = 13, + CSU_CSL_GPT2 = 14, + CSU_CSL_GPT3 = 15, + CSU_CSL_ROMCP = 17, + CSU_CSL_LCDIF = 18, + CSU_CSL_IOMUXC = 19, + CSU_CSL_IOMUXC_GPR = 20, + CSU_CSL_OCOTP_CTRL = 21, + CSU_CSL_ANA_PLL = 22, + CSU_CSL_SNVS_HP = 23, + CSU_CSL_CCM = 24, + CSU_CSL_SRC = 25, + CSU_CSL_GPC = 26, + CSU_CSL_SEMAPHORE1 = 27, + CSU_CSL_SEMAPHORE2 = 28, + CSU_CSL_RDC = 29, + CSU_CSL_CSU = 30, + CSU_CSL_DC_MST0 = 32, + CSU_CSL_DC_MST1 = 33, + CSU_CSL_DC_MST2 = 34, + CSU_CSL_DC_MST3 = 35, + CSU_CSL_PWM1 = 38, + CSU_CSL_PWM2 = 39, + CSU_CSL_PWM3 = 40, + CSU_CSL_PWM4 = 41, + CSU_CSL_System_Counter_RD = 42, + CSU_CSL_System_Counter_CMP = 43, + CSU_CSL_System_Counter_CTRL = 44, + CSU_CSL_GPT6 = 46, + CSU_CSL_GPT5 = 47, + CSU_CSL_GPT4 = 48, + CSU_CSL_TZASC = 56, + CSU_CSL_MTR = 59, + CSU_CSL_PERFMON1 = 60, + CSU_CSL_PERFMON2 = 61, + CSU_CSL_PLATFORM_CTRL = 62, + CSU_CSL_QoSC = 63, + CSU_CSL_MIPI_PHY = 64, + CSU_CSL_MIPI_DSI = 65, + CSU_CSL_I2C1 = 66, + CSU_CSL_I2C2 = 67, + CSU_CSL_I2C3 = 68, + CSU_CSL_I2C4 = 69, + CSU_CSL_UART4 = 70, + CSU_CSL_MIPI_CSI1 = 71, + CSU_CSL_MIPI_CSI_PHY1 = 72, + CSU_CSL_CSI1 = 73, + CSU_CSL_MU_A = 74, + CSU_CSL_MU_B = 75, + CSU_CSL_SEMAPHORE_HS = 76, + CSU_CSL_SAI1 = 78, + CSU_CSL_SAI6 = 80, + CSU_CSL_SAI5 = 81, + CSU_CSL_SAI4 = 82, + CSU_CSL_uSDHC1 = 84, + CSU_CSL_uSDHC2 = 85, + CSU_CSL_MIPI_CSI2 = 86, + CSU_CSL_MIPI_CSI_PHY2 = 87, + CSU_CSL_CSI2 = 88, + CSU_CSL_SPBA2 = 90, + CSU_CSL_QSPI = 91, + CSU_CSL_SDMA1 = 93, + CSU_CSL_ENET1 = 94, + CSU_CSL_SPDIF1 = 97, + CSU_CSL_eCSPI1 = 98, + CSU_CSL_eCSPI2 = 99, + CSU_CSL_eCSPI3 = 100, + CSU_CSL_UART1 = 102, + CSU_CSL_UART3 = 104, + CSU_CSL_UART2 = 105, + CSU_CSL_SPDIF2 = 106, + CSU_CSL_SAI2 = 107, + CSU_CSL_SAI3 = 108, + CSU_CSL_SPBA1 = 111, + CSU_CSL_CAAM = 114, +}; + +#endif /* IMX_SEC_DEF_H */ diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h new file mode 100644 index 0000000..65749f3 --- /dev/null +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE 0xB00 +#define CACHE_WRITEBACK_GRANULE 64 + +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(0) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) + +#define IMX_PWR_LVL0 MPIDR_AFFLVL0 +#define IMX_PWR_LVL1 MPIDR_AFFLVL1 +#define IMX_PWR_LVL2 MPIDR_AFFLVL2 + +#define PWR_DOMAIN_AT_MAX_LVL U(1) +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_OFF_STATE U(4) +#define PLAT_MAX_RET_STATE U(2) + +#define PLAT_WAIT_RET_STATE U(1) +#define PLAT_STOP_OFF_STATE U(3) + +#define PLAT_PRI_BITS U(3) +#define PLAT_SDEI_CRITICAL_PRI 0x10 +#define PLAT_SDEI_NORMAL_PRI 0x20 +#define PLAT_SDEI_SGI_PRIVATE U(9) + +#if defined(NEED_BL2) +#define BL2_BASE U(0x920000) +#define BL2_SIZE SZ_128K +#define BL2_LIMIT (BL2_BASE + BL2_SIZE) +#define BL31_BASE U(0x900000) +#define IMX_FIP_BASE U(0x40310000) +#define IMX_FIP_SIZE U(0x000300000) +#define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE) + +/* Define FIP image location on eMMC */ +#define IMX_FIP_MMC_BASE U(0x100000) + +#define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */ +#else +#define BL31_BASE U(0x920000) +#endif + +#define BL31_SIZE SZ_128K +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* non-secure uboot base */ +#define PLAT_NS_IMAGE_OFFSET U(0x40200000) +#define PLAT_NS_IMAGE_SIZE U(0x00200000) + +#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) + +/* GICv3 base address */ +#define PLAT_GICD_BASE U(0x38800000) +#define PLAT_GICR_BASE U(0x38880000) + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) + +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 16 + +#define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ + +#define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ + +#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE +#define PLAT_CRASH_UART_CLK_IN_HZ 24000000 +#define IMX_CONSOLE_BAUDRATE 115200 + +#define IMX_AIPSTZ1 U(0x301f0000) +#define IMX_AIPSTZ2 U(0x305f0000) +#define IMX_AIPSTZ3 U(0x309f0000) +#define IMX_AIPSTZ4 U(0x32df0000) + +#define IMX_AIPS_BASE U(0x30000000) +#define IMX_AIPS_SIZE U(0x3000000) +#define IMX_GPV_BASE U(0x32000000) +#define IMX_GPV_SIZE U(0x800000) +#define IMX_AIPS1_BASE U(0x30200000) +#define IMX_AIPS4_BASE U(0x32c00000) +#define IMX_ANAMIX_BASE U(0x30360000) +#define IMX_CCM_BASE U(0x30380000) +#define IMX_SRC_BASE U(0x30390000) +#define IMX_GPC_BASE U(0x303a0000) +#define IMX_RDC_BASE U(0x303d0000) +#define IMX_CSU_BASE U(0x303e0000) +#define IMX_WDOG_BASE U(0x30280000) +#define IMX_SNVS_BASE U(0x30370000) +#define IMX_NOC_BASE U(0x32700000) +#define IMX_TZASC_BASE U(0x32F80000) +#define IMX_IOMUX_GPR_BASE U(0x30340000) +#define IMX_CAAM_BASE U(0x30900000) +#define IMX_DDRC_BASE U(0x3d400000) +#define IMX_DDRPHY_BASE U(0x3c000000) +#define IMX_DDR_IPS_BASE U(0x3d000000) +#define IMX_DDR_IPS_SIZE U(0x1800000) +#define IMX_VPUMIX_BASE U(0x38330000) +#define IMX_VPUMIX_SIZE U(0x100000) +#define IMX_ROM_BASE U(0x0) +#define IMX_ROM_SIZE U(0x40000) +#define IMX_NS_OCRAM_BASE U(0x900000) +#define IMX_NS_OCRAM_SIZE U(0x20000) +#define IMX_CAAM_RAM_BASE U(0x100000) +#define IMX_CAAM_RAM_SIZE U(0x10000) +#define IMX_DRAM_BASE U(0x40000000) +#define IMX_DRAM_SIZE U(0xc0000000) + +#define GPV_BASE U(0x32000000) +#define GPV_SIZE U(0x800000) +#define IMX_GIC_BASE PLAT_GICD_BASE +#define IMX_GIC_SIZE U(0x200000) + +#define WDOG_WSR U(0x2) +#define WDOG_WCR_WDZST BIT(0) +#define WDOG_WCR_WDBG BIT(1) +#define WDOG_WCR_WDE BIT(2) +#define WDOG_WCR_WDT BIT(3) +#define WDOG_WCR_SRS BIT(4) +#define WDOG_WCR_WDA BIT(5) +#define WDOG_WCR_SRE BIT(6) +#define WDOG_WCR_WDW BIT(7) + +#define SRC_A53RCR0 U(0x4) +#define SRC_A53RCR1 U(0x8) +#define SRC_OTG1PHY_SCR U(0x20) +#define SRC_OTG2PHY_SCR U(0x24) +#define SRC_GPR1_OFFSET U(0x74) +#define SRC_GPR10_OFFSET U(0x98) +#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) + +#define SNVS_LPCR U(0x38) +#define SNVS_LPCR_SRTC_ENV BIT(0) +#define SNVS_LPCR_DP_EN BIT(5) +#define SNVS_LPCR_TOP BIT(6) + +#define IOMUXC_GPR10 U(0x28) +#define GPR_TZASC_EN BIT(0) +#define GPR_TZASC_EN_LOCK BIT(16) + +#define ANAMIX_MISC_CTL U(0x124) +#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) + +#define MAX_CSU_NUM U(64) + +#define OCRAM_S_BASE U(0x00180000) +#define OCRAM_S_SIZE U(0x8000) +#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) +#define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE + +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define IMX_WDOG_B_RESET + +#define MAX_IO_HANDLES 3U +#define MAX_IO_DEVICES 2U +#define MAX_IO_BLOCK_DEVICES 1U + +#define PLAT_IMX8M_DTO_BASE 0x53000000 +#define PLAT_IMX8M_DTO_MAX_SIZE 0x1000 +#define PLAT_IMX_EVENT_LOG_MAX_SIZE UL(0x400) |