diff options
Diffstat (limited to 'plat/imx/imx8qm')
| -rw-r--r-- | plat/imx/imx8qm/imx8qm_bl31_setup.c | 415 | ||||
| -rw-r--r-- | plat/imx/imx8qm/imx8qm_psci.c | 326 | ||||
| -rw-r--r-- | plat/imx/imx8qm/include/platform_def.h | 79 | ||||
| -rw-r--r-- | plat/imx/imx8qm/include/sec_rsrc.h | 32 | ||||
| -rw-r--r-- | plat/imx/imx8qm/platform.mk | 50 |
5 files changed, 902 insertions, 0 deletions
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c new file mode 100644 index 0000000..68eb534 --- /dev/null +++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <inttypes.h> +#include <stdint.h> +#include <stdbool.h> + +#include <platform_def.h> + +#include <arch_helpers.h> +#include <context.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <drivers/arm/cci.h> +#include <drivers/console.h> +#include <lib/el3_runtime/context_mgmt.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> + +#include <imx8qm_pads.h> +#include <imx8_iomux.h> +#include <imx8_lpuart.h> +#include <plat_imx8.h> +#include <sci/sci.h> +#include <sec_rsrc.h> + +static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE; +static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END; +static const unsigned long BL31_RO_START = BL_CODE_BASE; +static const unsigned long BL31_RO_END = BL_CODE_END; +static const unsigned long BL31_RW_END = BL_END; + +IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +#define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \ + (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) + +#if defined(IMX_USE_UART0) +#define IMX_RES_UART SC_R_UART_0 +#define IMX_PAD_UART_RX SC_P_UART0_RX +#define IMX_PAD_UART_TX SC_P_UART0_TX +#define IMX_PAD_UART_RTS_B SC_P_UART0_RTS_B +#define IMX_PAD_UART_CTS_B SC_P_UART0_CTS_B +#elif defined(IMX_USE_UART1) +#define IMX_RES_UART SC_R_UART_1 +#define IMX_PAD_UART_RX SC_P_UART1_RX +#define IMX_PAD_UART_TX SC_P_UART1_TX +#define IMX_PAD_UART_RTS_B SC_P_UART1_RTS_B +#define IMX_PAD_UART_CTS_B SC_P_UART1_CTS_B +#else +#error "Provide proper UART number in IMX_DEBUG_UART" +#endif + +const static int imx8qm_cci_map[] = { + CLUSTER0_CCI_SLVAE_IFACE, + CLUSTER1_CCI_SLVAE_IFACE +}; + +static const mmap_region_t imx_mmap[] = { + MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW), + {0} +}; + +static uint32_t get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned long mode; + uint32_t spsr; + + /* figure out what mode we enter the non-secure world */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + + return spsr; +} + +#if DEBUG_CONSOLE_A53 +static void lpuart32_serial_setbrg(unsigned int base, int baudrate) +{ + unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr; + unsigned int diff1, diff2, tmp, rate; + + if (baudrate == 0) + panic(); + + sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); + + baud_diff = baudrate; + osr = 0; + sbr = 0; + for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { + tmp_sbr = (rate / (baudrate * tmp_osr)); + if (tmp_sbr == 0) + tmp_sbr = 1; + + /* calculate difference in actual baud w/ current values */ + diff1 = rate / (tmp_osr * tmp_sbr) - baudrate; + diff2 = rate / (tmp_osr * (tmp_sbr + 1)); + + /* select best values between sbr and sbr+1 */ + if (diff1 > (baudrate - diff2)) { + diff1 = baudrate - diff2; + tmp_sbr++; + } + + if (diff1 <= baud_diff) { + baud_diff = diff1; + osr = tmp_osr; + sbr = tmp_sbr; + } + } + + tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); + + if ((osr > 3) && (osr < 8)) + tmp |= LPUART_BAUD_BOTHEDGE_MASK; + + tmp &= ~LPUART_BAUD_OSR_MASK; + tmp |= LPUART_BAUD_OSR(osr - 1); + tmp &= ~LPUART_BAUD_SBR_MASK; + tmp |= LPUART_BAUD_SBR(sbr); + + /* explicitly disable 10 bit mode & set 1 stop bit */ + tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); + + mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); +} + +static int lpuart32_serial_init(unsigned int base) +{ + unsigned int tmp; + + /* disable TX & RX before enabling clocks */ + tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); + tmp &= ~(CTRL_TE | CTRL_RE); + mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); + + mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0); + mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE)); + + mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0); + + /* provide data bits, parity, stop bit, etc */ + lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE); + + /* eight data bits no parity bit */ + tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); + tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); + mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); + + mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE); + + mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); + mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); + mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A); + + return 0; +} +#endif + +void mx8_partition_resources(void) +{ + sc_rm_pt_t secure_part, os_part; + sc_rm_mr_t mr, mr_record = 64; + sc_faddr_t start, end; + bool owned, owned2; + sc_err_t err; + int i; + + err = sc_rm_get_partition(ipc_handle, &secure_part); + + err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false, + false, false, false); + + err = sc_rm_set_parent(ipc_handle, os_part, secure_part); + + /* set secure resources to NOT-movable */ + for (i = 0; i < ARRAY_SIZE(secure_rsrcs); i++) { + err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i], + secure_rsrcs[i], false); + if (err) + ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", + secure_rsrcs[i], err); + } + + owned = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_0_PID0); + if (owned) { + err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0, + SC_R_M4_0_PID0, false); + if (err) + ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", + SC_R_M4_0_PID0, err); + } + + owned2 = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_1_PID0); + if (owned2) { + err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0, + SC_R_M4_1_PID0, false); + if (err) + ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", + SC_R_M4_1_PID0, err); + } + /* move all movable resources and pins to non-secure partition */ + err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true); + if (err) + ERROR("sc_rm_move_all: %u\n", err); + + /* iterate through peripherals to give NS OS part access */ + for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) { + err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i], + os_part, SC_RM_PERM_FULL); + if (err) + ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \ + ret %u\n", ns_access_allowed[i], err); + } + + if (owned) { + err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0, + SC_R_M4_0_PID0, true); + if (err) + ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", + SC_R_M4_0_PID0, err); + err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_0_PID0); + if (err) + ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n", + SC_R_M4_0_PID0, err); + } + if (owned2) { + err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0, + SC_R_M4_1_PID0, true); + if (err) + ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", + SC_R_M4_1_PID0, err); + err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_1_PID0); + if (err) + ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n", + SC_R_M4_1_PID0, err); + } + + /* + * sc_rm_set_peripheral_permissions + * sc_rm_set_memreg_permissions + * sc_rm_set_pin_movable + */ + + for (mr = 0; mr < 64; mr++) { + owned = sc_rm_is_memreg_owned(ipc_handle, mr); + if (owned) { + err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end); + if (err) + ERROR("Memreg get info failed, %u\n", mr); + NOTICE("Memreg %u 0x%" PRIx64 " -- 0x%" PRIx64 "\n", mr, start, end); + if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) { + mr_record = mr; /* Record the mr for ATF running */ + } else { + err = sc_rm_assign_memreg(ipc_handle, os_part, mr); + if (err) + ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 ", \ + err %d\n", start, end, err); + } + } + } + + if (mr_record != 64) { + err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end); + if (err) + ERROR("Memreg get info failed, %u\n", mr_record); + if ((BL31_LIMIT - 1) < end) { + err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end); + if (err) + ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", + (sc_faddr_t)BL31_LIMIT, end); + err = sc_rm_assign_memreg(ipc_handle, os_part, mr); + if (err) + ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", + (sc_faddr_t)BL31_LIMIT, end); + } + + if (start < (BL31_BASE - 1)) { + err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1); + if (err) + ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", + start, (sc_faddr_t)BL31_BASE - 1); + err = sc_rm_assign_memreg(ipc_handle, os_part, mr); + if (err) + ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", + start, (sc_faddr_t)BL31_BASE - 1); + } + } + + if (err) + NOTICE("Partitioning Failed\n"); + else + NOTICE("Non-secure Partitioning Succeeded\n"); + +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ +#if DEBUG_CONSOLE + static console_t console; +#endif + if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE) + panic(); + +#if DEBUG_CONSOLE_A53 + sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART, + SC_PM_PW_MODE_ON); + sc_pm_clock_rate_t rate = 80000000; + sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate); + sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false); + + /* configure UART pads */ + sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_RTS_B, UART_PAD_CTRL); + sc_pad_set(ipc_handle, IMX_PAD_UART_CTS_B, UART_PAD_CTRL); + lpuart32_serial_init(IMX_BOOT_UART_BASE); +#endif + +#if DEBUG_CONSOLE + console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE, &console); +#endif + + /* turn on MU1 for non-secure OS/Hypervisor */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); + /* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON); + sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0); + mmio_write_32(IMX_GPT_LPCG_BASE, mmio_read_32(IMX_GPT_LPCG_BASE) | (1 << 25)); + + /* + * create new partition for non-secure OS/Hypervisor + * uses global structs defined in sec_rsrc.h + */ + mx8_partition_resources(); + + bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; + bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + + /* init the first cluster's cci slave interface */ + cci_init(PLAT_CCI_BASE, imx8qm_cci_map, PLATFORM_CLUSTER_COUNT); + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); +} + +void bl31_plat_arch_setup(void) +{ + unsigned long ro_start = BL31_RO_START; + unsigned long ro_size = BL31_RO_END - BL31_RO_START; + unsigned long rw_start = BL31_RW_START; + unsigned long rw_size = BL31_RW_END - BL31_RW_START; +#if USE_COHERENT_MEM + unsigned long coh_start = BL31_COHERENT_RAM_START; + unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START; +#endif + + mmap_add_region(ro_start, ro_start, ro_size, + MT_RO | MT_MEMORY | MT_SECURE); + mmap_add_region(rw_start, rw_start, rw_size, + MT_RW | MT_MEMORY | MT_SECURE); + mmap_add(imx_mmap); + +#if USE_COHERENT_MEM + mmap_add_region(coh_start, coh_start, coh_size, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + /* setup xlat table */ + init_xlat_tables(); + /* enable the MMU */ + enable_mmu_el3(0); +} + +void bl31_platform_setup(void) +{ + plat_gic_driver_init(); + plat_gic_init(); +} + +entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) +{ + if (type == NON_SECURE) + return &bl33_image_ep_info; + if (type == SECURE) + return &bl32_image_ep_info; + + return NULL; +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return COUNTER_FREQUENCY; +} + +void bl31_plat_runtime_setup(void) +{ + return; +} diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c new file mode 100644 index 0000000..bdba37c --- /dev/null +++ b/plat/imx/imx8qm/imx8qm_psci.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> + +#include <arch.h> +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/arm/cci.h> +#include <drivers/arm/gicv3.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> + +#include <plat_imx8.h> +#include <sci/sci.h> + +#include "../../common/sci/imx8_mu.h" + +#define CORE_PWR_STATE(state) \ + ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define CLUSTER_PWR_STATE(state) \ + ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define SYSTEM_PWR_STATE(state) \ + ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + +const static int ap_core_index[PLATFORM_CORE_COUNT] = { + SC_R_A53_0, SC_R_A53_1, SC_R_A53_2, + SC_R_A53_3, SC_R_A72_0, SC_R_A72_1, +}; + +/* save gic dist/redist context when GIC is poewr down */ +static struct plat_gic_ctx imx_gicv3_ctx; +static unsigned int gpt_lpcg, gpt_reg[2]; + +static void imx_enable_irqstr_wakeup(void) +{ + uint32_t irq_mask; + gicv3_dist_ctx_t *dist_ctx = &imx_gicv3_ctx.dist_ctx; + + /* put IRQSTR into ON mode */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_ON); + + /* enable the irqsteer to handle wakeup irq */ + mmio_write_32(IMX_WUP_IRQSTR_BASE, 0x1); + for (int i = 0; i < 15; i++) { + irq_mask = dist_ctx->gicd_isenabler[i]; + mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x3c - 0x4 * i, irq_mask); + } + + /* set IRQSTR low power mode */ + if (imx_is_wakeup_src_irqsteer()) + sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_STBY); + else + sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_OFF); +} + +static void imx_disable_irqstr_wakeup(void) +{ + /* put IRQSTR into ON from STBY mode */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_ON); + + /* disable the irqsteer */ + mmio_write_32(IMX_WUP_IRQSTR_BASE, 0x0); + for (int i = 0; i < 16; i++) + mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x4 + 0x4 * i, 0x0); + + /* put IRQSTR into OFF mode */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_OFF); +} + +int imx_pwr_domain_on(u_register_t mpidr) +{ + int ret = PSCI_E_SUCCESS; + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + sc_pm_set_resource_power_mode(ipc_handle, cluster_id == 0 ? + SC_R_A53 : SC_R_A72, SC_PM_PW_MODE_ON); + + if (cluster_id == 1) + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON); + + if (sc_pm_set_resource_power_mode(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + SC_PM_PW_MODE_ON) != SC_ERR_NONE) { + ERROR("core %d power on failed!\n", cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id); + ret = PSCI_E_INTERN_FAIL; + } + + if (sc_pm_cpu_start(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + true, BL31_BASE) != SC_ERR_NONE) { + ERROR("boot core %d failed!\n", cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id); + ret = PSCI_E_INTERN_FAIL; + } + + return ret; +} + +void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + uint64_t mpidr = read_mpidr_el1(); + + if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + + plat_gic_pcpu_init(); + plat_gic_cpuif_enable(); +} + +void imx_pwr_domain_off(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + plat_gic_cpuif_disable(); + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE); + + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) { + cci_disable_snoop_dvm_reqs(cluster_id); + if (cluster_id == 1) + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF); + } + printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id); +} + +void imx_domain_suspend(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + plat_gic_cpuif_disable(); + sc_pm_set_cpu_resume(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + true, BL31_BASE); + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC); + } else { + dsb(); + write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); + isb(); + } + + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) { + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + if (cluster_id == 1) + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF); + } + + if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { + plat_gic_cpuif_disable(); + + /* save gic context */ + plat_gic_save(cpu_id, &imx_gicv3_ctx); + /* enable the irqsteer for wakeup */ + imx_enable_irqstr_wakeup(); + + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + + /* Put GIC in LP mode. */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_OFF); + /* Save GPT clock and registers, then turn off its power */ + gpt_lpcg = mmio_read_32(IMX_GPT_LPCG_BASE); + gpt_reg[0] = mmio_read_32(IMX_GPT_BASE); + gpt_reg[1] = mmio_read_32(IMX_GPT_BASE + 0x4); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_OFF); + + sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_OFF); + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF); + sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_OFF); + + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_OFF); + + sc_pm_set_cpu_resume(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + true, BL31_BASE); + if (imx_is_wakeup_src_irqsteer()) + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_IRQSTEER); + else + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_SCU); + } +} + +void imx_domain_suspend_finish(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + /* check the system level status */ + if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { + MU_Resume(SC_IPC_BASE); + + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC); + + /* Put GIC/IRQSTR back to high power mode. */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_ON); + + /* Turn GPT power and restore its clock and registers */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON); + sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0); + mmio_write_32(IMX_GPT_BASE, gpt_reg[0]); + mmio_write_32(IMX_GPT_BASE + 0x4, gpt_reg[1]); + mmio_write_32(IMX_GPT_LPCG_BASE, gpt_lpcg); + + sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON); + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON); + sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_ON); + + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_ON); + + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + + /* restore gic context */ + plat_gic_restore(cpu_id, &imx_gicv3_ctx); + /* disable the irqsteer wakeup */ + imx_disable_irqstr_wakeup(); + + plat_gic_cpuif_enable(); + } + + /* check the cluster level power status */ + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) { + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + if (cluster_id == 1) + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON); + } + + /* check the core level power status */ + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + sc_pm_set_cpu_resume(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + false, BL31_BASE); + sc_pm_req_cpu_low_power_mode(ipc_handle, + ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], + SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC); + plat_gic_cpuif_enable(); + } else { + write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); + isb(); + } +} + +int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) +{ + return PSCI_E_SUCCESS; +} + +static const plat_psci_ops_t imx_plat_psci_ops = { + .pwr_domain_on = imx_pwr_domain_on, + .pwr_domain_on_finish = imx_pwr_domain_on_finish, + .pwr_domain_off = imx_pwr_domain_off, + .pwr_domain_suspend = imx_domain_suspend, + .pwr_domain_suspend_finish = imx_domain_suspend_finish, + .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, + .validate_power_state = imx_validate_power_state, + .validate_ns_entrypoint = imx_validate_ns_entrypoint, + .system_off = imx_system_off, + .system_reset = imx_system_reset, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + imx_mailbox_init(sec_entrypoint); + *psci_ops = &imx_plat_psci_ops; + + /* make sure system sources power ON in low power mode by default */ + sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON); + sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON); + sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_ON); + + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + + return 0; +} diff --git a/plat/imx/imx8qm/include/platform_def.h b/plat/imx/imx8qm/include/platform_def.h new file mode 100644 index 0000000..671c77f --- /dev/null +++ b/plat/imx/imx8qm/include/platform_def.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <lib/utils_def.h> + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE 0X400 +#define CACHE_WRITEBACK_GRANULE 64 + +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(4) +#define PLATFORM_CLUSTER_COUNT U(2) +#define PLATFORM_CLUSTER0_CORE_COUNT U(4) +#define PLATFORM_CLUSTER1_CORE_COUNT U(2) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ + PLATFORM_CLUSTER1_CORE_COUNT) + +#define IMX_PWR_LVL0 MPIDR_AFFLVL0 +#define IMX_PWR_LVL1 MPIDR_AFFLVL1 +#define IMX_PWR_LVL2 MPIDR_AFFLVL2 + +#define PWR_DOMAIN_AT_MAX_LVL U(1) +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) + +#define BL31_BASE 0x80000000 +#define BL31_LIMIT 0x80020000 + +#define PLAT_GICD_BASE 0x51a00000 +#define PLAT_GICR_BASE 0x51b00000 +#define PLAT_CCI_BASE 0x52090000 +#define CLUSTER0_CCI_SLVAE_IFACE 3 +#define CLUSTER1_CCI_SLVAE_IFACE 4 + +/* UART */ +#if defined(IMX_USE_UART0) +#define IMX_BOOT_UART_BASE 0x5a060000 +#elif defined(IMX_USE_UART1) +#define IMX_BOOT_UART_BASE 0x5a070000 +#else +#error "Provide proper UART number in IMX_DEBUG_UART" +#endif + +#define IMX_BOOT_UART_BAUDRATE 115200 +#define IMX_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE +#define PLAT__CRASH_UART_CLK_IN_HZ 24000000 +#define IMX_CONSOLE_BAUDRATE 115200 + +#define SC_IPC_BASE 0x5d1b0000 +#define IMX_GPT_LPCG_BASE 0x5d540000 +#define IMX_GPT_BASE 0x5d140000 +#define IMX_WUP_IRQSTR_BASE 0x51090000 +#define IMX_REG_BASE 0x50000000 +#define IMX_REG_SIZE 0x10000000 + +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* non-secure uboot base */ +#define PLAT_NS_IMAGE_OFFSET 0x80020000 + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) + +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 12 + +#define DEBUG_CONSOLE_A53 DEBUG_CONSOLE + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/imx/imx8qm/include/sec_rsrc.h b/plat/imx/imx8qm/include/sec_rsrc.h new file mode 100644 index 0000000..d16d051 --- /dev/null +++ b/plat/imx/imx8qm/include/sec_rsrc.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* resources that are going to stay in secure partition */ +sc_rsrc_t secure_rsrcs[] = { + SC_R_MU_0A, + SC_R_A53, + SC_R_A53_0, + SC_R_A53_1, + SC_R_A53_2, + SC_R_A53_3, + SC_R_A72, + SC_R_A72_0, + SC_R_A72_1, + SC_R_GIC, + SC_R_GIC_SMMU, + SC_R_CCI, + SC_R_SYSTEM, + SC_R_IRQSTR_SCU2, + SC_R_GPT_0 +}; + +/* resources that have register access for non-secure domain */ +sc_rsrc_t ns_access_allowed[] = { + SC_R_GIC, + SC_R_GIC_SMMU, + SC_R_CCI, + SC_R_GPT_0 +}; diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk new file mode 100644 index 0000000..c57edbe --- /dev/null +++ b/plat/imx/imx8qm/platform.mk @@ -0,0 +1,50 @@ +# +# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Translation tables library +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -Iplat/imx/imx8qm/include \ + -Iplat/imx/common/include \ + +# Include GICv3 driver files +include drivers/arm/gic/v3/gicv3.mk + +IMX_GIC_SOURCES := ${GICV3_SOURCES} \ + plat/common/plat_gicv3.c \ + plat/common/plat_psci_common.c \ + plat/imx/common/plat_imx8_gic.c + +BL31_SOURCES += plat/imx/common/lpuart_console.S \ + plat/imx/common/imx8_helpers.S \ + plat/imx/imx8qm/imx8qm_bl31_setup.c \ + plat/imx/imx8qm/imx8qm_psci.c \ + plat/imx/common/imx8_topology.c \ + plat/imx/common/imx8_psci.c \ + plat/imx/common/imx_sip_svc.c \ + plat/imx/common/imx_sip_handler.c \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a72.S \ + drivers/arm/cci/cci.c \ + ${XLAT_TABLES_LIB_SRCS} \ + ${IMX_GIC_SOURCES} \ + +include plat/imx/common/sci/sci_api.mk + +USE_COHERENT_MEM := 1 +RESET_TO_BL31 := 1 +A53_DISABLE_NON_TEMPORAL_HINT := 0 +ERRATA_A72_859971 := 1 + +ERRATA_A53_835769 := 1 +ERRATA_A53_843419 := 1 +ERRATA_A53_855873 := 1 + +IMX_DEBUG_UART ?= 0 +$(eval $(call add_define,IMX_USE_UART${IMX_DEBUG_UART})) + +DEBUG_CONSOLE ?= 0 +$(eval $(call add_define,DEBUG_CONSOLE)) |