diff options
Diffstat (limited to 'plat/mediatek/mt8192')
76 files changed, 15644 insertions, 0 deletions
diff --git a/plat/mediatek/mt8192/aarch64/plat_helpers.S b/plat/mediatek/mt8192/aarch64/plat_helpers.S new file mode 100644 index 0000000..99274de --- /dev/null +++ b/plat/mediatek/mt8192/aarch64/plat_helpers.S @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> + + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_mediatek_calc_core_pos + +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #PLAT_PRIMARY_CPU + cset x0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_mediatek_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_mediatek_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); + * + * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and + * AFF0 is thread id. There is only one cluster in ARMv8.2 + * and one thread in current implementation. + * + * With this function: CorePos = CoreID (AFF1) + * we do it with x0 = (x0 >> 8) & 0xff + * ----------------------------------------------------- + */ +func plat_mediatek_calc_core_pos + mov x1, #MPIDR_AFFLVL_MASK + and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT + ret +endfunc plat_mediatek_calc_core_pos diff --git a/plat/mediatek/mt8192/aarch64/platform_common.c b/plat/mediatek/mt8192/aarch64/platform_common.c new file mode 100644 index 0000000..fc98871 --- /dev/null +++ b/plat/mediatek/mt8192/aarch64/platform_common.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Project Includes */ +#include <lib/xlat_tables/xlat_tables_v2.h> + +/* Platform Includes */ +#include <platform_def.h> + +/* Table of regions to map using the MMU. */ +const mmap_region_t plat_mmap[] = { + /* for TF text, RO, RW */ + MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +void plat_configure_mmu_el3(uintptr_t total_base, + uintptr_t total_size, + uintptr_t ro_start, + uintptr_t ro_limit) +{ + mmap_add_region(total_base, total_base, total_size, + MT_RW_DATA | MT_SECURE); + mmap_add_region(ro_start, ro_start, ro_limit - ro_start, + MT_CODE | MT_SECURE); + mmap_add(plat_mmap); + init_xlat_tables(); + enable_mmu_el3(0); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c new file mode 100644 index 0000000..c3cb9a5 --- /dev/null +++ b/plat/mediatek/mt8192/bl31_plat_setup.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* System Includes */ +#include <assert.h> + +/* Project Includes */ +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/desc_image_load.h> +#include <drivers/generic_delay_timer.h> +#include <drivers/ti/uart/uart_16550.h> +#include <lib/coreboot.h> + +/* Platform Includes */ +#include <devapc/devapc.h> +#include <emi_mpu/emi_mpu.h> +#include <gpio/mtgpio.h> +#include <mt_gic_v3.h> +#include <mt_spm.h> +#include <mt_timer.h> +#include <mtk_dcm.h> +#include <plat_params.h> +#include <plat_private.h> + +static entry_point_info_t bl32_ep_info; +static entry_point_info_t bl33_ep_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; + assert(next_image_info->h.type == PARAM_EP); + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) { + return next_image_info; + } else { + return NULL; + } +} + +/******************************************************************************* + * Perform any BL31 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + * BL2 has flushed this information to memory, so we are guaranteed to pick up + * good data. + ******************************************************************************/ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + static console_t console; + + params_early_setup(arg1); + +#if COREBOOT + if (coreboot_serial.type) { + console_16550_register(coreboot_serial.baseaddr, + coreboot_serial.input_hertz, + coreboot_serial.baud, + &console); + } +#else + console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); +#endif + + NOTICE("MT8192 bl31_setup\n"); + + bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); +} + + +/******************************************************************************* + * Perform any BL31 platform setup code + ******************************************************************************/ +void bl31_platform_setup(void) +{ + /* Set dcm on */ + if (!dcm_set_default()) { + ERROR("Failed to set default dcm on!!\n"); + } + + /* MPU Init */ + emi_mpu_init(); + + /* DAPC Init */ + devapc_init(); + + /* Initialize the GIC driver, CPU and distributor interfaces */ + mt_gic_driver_init(); + mt_gic_init(); + + mt_gpio_init(); + mt_systimer_init(); + generic_delay_timer_init(); + spm_boot_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + plat_configure_mmu_el3(BL31_START, + BL31_END - BL31_START, + BL_CODE_BASE, + BL_CODE_END); +} diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c new file mode 100644 index 0000000..782aa5f --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <drivers/console.h> +#include <lib/mmio.h> +#include <mtk_apusys.h> +#include <plat/common/platform.h> + +uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + uint32_t *ret1) +{ + uint32_t request_ops; + + request_ops = (uint32_t)x1; + INFO("[APUSYS] ops=0x%x\n", request_ops); + + switch (request_ops) { + case MTK_SIP_APU_START_MCU: + /* setup addr[33:32] in reviser */ + mmio_write_32(REVISER_SECUREFW_CTXT, 0U); + mmio_write_32(REVISER_USDRFW_CTXT, 0U); + + /* setup secure sideband */ + mmio_write_32(AO_SEC_FW, + (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) | + (0U << SEC_FW_DOMAIN_SHIFT)); + + /* setup boot address */ + mmio_write_32(AO_MD32_BOOT_CTRL, 0U); + + /* setup pre-define region */ + mmio_write_32(AO_MD32_PRE_DEFINE, + (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) | + (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) | + (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) | + (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G)); + + /* release runstall */ + mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN); + + INFO("[APUSYS] reviser_ctxt=%x,%x\n", + mmio_read_32(REVISER_SECUREFW_CTXT), + mmio_read_32(REVISER_USDRFW_CTXT)); + INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n", + mmio_read_32(AO_SEC_FW), + mmio_read_32(AO_MD32_BOOT_CTRL), + mmio_read_32(AO_MD32_PRE_DEFINE), + mmio_read_32(AO_MD32_SYS_CTRL)); + break; + case MTK_SIP_APU_STOP_MCU: + /* hold runstall */ + mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL); + + INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n", + mmio_read_32(AO_MD32_BOOT_CTRL), + mmio_read_32(AO_MD32_SYS_CTRL)); + break; + default: + ERROR("%s, unknown request_ops = %x\n", __func__, request_ops); + break; + } + + return 0UL; +} diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h new file mode 100644 index 0000000..95fac4a --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_APUSYS_H__ +#define __MTK_APUSYS_H__ + +#include <stdint.h> + +/* setup the SMC command ops */ +#define MTK_SIP_APU_START_MCU 0x00U +#define MTK_SIP_APU_STOP_MCU 0x01U + +/* AO Register */ +#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00) +#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04) +#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08) +#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10) + +#define PRE_DEFINE_CACHE_TCM 0x3U +#define PRE_DEFINE_CACHE 0x2U +#define PRE_DEFINE_SHIFT_0G 0U +#define PRE_DEFINE_SHIFT_1G 2U +#define PRE_DEFINE_SHIFT_2G 4U +#define PRE_DEFINE_SHIFT_3G 6U + +#define SEC_FW_NON_SECURE 1U +#define SEC_FW_SHIFT_NS 4U +#define SEC_FW_DOMAIN_SHIFT 0U + +#define SYS_CTRL_RUN 0U +#define SYS_CTRL_STALL 1U + +/* Reviser Register */ +#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x300) +#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x304) + +uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + uint32_t *ret1); +#endif /* __MTK_APUSYS_H__ */ diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c new file mode 100644 index 0000000..245d512 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c @@ -0,0 +1,571 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <mtk_apusys_apc.h> +#include <mtk_apusys_apc_def.h> +#include <mtk_plat_common.h> +#include <platform_def.h> + +static const struct APC_DOM_16 APUSYS_NOC_DAPC_AO[] = { +/* 0~3 */ +APUSYS_APC_AO_ATTR("slv07-0", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv07-1", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv07-2", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv07-3", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), + +/* 16~18 */ +APUSYS_APC_AO_ATTR("slv01-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv01-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv01-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 19~21 */ +APUSYS_APC_AO_ATTR("slv00-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv00-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("slv00-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 22~26 */ +APUSYS_APC_AO_ATTR("slv02-0", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-1", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-2", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-3", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +APUSYS_APC_AO_ATTR("slv02-4", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION), +}; + +static int32_t set_slave_noc_dapc(uint32_t slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + uintptr_t base; + uint32_t clr_bit; + uint32_t set_bit; + int32_t ret; + + if (perm >= PERM_NUM) { + ERROR("[NOC_DAPC] perm type:0x%x is not supported!\n", perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = perm << (apc_set_index * 2); + + if ((slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM) && + (domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM)) { + base = APUSYS_NOC_DAPC_AO_BASE + + (domain_id * 0x40) + (apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + ERROR("[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_noc_dapc(void) +{ + uint32_t reg_num; + uint32_t d, i; + + reg_num = APUSYS_NOC_DAPC_AO_SLAVE_NUM / + APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) { + INFO("[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_NOC_DAPC_AO_BASE + + (d * 0x40) + (i * 4))); + } + } + + INFO("[NOCDAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_NOC_DAPC_CON)); +} + +static const struct APC_DOM_16 APUSYS_AO_Devices[] = { + +/* 0 */ +APUSYS_APC_AO_ATTR("apusys_ao-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-2", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-4", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apusys_ao-5", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_apb_s-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_apb_s-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_apb_s-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("md32_debug_apb", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +APUSYS_APC_AO_ATTR("apu_conn_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_sctrl_reviser", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_sema_stimer", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_emi_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_adl", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma_lite0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma_lite1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_edma0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_dapc_ao", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +APUSYS_APC_AO_ATTR("apu_dapc", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("infra_bcrm", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apb_dbg_ctl", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("noc_dapc", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_noc_bcrm", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_noc_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core0_config-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core0_config-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core1_config-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vpu_core1_config-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 30 */ +APUSYS_APC_AO_ATTR("mdla0_apb-0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("mdla0_apb-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("mdla0_apb-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("mdla0_apb-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r0", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r1", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r2", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r3", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_iommu0_r4", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("apu_rsi2_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 40 */ +APUSYS_APC_AO_ATTR("apu_ssc2_config", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vp6_core0_debug_apb", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +APUSYS_APC_AO_ATTR("vp6_core1_debug_apb", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +}; + +static int32_t set_slave_apc(uint32_t slave, + enum APUSYS_APC_DOMAIN_ID domain_id, + enum APUSYS_APC_PERM_TYPE perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + uintptr_t base; + uint32_t clr_bit; + uint32_t set_bit; + int32_t ret; + + if (perm >= PERM_NUM) { + ERROR("[APUAPC] perm type:0x%x is not supported!\n", perm); + ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + goto exit; + } + + apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + + clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2)); + set_bit = perm << (apc_set_index * 2); + + if ((slave < APUSYS_APC_SYS0_AO_SLAVE_NUM) && + (domain_id < APUSYS_APC_SYS0_AO_DOM_NUM)) { + base = APUSYS_APC_AO_BASE + + (domain_id * 0x40) + (apc_register_index * 4); + apuapc_writel(apuapc_readl(base) & clr_bit, base); + apuapc_writel(apuapc_readl(base) | set_bit, base); + ret = APUSYS_APC_OK; + } else { + ERROR("[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave", slave, + "domain_id", domain_id); + ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + +exit: + return ret; +} + +static void dump_apusys_ao_apc(void) +{ + uint32_t reg_num; + uint32_t d, i; + + reg_num = APUSYS_APC_SYS0_AO_SLAVE_NUM / + APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { + for (i = 0U; i <= reg_num; i++) { + INFO("[APUAPC] D%d_APC_%d: 0x%x\n", d, i, + apuapc_readl(APUSYS_APC_AO_BASE + + (d * 0x40) + (i * 4))); + } + } + INFO("[APUAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_APC_CON)); +} + +static int32_t set_apusys_noc_dapc(void) +{ + int32_t ret = 0; + uint32_t i; + uint32_t index; + + for (i = 0U; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) { + if (i < APUSYS_NOC_DAPC_GAP_BOUNDARY) { + index = i; + } else { + index = i + APUSYS_NOC_DAPC_JUMP_GAP; + } + ret += set_slave_noc_dapc(index, DOMAIN_0, + APUSYS_NOC_DAPC_AO[i].d0_permission); + ret += set_slave_noc_dapc(index, DOMAIN_1, + APUSYS_NOC_DAPC_AO[i].d1_permission); + ret += set_slave_noc_dapc(index, DOMAIN_2, + APUSYS_NOC_DAPC_AO[i].d2_permission); + ret += set_slave_noc_dapc(index, DOMAIN_3, + APUSYS_NOC_DAPC_AO[i].d3_permission); + ret += set_slave_noc_dapc(index, DOMAIN_4, + APUSYS_NOC_DAPC_AO[i].d4_permission); + ret += set_slave_noc_dapc(index, DOMAIN_5, + APUSYS_NOC_DAPC_AO[i].d5_permission); + ret += set_slave_noc_dapc(index, DOMAIN_6, + APUSYS_NOC_DAPC_AO[i].d6_permission); + ret += set_slave_noc_dapc(index, DOMAIN_7, + APUSYS_NOC_DAPC_AO[i].d7_permission); + ret += set_slave_noc_dapc(index, DOMAIN_8, + APUSYS_NOC_DAPC_AO[i].d8_permission); + ret += set_slave_noc_dapc(index, DOMAIN_9, + APUSYS_NOC_DAPC_AO[i].d9_permission); + ret += set_slave_noc_dapc(index, DOMAIN_10, + APUSYS_NOC_DAPC_AO[i].d10_permission); + ret += set_slave_noc_dapc(index, DOMAIN_11, + APUSYS_NOC_DAPC_AO[i].d11_permission); + ret += set_slave_noc_dapc(index, DOMAIN_12, + APUSYS_NOC_DAPC_AO[i].d12_permission); + ret += set_slave_noc_dapc(index, DOMAIN_13, + APUSYS_NOC_DAPC_AO[i].d13_permission); + ret += set_slave_noc_dapc(index, DOMAIN_14, + APUSYS_NOC_DAPC_AO[i].d14_permission); + ret += set_slave_noc_dapc(index, DOMAIN_15, + APUSYS_NOC_DAPC_AO[i].d15_permission); + } + + return ret; +} + +static int32_t set_apusys_ao_apc(void) +{ + int32_t ret = 0; + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(APUSYS_AO_Devices); i++) { + ret += set_slave_apc(i, DOMAIN_0, + APUSYS_AO_Devices[i].d0_permission); + ret += set_slave_apc(i, DOMAIN_1, + APUSYS_AO_Devices[i].d1_permission); + ret += set_slave_apc(i, DOMAIN_2, + APUSYS_AO_Devices[i].d2_permission); + ret += set_slave_apc(i, DOMAIN_3, + APUSYS_AO_Devices[i].d3_permission); + ret += set_slave_apc(i, DOMAIN_4, + APUSYS_AO_Devices[i].d4_permission); + ret += set_slave_apc(i, DOMAIN_5, + APUSYS_AO_Devices[i].d5_permission); + ret += set_slave_apc(i, DOMAIN_6, + APUSYS_AO_Devices[i].d6_permission); + ret += set_slave_apc(i, DOMAIN_7, + APUSYS_AO_Devices[i].d7_permission); + ret += set_slave_apc(i, DOMAIN_8, + APUSYS_AO_Devices[i].d8_permission); + ret += set_slave_apc(i, DOMAIN_9, + APUSYS_AO_Devices[i].d9_permission); + ret += set_slave_apc(i, DOMAIN_10, + APUSYS_AO_Devices[i].d10_permission); + ret += set_slave_apc(i, DOMAIN_11, + APUSYS_AO_Devices[i].d11_permission); + ret += set_slave_apc(i, DOMAIN_12, + APUSYS_AO_Devices[i].d12_permission); + ret += set_slave_apc(i, DOMAIN_13, + APUSYS_AO_Devices[i].d13_permission); + ret += set_slave_apc(i, DOMAIN_14, + APUSYS_AO_Devices[i].d14_permission); + ret += set_slave_apc(i, DOMAIN_15, + APUSYS_AO_Devices[i].d15_permission); + } + + return ret; +} + +static void set_apusys_apc_lock(void) +{ + uint32_t set_bit = 1U << APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER; + + /* Lock apu_sctrl_reviser */ + set_bit = set_bit | (1U << APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5); + apuapc_writel(set_bit, APUSYS_SYS0_APC_LOCK_0); +} + +void set_apusys_apc(void) +{ + int32_t ret = 0; + + /* Check violation status */ + INFO("[APUAPC] vio %d\n", apuapc_readl(APUSYS_APC_CON) & 0x80000000); + + /* Initial Permission */ + ret = set_apusys_ao_apc(); + INFO("[APUAPC] %s - %s!\n", "set_apusys_ao_apc", + ret ? "FAILED" : "SUCCESS"); + + /* Lock */ + set_apusys_apc_lock(); + + /* Initial NoC Permission */ + ret = set_apusys_noc_dapc(); + INFO("[APUAPC] %s - %s!\n", "set_apusys_noc_dapc", + ret ? "FAILED" : "SUCCESS"); + + /* Dump Permission */ + dump_apusys_ao_apc(); + dump_apusys_noc_dapc(); + + INFO("[APUAPC] %s done\n", __func__); +} diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h new file mode 100644 index 0000000..ff7a9fa --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_APUSYS_APC_H__ +#define __MTK_APUSYS_APC_H__ + +void set_apusys_apc(void); + +#endif /* __MTK_APUSYS_APC_H__ */ diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h new file mode 100644 index 0000000..b392d6a --- /dev/null +++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MTK_APUSYS_APC_DEF_H__ +#define __MTK_APUSYS_APC_DEF_H__ + +#include <lib/mmio.h> + +enum APUSYS_APC_ERR_STATUS { + APUSYS_APC_OK = 0x0, + + APUSYS_APC_ERR_GENERIC = 0x1000, + APUSYS_APC_ERR_INVALID_CMD = 0x1001, + APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002, + APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003, + APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004, + APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005, + APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006, + APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007, +}; + +enum APUSYS_APC_PERM_TYPE { + NO_PROTECTION = 0U, + SEC_RW_ONLY = 1U, + SEC_RW_NS_R = 2U, + FORBIDDEN = 3U, + PERM_NUM = 4U, +}; + +enum APUSYS_APC_DOMAIN_ID { + DOMAIN_0 = 0U, + DOMAIN_1 = 1U, + DOMAIN_2 = 2U, + DOMAIN_3 = 3U, + DOMAIN_4 = 4U, + DOMAIN_5 = 5U, + DOMAIN_6 = 6U, + DOMAIN_7 = 7U, + DOMAIN_8 = 8U, + DOMAIN_9 = 9U, + DOMAIN_10 = 10U, + DOMAIN_11 = 11U, + DOMAIN_12 = 12U, + DOMAIN_13 = 13U, + DOMAIN_14 = 14U, + DOMAIN_15 = 15U, +}; + +struct APC_DOM_16 { + unsigned char d0_permission; + unsigned char d1_permission; + unsigned char d2_permission; + unsigned char d3_permission; + unsigned char d4_permission; + unsigned char d5_permission; + unsigned char d6_permission; + unsigned char d7_permission; + unsigned char d8_permission; + unsigned char d9_permission; + unsigned char d10_permission; + unsigned char d11_permission; + unsigned char d12_permission; + unsigned char d13_permission; + unsigned char d14_permission; + unsigned char d15_permission; +}; + +#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \ + (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \ + (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \ + (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \ + (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \ + (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \ + (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15} + +#define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) +#define apuapc_readl(REG) mmio_read_32((uintptr_t)REG) + +/* APUSYS APC AO Registers */ +#define APUSYS_APC_AO_BASE APUSYS_APC_AO_WRAPPER_BASE +#define APUSYS_APC_CON (APUSYS_APC_AO_BASE + 0x00F00) +#define APUSYS_SYS0_APC_LOCK_0 (APUSYS_APC_AO_BASE + 0x00700) + +/* APUSYS NOC_DPAC_AO Registers */ +#define APUSYS_NOC_DAPC_CON (APUSYS_NOC_DAPC_AO_BASE + 0x00F00) + +#define APUSYS_NOC_DAPC_GAP_BOUNDARY 4U +#define APUSYS_NOC_DAPC_JUMP_GAP 12U + +#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_APC_SYS0_AO_DOM_NUM 16U +#define APUSYS_APC_SYS0_AO_SLAVE_NUM 59U + +#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER 11U +#define APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5 5U + +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 27U + +#endif /* __MTK_APUSYS_APC_DEF_H__ */ diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c new file mode 100644 index 0000000..dd8bf4e --- /dev/null +++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <mtk_dcm.h> +#include <mtk_dcm_utils.h> + +static void dcm_armcore(bool mode) +{ + dcm_mp_cpusys_top_bus_pll_div_dcm(mode); + dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); + dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); +} + +static void dcm_mcusys(bool on) +{ + dcm_mp_cpusys_top_adb_dcm(on); + dcm_mp_cpusys_top_apb_dcm(on); + dcm_mp_cpusys_top_cpubiu_dcm(on); + dcm_mp_cpusys_top_misc_dcm(on); + dcm_mp_cpusys_top_mp0_qdcm(on); + dcm_cpccfg_reg_emi_wfifo(on); + dcm_mp_cpusys_top_last_cor_idle_dcm(on); +} + +static void dcm_stall(bool on) +{ + dcm_mp_cpusys_top_core_stall_dcm(on); + dcm_mp_cpusys_top_fcm_stall_dcm(on); +} + +static bool check_dcm_state(void) +{ + bool ret = true; + + ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); + ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); + ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); + + ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); + ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); + ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); + ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); + ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); + ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); + ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); + + ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); + ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); + + return ret; +} + +bool dcm_set_default(void) +{ + dcm_armcore(true); + dcm_mcusys(true); + dcm_stall(true); + + return check_dcm_state(); +} diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h new file mode 100644 index 0000000..ee98d0e --- /dev/null +++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_DCM_H +#define MTK_DCM_H + +#include <stdbool.h> + +bool dcm_set_default(void); + +#endif /* #ifndef MTK_DCM_H */ diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c new file mode 100644 index 0000000..15a700c --- /dev/null +++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c @@ -0,0 +1,562 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <mtk_dcm_utils.h> + +#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17)) +#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \ + BIT(16) | \ + BIT(17) | \ + BIT(18) | \ + BIT(21)) +#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \ + BIT(16) | \ + BIT(17) | \ + BIT(18)) +#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17)) +#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \ + BIT(16) | \ + BIT(17) | \ + BIT(18) | \ + BIT(21)) +#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \ + BIT(16) | \ + BIT(17) | \ + BIT(18)) +#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17)) +#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \ + (0x0 << 16) | \ + (0x0 << 17) | \ + (0x0 << 18) | \ + (0x0 << 21)) +#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \ + (0x0 << 16) | \ + (0x0 << 17) | \ + (0x0 << 18)) + +bool dcm_mp_cpusys_top_adb_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) & + MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON); + ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) & + MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) == + (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON); + ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & + MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) == + (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON); + + return ret; +} + +void dcm_mp_cpusys_top_adb_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */ + mmio_clrsetbits_32(MP_ADB_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG0_ON); + mmio_clrsetbits_32(MP_ADB_DCM_CFG4, + MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG1_ON); + mmio_clrsetbits_32(MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG2_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */ + mmio_clrsetbits_32(MP_ADB_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG0_OFF); + mmio_clrsetbits_32(MP_ADB_DCM_CFG4, + MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG1_OFF); + mmio_clrsetbits_32(MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG2_OFF); + } +} + +#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5)) +#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8)) +#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16)) +#define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5)) +#define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8)) +#define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16)) +#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5)) +#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8)) +#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16)) + +bool dcm_mp_cpusys_top_apb_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) & + MP_CPUSYS_TOP_APB_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON); + ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & + MP_CPUSYS_TOP_APB_DCM_REG1_MASK) == + (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON); + ret &= ((mmio_read_32(MP0_DCM_CFG0) & + MP_CPUSYS_TOP_APB_DCM_REG2_MASK) == + (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON); + + return ret; +} + +void dcm_mp_cpusys_top_apb_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */ + mmio_clrsetbits_32(MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG0_MASK, + MP_CPUSYS_TOP_APB_DCM_REG0_ON); + mmio_clrsetbits_32(MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG1_MASK, + MP_CPUSYS_TOP_APB_DCM_REG1_ON); + mmio_clrsetbits_32(MP0_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG2_MASK, + MP_CPUSYS_TOP_APB_DCM_REG2_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */ + mmio_clrsetbits_32(MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG0_MASK, + MP_CPUSYS_TOP_APB_DCM_REG0_OFF); + mmio_clrsetbits_32(MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG1_MASK, + MP_CPUSYS_TOP_APB_DCM_REG1_OFF); + mmio_clrsetbits_32(MP0_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG2_MASK, + MP_CPUSYS_TOP_APB_DCM_REG2_OFF); + } +} + +#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11)) +#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11)) +#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11)) + +bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(BUS_PLLDIV_CFG) & + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ + mmio_clrsetbits_32(BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ + mmio_clrsetbits_32(BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0)) +#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0)) +#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0)) + +bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(MP0_DCM_CFG7) & + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_core_stall_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */ + mmio_clrsetbits_32(MP0_DCM_CFG7, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */ + mmio_clrsetbits_32(MP0_DCM_CFG7, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0)) +#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0)) +#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0)) + +bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(MCSI_DCM0) & + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_cpubiu_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */ + mmio_clrsetbits_32(MCSI_DCM0, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */ + mmio_clrsetbits_32(MCSI_DCM0, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 11)) + +bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(CPU_PLLDIV_CFG0) & + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG0, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG0, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 11)) + +bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(CPU_PLLDIV_CFG1) & + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG1, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG1, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF ((0x0 << 11)) + +bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(CPU_PLLDIV_CFG2) & + MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG2, + MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG2, + MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF ((0x0 << 11)) + +bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(CPU_PLLDIV_CFG3) & + MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG3, + MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG3, + MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON (BIT(11)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF ((0x0 << 11)) + +bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(CPU_PLLDIV_CFG4) & + MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG4, + MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */ + mmio_clrsetbits_32(CPU_PLLDIV_CFG4, + MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4)) +#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4)) +#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4)) + +bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(MP0_DCM_CFG7) & + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_fcm_stall_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */ + mmio_clrsetbits_32(MP0_DCM_CFG7, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */ + mmio_clrsetbits_32(MP0_DCM_CFG7, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31)) +#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31)) +#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31)) + +bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(BUS_PLLDIV_CFG) & + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ + mmio_clrsetbits_32(BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ + mmio_clrsetbits_32(BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \ + BIT(4)) +#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \ + BIT(4)) +#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \ + (0x0 << 4)) + +bool dcm_mp_cpusys_top_misc_dcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) & + MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON); + + return ret; +} + +void dcm_mp_cpusys_top_misc_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */ + mmio_clrsetbits_32(MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, + MP_CPUSYS_TOP_MISC_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */ + mmio_clrsetbits_32(MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, + MP_CPUSYS_TOP_MISC_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \ + BIT(1) | \ + BIT(2) | \ + BIT(3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \ + BIT(1) | \ + BIT(2) | \ + BIT(3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \ + (0x0 << 1) | \ + (0x0 << 2) | \ + (0x0 << 3)) + +bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) & + MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) == + (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); + ret &= ((mmio_read_32(MP0_DCM_CFG0) & + MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) == + (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); + + return ret; +} + +void dcm_mp_cpusys_top_mp0_qdcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */ + mmio_clrsetbits_32(MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); + mmio_clrsetbits_32(MP0_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */ + mmio_clrsetbits_32(MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF); + mmio_clrsetbits_32(MP0_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF); + } +} + +#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \ + BIT(1) | \ + BIT(2) | \ + BIT(3)) +#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \ + BIT(1) | \ + BIT(2) | \ + BIT(3)) +#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \ + (0x0 << 1) | \ + (0x0 << 2) | \ + (0x0 << 3)) + +bool dcm_cpccfg_reg_emi_wfifo_is_on(void) +{ + bool ret = true; + + ret &= ((mmio_read_32(EMI_WFIFO) & + CPCCFG_REG_EMI_WFIFO_REG0_MASK) == + (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON); + + return ret; +} + +void dcm_cpccfg_reg_emi_wfifo(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */ + mmio_clrsetbits_32(EMI_WFIFO, + CPCCFG_REG_EMI_WFIFO_REG0_MASK, + CPCCFG_REG_EMI_WFIFO_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */ + mmio_clrsetbits_32(EMI_WFIFO, + CPCCFG_REG_EMI_WFIFO_REG0_MASK, + CPCCFG_REG_EMI_WFIFO_REG0_OFF); + } +} + diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h new file mode 100644 index 0000000..1cf7834 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_DCM_UTILS_H +#define MTK_DCM_UTILS_H + +#include <stdbool.h> + +#include <mtk_dcm.h> +#include <platform_def.h> + +/* Base */ +#define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000) +#define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800) + +/* Register Definition */ +#define CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) +#define CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) +#define CPU_PLLDIV_CFG2 (MP_CPUSYS_TOP_BASE + 0x22a8) +#define CPU_PLLDIV_CFG3 (MP_CPUSYS_TOP_BASE + 0x22ac) +#define CPU_PLLDIV_CFG4 (MP_CPUSYS_TOP_BASE + 0x22b0) +#define BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0) +#define MCSI_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440) +#define MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500) +#define MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510) +#define MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) +#define MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) +#define EMI_WFIFO (CPCCFG_REG_BASE + 0x100) +#define MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) +#define MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c) + +/* MP_CPUSYS_TOP */ +bool dcm_mp_cpusys_top_adb_dcm_is_on(void); +void dcm_mp_cpusys_top_adb_dcm(bool on); +bool dcm_mp_cpusys_top_apb_dcm_is_on(void); +void dcm_mp_cpusys_top_apb_dcm(bool on); +bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void); +void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on); +bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void); +void dcm_mp_cpusys_top_core_stall_dcm(bool on); +bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void); +void dcm_mp_cpusys_top_cpubiu_dcm(bool on); +bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void); +void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on); +bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void); +void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on); +bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void); +void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on); +bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void); +void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on); +bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void); +void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on); +bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void); +void dcm_mp_cpusys_top_fcm_stall_dcm(bool on); +bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void); +void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on); +bool dcm_mp_cpusys_top_misc_dcm_is_on(void); +void dcm_mp_cpusys_top_misc_dcm(bool on); +bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void); +void dcm_mp_cpusys_top_mp0_qdcm(bool on); +/* CPCCFG_REG */ +bool dcm_cpccfg_reg_emi_wfifo_is_on(void); +void dcm_cpccfg_reg_emi_wfifo(bool on); + +#endif diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.c b/plat/mediatek/mt8192/drivers/devapc/devapc.c new file mode 100644 index 0000000..b11f272 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/devapc/devapc.c @@ -0,0 +1,2847 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <drivers/console.h> +#include <lib/mmio.h> + +#include <devapc.h> +#include <mtk_apusys_apc.h> + +/* Infra_ao */ +static const struct APC_INFRA_PERI_DOM_16 INFRA_AO_SYS0_Devices[] = { + +/* 0 */ +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-4", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-5", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-6", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-7", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-8", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("APU_S_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +DAPC_INFRA_AO_SYS0_ATTR("L3C_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS0_ATTR("PCIE_AXI_S", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS1_Devices[] = { + +/* 0 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-20", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-21", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-22", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-23", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-28", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-29", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 30 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-30", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-31", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-32", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-33", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-34", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-35", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-36", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-37", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-38", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-39", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 40 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-100", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-101", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-102", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-103", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-104", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-105", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-106", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-107", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-108", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-109", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 50 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-110", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-111", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-112", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-113", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-114", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-115", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-116", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-117", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-118", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-119", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 60 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-120", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-121", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-122", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-123", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-124", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-125", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-126", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-127", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-128", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-129", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 70 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-130", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-131", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-132", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-133", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-134", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-135", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-136", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-137", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-138", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-139", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 80 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-140", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-141", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-142", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-143", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-200", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-201", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-202", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-203", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-204", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-205", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 90 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-206", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-207", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-300", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-301", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-302", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-303", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-304", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-305", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-306", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-307", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 100 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-400", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-401", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-402", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-403", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-404", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-405", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-406", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-407", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-408", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-409", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 110 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-410", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-411", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-412", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-413", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-414", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-415", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-416", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-417", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-418", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-419", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 120 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-420", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-421", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-422", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-423", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-424", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-425", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-426", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-427", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-428", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-429", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 130 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-430", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-431", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-432", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-433", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-434", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-435", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-436", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-437", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-438", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-439", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 140 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-440", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-441", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-442", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-443", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-444", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-445", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-446", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-447", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-448", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-449", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 150 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-450", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-451", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-452", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-453", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-454", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-455", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-456", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-457", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-458", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-459", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 160 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-460", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-461", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-462", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-463", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-464", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-465", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-466", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-467", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-468", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-469", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 170 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-470", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-471", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-472", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-473", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-474", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-475", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-476", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-477", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-478", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-479", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 180 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-480", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-481", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-482", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-483", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-484", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-485", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-486", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-487", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-488", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-489", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 190 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-490", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-491", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-492", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-493", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-494", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-495", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-496", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-497", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-498", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-499", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 200 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-500", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-501", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-502", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-503", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-504", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-505", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-506", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-507", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-508", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-509", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 210 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-510", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-511", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-512", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-513", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-514", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-515", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-516", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-517", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-518", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-519", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 220 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-520", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-521", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-522", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-523", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-524", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-525", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-526", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-527", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-528", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-529", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 230 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-530", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-531", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-532", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-533", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-534", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-535", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-536", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-537", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-538", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-539", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 240 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-540", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-541", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-542", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-543", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-544", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-545", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-546", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-547", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-548", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-549", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 250 */ +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-550", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-551", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-552", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-553", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-554", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-555", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS2_Devices[] = { + +/* 0 */ +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-556", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-557", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-558", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-559", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-560", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-561", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-562", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-563", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-564", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-565", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-566", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-567", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-568", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-569", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-570", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-571", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-572", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-573", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-574", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-575", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-576", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-577", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-578", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-579", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-580", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-581", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-582", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-583", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-584", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-585", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 30 */ +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-586", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-587", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-588", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-589", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-590", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-591", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-592", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-593", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-594", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-595", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 40 */ +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-600", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-601", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-602", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-603", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-604", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-605", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-606", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-607", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-608", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-609", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 50 */ +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-610", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-611", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-700", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-701", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-702", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-703", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-704", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-705", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-706", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-707", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 60 */ +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-708", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-709", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-710", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-711", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-712", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-713", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-714", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-715", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-716", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-717", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +/* Peri_ao */ +static const struct APC_INFRA_PERI_DOM_16 PERI_AO_SYS0_Devices[] = { + +/* 0 */ +DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-4", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, NO_PROTECTION, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, NO_PROTECTION, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +DAPC_PERI_AO_SYS0_ATTR("PERICFG_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("GPIO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("TOPRGU_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("RESERVED_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +DAPC_PERI_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PMIC_WRAP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MM_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("KP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("TOP_MISC_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DVFSRC_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("MBIST_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DPMAIF_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_AO_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SYS_TIMER_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 30 */ +DAPC_PERI_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MD_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PMIF1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PMICSPI_MST_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("TIA_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 40 */ +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("AUDIO_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("AUDIO_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 50 */ +DAPC_PERI_AO_SYS0_ATTR("SSUSB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("UFS_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("UFS_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("UFS_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("UFS_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 60 */ +DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("PCIE_AHB_S", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 70 */ +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 80 */ +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 90 */ +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("CCIF3_AP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("CCIF3_MD_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("CCIF4_AP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("CCIF4_MD_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("INFRA_BUS_TRACE_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("CCIF5_AP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 100 */ +DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +static const struct APC_INFRA_PERI_DOM_8 PERI_AO_SYS1_Devices[] = { + +/* 0 */ +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-4", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-4", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-5", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-6", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 30 */ +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-7", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-8", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-9", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-10", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-11", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-12", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-13", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-14", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-15", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-16", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 40 */ +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-17", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-18", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-19", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-20", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-21", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-22", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-23", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-24", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-25", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-26", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 50 */ +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-27", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-28", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-29", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-30", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-31", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-32", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-33", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-34", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-35", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-36", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 60 */ +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-37", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-38", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-39", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-40", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-41", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-42", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +static const struct APC_INFRA_PERI_DOM_4 PERI_AO_SYS2_Devices[] = { + +/* 0 */ +DAPC_PERI_AO_SYS2_ATTR("CONN_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +/* Peri_ao2 */ +static const struct APC_INFRA_PERI_DOM_16 PERI_AO2_SYS0_Devices[] = { + +/* 0 */ +DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("APXGPT_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("SEJ_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("AES_TOP0_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("SECURITY_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_AO2_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_AO2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_PERI_AO2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("SPMI_MST_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("PWM_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-1", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-2", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-3", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB0_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB1_S", + NO_PROTECTION, FORBIDDEN, SEC_RW_NS_R, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB3_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB4_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB5_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB6_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB7_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB8_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 30 */ +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB9_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB10_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB11_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB12_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB13_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB14_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB15_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB0_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB1_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 40 */ +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB3_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB4_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB5_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB6_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB7_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB0_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB1_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB3_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB4_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 50 */ +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB5_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB6_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB7_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB8_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB9_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB10_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB11_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB12_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB13_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB14_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 60 */ +DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB15_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB0_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB1_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB3_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB4_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB5_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB6_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB7_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB8_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 70 */ +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB9_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB10_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB11_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB12_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB13_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB14_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB15_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB0_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB1_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 80 */ +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB3_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB4_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB5_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB6_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB7_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_INFRA_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("CCIF0_AP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 90 */ +DAPC_PERI_AO2_SYS0_ATTR("CCIF0_MD_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("CCIF1_AP_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("CCIF1_MD_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("MBIST_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("TRNG_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DX_CC_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("CQ_DMA_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("SRAMROM_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_MEM_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 100 */ +DAPC_PERI_AO2_SYS0_ATTR("RESERVED_DVFS_PROC_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB1_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("EMI_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("EMI_MPU_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEVICE_MPU_PDN_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("APDMA_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BCRM_INFRA_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 110 */ +DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +/* Peri_par_ao */ +static const struct APC_INFRA_PERI_DOM_16 PERI_PAR_AO_SYS0_Devices[] = { + +/* 0 */ +DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB4_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("BTIF_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI1_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 10 */ +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI2_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI3_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB0_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB1_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI4_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI5_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB2_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB3_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI6_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("SPI7_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +/* 20 */ +DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_AO_APB_S", + SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("DEBUG_CTRL_PERI_PAR_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), +DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_AO_APB_S", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN), + +}; + +static void set_module_apc(enum DEVAPC_SLAVE_TYPE slave_type, + uint32_t module, enum DOMAIN_ID domain_id, + enum DEVAPC_PERM_TYPE perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + uintptr_t base = 0, reg; + uint32_t clr_bit; + uint32_t set_bit; + + apc_register_index = module / MOD_NO_IN_1_DEVAPC; + apc_set_index = module % MOD_NO_IN_1_DEVAPC; + + clr_bit = (0x3U << (apc_set_index * 2)); + set_bit = (uint32_t)perm << (apc_set_index * 2); + + /* infra_ao */ + if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS0) && + (module < SLAVE_NUM_INFRA_AO_SYS0) && + (domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS0)) { + base = DEVAPC_INFRA_AO_SYS0_D0_APC_0; + + } else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS1) && + (module < SLAVE_NUM_INFRA_AO_SYS1) && + (domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS1)) { + base = DEVAPC_INFRA_AO_SYS1_D0_APC_0; + + } else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS2) && + (module < SLAVE_NUM_INFRA_AO_SYS2) && + (domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS2)) { + base = DEVAPC_INFRA_AO_SYS2_D0_APC_0; + /* peri_ao */ + } else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS0) && + (module < SLAVE_NUM_PERI_AO_SYS0) && + (domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS0)) { + base = DEVAPC_PERI_AO_SYS0_D0_APC_0; + + } else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS1) && + (module < SLAVE_NUM_PERI_AO_SYS1) && + (domain_id <= (uint32_t)DOM_NUM_PERI_AO_SYS1)) { + base = DEVAPC_PERI_AO_SYS1_D0_APC_0; + + } else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS2) && + (module < SLAVE_NUM_PERI_AO_SYS2) && + (domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS2)) { + base = DEVAPC_PERI_AO_SYS2_D0_APC_0; + /* peri_ao2 */ + } else if ((slave_type == SLAVE_TYPE_PERI_AO2_SYS0) && + (module < SLAVE_NUM_PERI_AO2_SYS0) && + (domain_id < (uint32_t)DOM_NUM_PERI_AO2_SYS0)) { + base = DEVAPC_PERI_AO2_SYS0_D0_APC_0; + + /* peri_par_ao */ + } else if ((slave_type == SLAVE_TYPE_PERI_PAR_AO_SYS0) && + (module < SLAVE_NUM_PERI_PAR_AO_SYS0) && + (domain_id < (uint32_t)DOM_NUM_PERI_PAR_AO_SYS0)) { + base = DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0; + + } else { + ERROR("[DEVAPC] %s: %s, %s:0x%x, %s:0x%x, %s:0x%x\n", + __func__, "out of boundary", + "slave_type", slave_type, + "module", module, + "domain_id", domain_id); + } + + if (base != 0U) { + reg = base + domain_id * 0x40 + apc_register_index * 4; + mmio_clrsetbits_32(reg, clr_bit, set_bit); + } +} + +static void dump_infra_ao_apc(void) +{ + int reg_num; + int d, i; + + reg_num = (SLAVE_NUM_INFRA_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_INFRA_AO_SYS0_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } + + reg_num = (SLAVE_NUM_INFRA_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_INFRA_AO_SYS1; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (INFRA_AO_SYS1)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_INFRA_AO_SYS1_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } + + reg_num = (SLAVE_NUM_INFRA_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_INFRA_AO_SYS2; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (INFRA_AO_SYS2)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_INFRA_AO_SYS2_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } + + INFO("[DEVAPC] (INFRA_AO)MAS_SEC_0: 0x%x\n", + devapc_readl(DEVAPC_INFRA_AO_MAS_SEC_0)); +} + +static void dump_peri_ao_apc(void) +{ + int reg_num; + int d, i; + + reg_num = (SLAVE_NUM_PERI_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_PERI_AO_SYS0; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (PERI_AO_SYS0)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_PERI_AO_SYS0_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } + + reg_num = (SLAVE_NUM_PERI_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_PERI_AO_SYS1; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (PERI_AO_SYS1)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_PERI_AO_SYS1_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } + + reg_num = (SLAVE_NUM_PERI_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_PERI_AO_SYS2; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (PERI_AO_SYS2)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_PERI_AO_SYS2_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } + + INFO("[DEVAPC] (PERI_AO)MAS_SEC_0: 0x%x\n", + devapc_readl(DEVAPC_PERI_AO_MAS_SEC_0)); +} + +static void dump_peri_ao2_apc(void) +{ + int reg_num; + int d, i; + + reg_num = (SLAVE_NUM_PERI_AO2_SYS0 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_PERI_AO2_SYS0; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (PERI_AO2_SYS0)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_PERI_AO2_SYS0_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } +} + +static void dump_peri_par_ao_apc(void) +{ + int reg_num; + int d, i; + + reg_num = (SLAVE_NUM_PERI_PAR_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC; + for (d = 0; d < DOM_NUM_PERI_PAR_AO_SYS0; d++) { + for (i = 0; i <= reg_num; i++) { + INFO("[DEVAPC] (PERI_PAR_AO_SYS0)D%d_APC_%d: 0x%x\n", + d, i, devapc_readl( + DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0 + + d * 0x40 + i * 4) + ); + } + } + + INFO("[DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x%x\n", + devapc_readl(DEVAPC_PERI_PAR_AO_MAS_SEC_0)); +} + +static void set_infra_ao_apc(void) +{ + uint32_t infra_ao_size; + uint32_t i; + + infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS0_Devices); + + for (i = 0; i < infra_ao_size; i++) { + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_0, + INFRA_AO_SYS0_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_1, + INFRA_AO_SYS0_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_2, + INFRA_AO_SYS0_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_3, + INFRA_AO_SYS0_Devices[i].d3_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_4, + INFRA_AO_SYS0_Devices[i].d4_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_5, + INFRA_AO_SYS0_Devices[i].d5_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_6, + INFRA_AO_SYS0_Devices[i].d6_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_7, + INFRA_AO_SYS0_Devices[i].d7_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_8, + INFRA_AO_SYS0_Devices[i].d8_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_9, + INFRA_AO_SYS0_Devices[i].d9_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_10, + INFRA_AO_SYS0_Devices[i].d10_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_11, + INFRA_AO_SYS0_Devices[i].d11_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_12, + INFRA_AO_SYS0_Devices[i].d12_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_13, + INFRA_AO_SYS0_Devices[i].d13_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_14, + INFRA_AO_SYS0_Devices[i].d14_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_15, + INFRA_AO_SYS0_Devices[i].d15_permission); + } + + infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS1_Devices); + + for (i = 0; i < infra_ao_size; i++) { + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_0, + INFRA_AO_SYS1_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_1, + INFRA_AO_SYS1_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_2, + INFRA_AO_SYS1_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_3, + INFRA_AO_SYS1_Devices[i].d3_permission); + } + + infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS2_Devices); + + for (i = 0; i < infra_ao_size; i++) { + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_0, + INFRA_AO_SYS2_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_1, + INFRA_AO_SYS2_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_2, + INFRA_AO_SYS2_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_3, + INFRA_AO_SYS2_Devices[i].d3_permission); + } +} + +static void set_peri_ao_apc(void) +{ + uint32_t peri_ao_size; + uint32_t i; + + peri_ao_size = ARRAY_SIZE(PERI_AO_SYS0_Devices); + + for (i = 0; i < peri_ao_size; i++) { + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_0, + PERI_AO_SYS0_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_1, + PERI_AO_SYS0_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_2, + PERI_AO_SYS0_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_3, + PERI_AO_SYS0_Devices[i].d3_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_4, + PERI_AO_SYS0_Devices[i].d4_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_5, + PERI_AO_SYS0_Devices[i].d5_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_6, + PERI_AO_SYS0_Devices[i].d6_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_7, + PERI_AO_SYS0_Devices[i].d7_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_8, + PERI_AO_SYS0_Devices[i].d8_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_9, + PERI_AO_SYS0_Devices[i].d9_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_10, + PERI_AO_SYS0_Devices[i].d10_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_11, + PERI_AO_SYS0_Devices[i].d11_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_12, + PERI_AO_SYS0_Devices[i].d12_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_13, + PERI_AO_SYS0_Devices[i].d13_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_14, + PERI_AO_SYS0_Devices[i].d14_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_15, + PERI_AO_SYS0_Devices[i].d15_permission); + } + + peri_ao_size = ARRAY_SIZE(PERI_AO_SYS1_Devices); + + for (i = 0; i < peri_ao_size; i++) { + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_0, + PERI_AO_SYS1_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_1, + PERI_AO_SYS1_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_2, + PERI_AO_SYS1_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_3, + PERI_AO_SYS1_Devices[i].d3_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_4, + PERI_AO_SYS1_Devices[i].d4_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_5, + PERI_AO_SYS1_Devices[i].d5_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_6, + PERI_AO_SYS1_Devices[i].d6_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_7, + PERI_AO_SYS1_Devices[i].d7_permission); + } + + peri_ao_size = ARRAY_SIZE(PERI_AO_SYS2_Devices); + + for (i = 0; i < peri_ao_size; i++) { + set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_0, + PERI_AO_SYS2_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_1, + PERI_AO_SYS2_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_2, + PERI_AO_SYS2_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_3, + PERI_AO_SYS2_Devices[i].d3_permission); + } +} + +static void set_peri_ao2_apc(void) +{ + uint32_t peri_ao2_size; + uint32_t i; + + peri_ao2_size = ARRAY_SIZE(PERI_AO2_SYS0_Devices); + + for (i = 0; i < peri_ao2_size; i++) { + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_0, + PERI_AO2_SYS0_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_1, + PERI_AO2_SYS0_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_2, + PERI_AO2_SYS0_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_3, + PERI_AO2_SYS0_Devices[i].d3_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_4, + PERI_AO2_SYS0_Devices[i].d4_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_5, + PERI_AO2_SYS0_Devices[i].d5_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_6, + PERI_AO2_SYS0_Devices[i].d6_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_7, + PERI_AO2_SYS0_Devices[i].d7_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_8, + PERI_AO2_SYS0_Devices[i].d8_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_9, + PERI_AO2_SYS0_Devices[i].d9_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_10, + PERI_AO2_SYS0_Devices[i].d10_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_11, + PERI_AO2_SYS0_Devices[i].d11_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_12, + PERI_AO2_SYS0_Devices[i].d12_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_13, + PERI_AO2_SYS0_Devices[i].d13_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_14, + PERI_AO2_SYS0_Devices[i].d14_permission); + set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_15, + PERI_AO2_SYS0_Devices[i].d15_permission); + } +} + +static void set_peri_par_ao_apc(void) +{ + uint32_t peri_par_ao_size; + uint32_t i; + + peri_par_ao_size = ARRAY_SIZE(PERI_PAR_AO_SYS0_Devices); + + for (i = 0; i < peri_par_ao_size; i++) { + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_0, + PERI_PAR_AO_SYS0_Devices[i].d0_permission); /* APMCU */ + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_1, + PERI_PAR_AO_SYS0_Devices[i].d1_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_2, + PERI_PAR_AO_SYS0_Devices[i].d2_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_3, + PERI_PAR_AO_SYS0_Devices[i].d3_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_4, + PERI_PAR_AO_SYS0_Devices[i].d4_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_5, + PERI_PAR_AO_SYS0_Devices[i].d5_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_6, + PERI_PAR_AO_SYS0_Devices[i].d6_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_7, + PERI_PAR_AO_SYS0_Devices[i].d7_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_8, + PERI_PAR_AO_SYS0_Devices[i].d8_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_9, + PERI_PAR_AO_SYS0_Devices[i].d9_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_10, + PERI_PAR_AO_SYS0_Devices[i].d10_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_11, + PERI_PAR_AO_SYS0_Devices[i].d11_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_12, + PERI_PAR_AO_SYS0_Devices[i].d12_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_13, + PERI_PAR_AO_SYS0_Devices[i].d13_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_14, + PERI_PAR_AO_SYS0_Devices[i].d14_permission); + set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_15, + PERI_PAR_AO_SYS0_Devices[i].d15_permission); + } +} + +static void set_extra_apc(void) +{ +#ifdef MTK_DEBUGSYS_LOCK + /* Block debugsys to avoid privilege escalation (user load only) */ + set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, DEVAPC_DEBUGSYS_INDEX, + DOMAIN_0, SEC_RW_NS_R); +#endif +} + +void devapc_init(void) +{ + /* Initial Permission */ + set_infra_ao_apc(); + set_peri_ao_apc(); + set_peri_ao2_apc(); + set_peri_par_ao_apc(); + + /* Extra Permission */ + set_extra_apc(); + + /* Dump Permission */ + dump_infra_ao_apc(); + dump_peri_ao_apc(); + dump_peri_ao2_apc(); + dump_peri_par_ao_apc(); + + /* Setup APUSYS Permission */ + set_apusys_apc(); + + INFO("[DEVAPC] %s done\n", __func__); +} diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.h b/plat/mediatek/mt8192/drivers/devapc/devapc.h new file mode 100644 index 0000000..9033a0f --- /dev/null +++ b/plat/mediatek/mt8192/drivers/devapc/devapc.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DEVAPC_H +#define DEVAPC_H + +#include <stdint.h> +#include <platform_def.h> + +/****************************************************************************** + * FUNCTION DEFINITION + ******************************************************************************/ +void devapc_init(void); + +/****************************************************************************** + * STRUCTURE DEFINITION + ******************************************************************************/ +enum DEVAPC_PERM_TYPE { + NO_PROTECTION = 0, + SEC_RW_ONLY, + SEC_RW_NS_R, + FORBIDDEN, + PERM_NUM, +}; + +enum DOMAIN_ID { + DOMAIN_0 = 0, + DOMAIN_1, + DOMAIN_2, + DOMAIN_3, + DOMAIN_4, + DOMAIN_5, + DOMAIN_6, + DOMAIN_7, + DOMAIN_8, + DOMAIN_9, + DOMAIN_10, + DOMAIN_11, + DOMAIN_12, + DOMAIN_13, + DOMAIN_14, + DOMAIN_15, +}; + +/* Slave Type */ +enum DEVAPC_SLAVE_TYPE_SIMPLE { + SLAVE_TYPE_INFRA = 0, + SLAVE_TYPE_PERI, + SLAVE_TYPE_PERI2, + SLAVE_TYPE_PERI_PAR, +}; + +enum DEVAPC_SYS_INDEX { + DEVAPC_SYS0 = 0, + DEVAPC_SYS1, + DEVAPC_SYS2, +}; + +enum DEVAPC_SLAVE_TYPE { + SLAVE_TYPE_INFRA_AO_SYS0 = 0, + SLAVE_TYPE_INFRA_AO_SYS1, + SLAVE_TYPE_INFRA_AO_SYS2, + SLAVE_TYPE_PERI_AO_SYS0, + SLAVE_TYPE_PERI_AO_SYS1, + SLAVE_TYPE_PERI_AO_SYS2, + SLAVE_TYPE_PERI_AO2_SYS0, + SLAVE_TYPE_PERI_PAR_AO_SYS0, +}; + +/* Slave Num */ +enum DEVAPC_SLAVE_NUM { + SLAVE_NUM_INFRA_AO_SYS0 = 23, + SLAVE_NUM_INFRA_AO_SYS1 = 256, + SLAVE_NUM_INFRA_AO_SYS2 = 70, + SLAVE_NUM_PERI_AO_SYS0 = 105, + SLAVE_NUM_PERI_AO_SYS1 = 66, + SLAVE_NUM_PERI_AO_SYS2 = 1, + SLAVE_NUM_PERI_AO2_SYS0 = 115, + SLAVE_NUM_PERI_PAR_AO_SYS0 = 27, +}; + +enum DEVAPC_SYS_DOM_NUM { + DOM_NUM_INFRA_AO_SYS0 = 16, + DOM_NUM_INFRA_AO_SYS1 = 4, + DOM_NUM_INFRA_AO_SYS2 = 4, + DOM_NUM_PERI_AO_SYS0 = 16, + DOM_NUM_PERI_AO_SYS1 = 8, + DOM_NUM_PERI_AO_SYS2 = 4, + DOM_NUM_PERI_AO2_SYS0 = 16, + DOM_NUM_PERI_PAR_AO_SYS0 = 16, +}; + +enum DEVAPC_CFG_INDEX { + DEVAPC_DEBUGSYS_INDEX = 57, +}; + +struct APC_INFRA_PERI_DOM_16 { + unsigned char d0_permission; + unsigned char d1_permission; + unsigned char d2_permission; + unsigned char d3_permission; + unsigned char d4_permission; + unsigned char d5_permission; + unsigned char d6_permission; + unsigned char d7_permission; + unsigned char d8_permission; + unsigned char d9_permission; + unsigned char d10_permission; + unsigned char d11_permission; + unsigned char d12_permission; + unsigned char d13_permission; + unsigned char d14_permission; + unsigned char d15_permission; +}; + +struct APC_INFRA_PERI_DOM_8 { + unsigned char d0_permission; + unsigned char d1_permission; + unsigned char d2_permission; + unsigned char d3_permission; + unsigned char d4_permission; + unsigned char d5_permission; + unsigned char d6_permission; + unsigned char d7_permission; +}; + +struct APC_INFRA_PERI_DOM_4 { + unsigned char d0_permission; + unsigned char d1_permission; + unsigned char d2_permission; + unsigned char d3_permission; +}; + +#define DAPC_INFRA_AO_SYS0_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \ + (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \ + (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \ + (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \ + (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \ + (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \ + (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15} + +#define DAPC_INFRA_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3} + +#define DAPC_PERI_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \ + (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \ + (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7} + +#define DAPC_INFRA_AO_SYS2_ATTR(...) DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__) +#define DAPC_PERI_AO_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__) +#define DAPC_PERI_AO_SYS2_ATTR(...) DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__) +#define DAPC_PERI_AO2_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__) +#define DAPC_PERI_PAR_AO_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__) + +/****************************************************************************** + * UTILITY DEFINITION + ******************************************************************************/ +#define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) +#define devapc_readl(REG) mmio_read_32((uintptr_t)REG) + +/******************************************************************************/ +/* Device APC AO for INFRA AO */ +#define DEVAPC_INFRA_AO_SYS0_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x0000) +#define DEVAPC_INFRA_AO_SYS1_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x1000) +#define DEVAPC_INFRA_AO_SYS2_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x2000) + +#define DEVAPC_INFRA_AO_MAS_SEC_0 (DEVAPC_INFRA_AO_BASE + 0x0A00) + +/******************************************************************************/ +/* Device APC AO for PERI AO */ +#define DEVAPC_PERI_AO_SYS0_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x0000) +#define DEVAPC_PERI_AO_SYS1_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x1000) +#define DEVAPC_PERI_AO_SYS2_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x2000) + +#define DEVAPC_PERI_AO_MAS_SEC_0 (DEVAPC_PERI_AO_BASE + 0x0A00) + +/******************************************************************************/ +/* Device APC AO for PERI AO2 */ +#define DEVAPC_PERI_AO2_SYS0_D0_APC_0 (DEVAPC_PERI_AO2_BASE + 0x0000) + +/******************************************************************************/ +/* Device APC AO for PERI PAR AO */ +#define DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0 (DEVAPC_PERI_PAR_AO_BASE + 0x0000) + +#define DEVAPC_PERI_PAR_AO_MAS_SEC_0 (DEVAPC_PERI_PAR_AO_BASE + 0x0A00) + +/******************************************************************************/ + + +/****************************************************************************** + * Variable DEFINITION + ******************************************************************************/ +#define MOD_NO_IN_1_DEVAPC 16 + +#endif /* DEVAPC_H */ + diff --git a/plat/mediatek/mt8192/drivers/dfd/plat_dfd.c b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.c new file mode 100644 index 0000000..69c395e --- /dev/null +++ b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch_helpers.h> +#include <common/debug.h> +#include <lib/mmio.h> +#include <mtk_sip_svc.h> +#include <plat_dfd.h> + +static bool dfd_enabled; +static uint64_t dfd_base_addr; +static uint64_t dfd_chain_length; +static uint64_t dfd_cache_dump; + +static void dfd_setup(uint64_t base_addr, uint64_t chain_length, + uint64_t cache_dump) +{ + /* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */ + /* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */ + sync_writel(DFD_INTERNAL_CTL, 0x5); + + /* bit[13]: xreset_b_update_disable */ + mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); + + /* + * bit[10:3]: DFD trigger selection mask + * bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger) + * bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger) + * bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger) + * bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger) + * bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger) + */ + mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3); + + /* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */ + mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); + + /* + * bit[0]: rg_rw_dfd_auto_power_on = 1 + * bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us) + * bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us) + */ + mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); + + /* longest scan chain length */ + mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); + + /* bit[1:0]: rg_rw_dfd_shift_clock_ratio */ + mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); + + /* rg_dfd_test_so_over_64 */ + mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); + + /* DFD3.0 */ + mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_DIS_VAL); + mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL); + mmio_write_32(DFD_TEST_SI_2, DFD_TEST_SI_2_VAL); + mmio_write_32(DFD_TEST_SI_3, DFD_TEST_SI_3_VAL); + + /* for iLDO feature */ + sync_writel(DFD_POWER_CTL, 0xF9); + + /* set base address */ + mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); + + /* + * disable sleep protect of DFD + * 10001220[8]: protect_en_reg[8] + * 10001a3c[2]: infra_mcu_pwr_ctl_mask[2] + */ + mmio_clrbits_32(DFD_O_PROTECT_EN_REG, 1 << 8); + mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 1 << 2); + + /* clean DFD trigger status */ + sync_writel(DFD_CLEAN_STATUS, 0x1); + sync_writel(DFD_CLEAN_STATUS, 0x0); + + /* DFD-3.0 */ + sync_writel(DFD_V30_CTL, 0x1); + + /* setup global variables for suspend and resume */ + dfd_enabled = true; + dfd_base_addr = base_addr; + dfd_chain_length = chain_length; + dfd_cache_dump = cache_dump; + + if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { + /* DFD3.5 */ + mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_EN_VAL); + sync_writel(DFD_V35_ENALBE, 0x1); + sync_writel(DFD_V35_TAP_NUMBER, 0xB); + sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); + sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); + + if (cache_dump & DFD_PARITY_ERR_TRIGGER) { + sync_writel(DFD_HW_TRIGGER_MASK, 0xC); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); + } + } + dsbsy(); +} + +void dfd_resume(void) +{ + if (dfd_enabled == true) { + dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); + } +} + +uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3) +{ + uint64_t ret = 0L; + + switch (arg0) { + case PLAT_MTK_DFD_SETUP_MAGIC: + dfd_setup(arg1, arg2, arg3); + break; + case PLAT_MTK_DFD_READ_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + ret = mmio_read_32(MISC1_CFG_BASE + arg1); + } + break; + case PLAT_MTK_DFD_WRITE_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + sync_writel(MISC1_CFG_BASE + arg1, arg2); + } + break; + default: + ret = MTK_SIP_E_INVALID_PARAM; + break; + } + + return ret; +} diff --git a/plat/mediatek/mt8192/drivers/dfd/plat_dfd.h b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.h new file mode 100644 index 0000000..7f0f4b5 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DFD_H +#define PLAT_DFD_H + +#include <arch_helpers.h> +#include <lib/mmio.h> +#include <platform_def.h> + +#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \ + dsbsy(); \ + } while (0) + +#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) +#define PLAT_MTK_DFD_READ_MAGIC (0x99716151) +#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) + +#define MCU_BIU_BASE (MCUCFG_BASE) +#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) +#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) +#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08) +#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C) +#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10) +#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C) +#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20) +#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24) +#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28) +#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30) +#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34) +#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48) +#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C) +#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50) +#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58) +#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C) +#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60) +#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8) +#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC) +#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC) + +#define DFD_V35_ENALBE (MCU_BIU_BASE + 0xE0A8) +#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC) +#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0) +#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4) +#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0) +#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4) + +#define DFD_O_PROTECT_EN_REG (0x10001220) +#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C) +#define DFD_O_SET_BASEADDR_REG (0x10043034) + +#define DFD_CACHE_DUMP_ENABLE 1U +#define DFD_PARITY_ERR_TRIGGER 2U + +#define DFD_TEST_SI_0_CACHE_DIS_VAL (0x1E000202) +#define DFD_TEST_SI_0_CACHE_EN_VAL (0x1E000002) +#define DFD_TEST_SI_1_VAL (0x20408100) +#define DFD_TEST_SI_2_VAL (0x10101000) +#define DFD_TEST_SI_3_VAL (0x00000010) +#define DFD_V35_TAP_EN_VAL (0x43FF) +#define DFD_V35_SEQ0_0_VAL (0x63668820) + +void dfd_resume(void); +uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3); + +#endif /* PLAT_DFD_H */ diff --git a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c new file mode 100644 index 0000000..26bed29 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <emi_mpu.h> +#include <lib/mmio.h> + +/* + * emi_mpu_set_region_protection: protect a region. + * @start: start address of the region + * @end: end address of the region + * @access_permission: EMI MPU access permission + * Return 0 for success, otherwise negative status code. + */ +static int _emi_mpu_set_protection( + unsigned long start, unsigned long end, + unsigned int apc) +{ + unsigned int dgroup; + unsigned int region; + + region = (start >> 24) & 0xFF; + start &= 0x00FFFFFF; + dgroup = (end >> 24) & 0xFF; + end &= 0x00FFFFFF; + + if ((region >= EMI_MPU_REGION_NUM) || (dgroup > EMI_MPU_DGROUP_NUM)) { + WARN("Region:%u or dgroup:%u is wrong!\n", region, dgroup); + return -1; + } + + apc &= 0x80FFFFFF; + + if ((start >= DRAM_OFFSET) && (end >= start)) { + start -= DRAM_OFFSET; + end -= DRAM_OFFSET; + } else { + WARN("start:0x%lx or end:0x%lx address is wrong!\n", + start, end); + return -2; + } + + mmio_write_32(EMI_MPU_SA(region), start); + mmio_write_32(EMI_MPU_EA(region), end); + mmio_write_32(EMI_MPU_APC(region, dgroup), apc); + + return 0; +} + +void dump_emi_mpu_regions(void) +{ + unsigned long apc[EMI_MPU_DGROUP_NUM], sa, ea; + + int region, i; + + /* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */ + for (region = 0; region < 8; ++region) { + for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i) + apc[i] = mmio_read_32(EMI_MPU_APC(region, i)); + sa = mmio_read_32(EMI_MPU_SA(region)); + ea = mmio_read_32(EMI_MPU_EA(region)); + + WARN("region %d:\n", region); + WARN("\tsa:0x%lx, ea:0x%lx, apc0: 0x%lx apc1: 0x%lx\n", + sa, ea, apc[0], apc[1]); + } +} + +int emi_mpu_set_protection(struct emi_region_info_t *region_info) +{ + unsigned long start, end; + int i; + + if (region_info->region >= EMI_MPU_REGION_NUM) + return -1; + + start = (unsigned long)(region_info->start >> EMI_MPU_ALIGN_BITS) | + (region_info->region << 24); + + for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) { + end = (unsigned long)(region_info->end >> EMI_MPU_ALIGN_BITS) | + (i << 24); + _emi_mpu_set_protection(start, end, region_info->apc[i]); + } + + return 0; +} + +void emi_mpu_init(void) +{ + struct emi_region_info_t region_info; + + /* reserve region 0 for future use */ + + /* PCI-e protect address(64MB) */ + region_info.start = 0xC0000000ULL; + region_info.end = 0xC3FF0000ULL; + region_info.region = 1; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, NO_PROT, NO_PROT); + emi_mpu_set_protection(®ion_info); + + /* SCP protect address */ + region_info.start = 0x50000000ULL; + region_info.end = 0x513F0000ULL; + region_info.region = 2; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + NO_PROT, FORBIDDEN, FORBIDDEN, NO_PROT); + emi_mpu_set_protection(®ion_info); + + /* DSP protect address */ + region_info.start = 0x40000000ULL; /* dram base addr */ + region_info.end = 0x1FFFF0000ULL; + region_info.region = 3; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROT); + emi_mpu_set_protection(®ion_info); + + /* Forbidden All */ + region_info.start = 0x40000000ULL; /* dram base addr */ + region_info.end = 0x1FFFF0000ULL; + region_info.region = 4; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROT); + emi_mpu_set_protection(®ion_info); + + dump_emi_mpu_regions(); +} + diff --git a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h new file mode 100644 index 0000000..0b15431 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMI_MPU_H +#define EMI_MPU_H + +#include <platform_def.h> + +#define EMI_MPUP (EMI_BASE + 0x01D8) +#define EMI_MPUQ (EMI_BASE + 0x01E0) +#define EMI_MPUR (EMI_BASE + 0x01E8) +#define EMI_MPUS (EMI_BASE + 0x01F0) +#define EMI_MPUT (EMI_BASE + 0x01F8) +#define EMI_MPUY (EMI_BASE + 0x0220) +#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000) +#define EMI_MPUD0_ST (EMI_BASE + 0x0160) +#define EMI_MPUD1_ST (EMI_BASE + 0x0164) +#define EMI_MPUD2_ST (EMI_BASE + 0x0168) +#define EMI_MPUD3_ST (EMI_BASE + 0x016C) +#define EMI_MPUD0_ST2 (EMI_BASE + 0x0200) +#define EMI_MPUD1_ST2 (EMI_BASE + 0x0204) +#define EMI_MPUD2_ST2 (EMI_BASE + 0x0208) +#define EMI_MPUD3_ST2 (EMI_BASE + 0x020C) + +#define EMI_PHY_OFFSET (0x40000000UL) + +#define NO_PROT (0) +#define SEC_RW (1) +#define SEC_RW_NSEC_R (2) +#define SEC_RW_NSEC_W (3) +#define SEC_R_NSEC_R (4) +#define FORBIDDEN (5) +#define SEC_R_NSEC_RW (6) + +#define SECURE_OS_MPU_REGION_ID (0) +#define ATF_MPU_REGION_ID (1) + +#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) +#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) +#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region) * 4) +#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region) * 4) + +#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) +#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region) * 4 + \ + (dgroup) * 0x100) + +#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) +#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4) +#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900) +#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4) + +#define EMI_MPU_DOMAIN_NUM 16 +#define EMI_MPU_REGION_NUM 32 +#define EMI_MPU_ALIGN_BITS 16 +#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) + +#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) + +#if (EMI_MPU_DGROUP_NUM == 1) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[0] = 0; \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \ + | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \ + | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \ + | (((unsigned int) d1) << 3) | ((unsigned int) d0) \ + | (((unsigned int) lock) << 31); \ +} while (0) +#elif (EMI_MPU_DGROUP_NUM == 2) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \ + d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[1] = \ + (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) \ + | (((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) \ + | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) \ + | (((unsigned int) d9) << 3) | ((unsigned int) d8); \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \ + | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \ + | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \ + | (((unsigned int) d1) << 3) | ((unsigned int) d0) \ + | (((unsigned int) lock) << 31); \ +} while (0) +#endif + +struct emi_region_info_t { + unsigned long long start; + unsigned long long end; + unsigned int region; + unsigned long apc[EMI_MPU_DGROUP_NUM]; +}; + +void emi_mpu_init(void); +int emi_mpu_set_protection(struct emi_region_info_t *region_info); +void dump_emi_mpu_regions(void); + +#endif /* __EMI_MPU_H */ diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c new file mode 100644 index 0000000..c78332d --- /dev/null +++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <mtgpio.h> +#include <platform_def.h> + +uintptr_t mt_gpio_find_reg_addr(uint32_t pin) +{ + uintptr_t reg_addr = 0U; + struct mt_pin_info gpio_info; + + assert(pin < MAX_GPIO_PIN); + + gpio_info = mt_pin_infos[pin]; + + switch (gpio_info.base & 0x0f) { + case 0: + reg_addr = IOCFG_RM_BASE; + break; + case 1: + reg_addr = IOCFG_BM_BASE; + break; + case 2: + reg_addr = IOCFG_BL_BASE; + break; + case 3: + reg_addr = IOCFG_BR_BASE; + break; + case 4: + reg_addr = IOCFG_LM_BASE; + break; + case 5: + reg_addr = IOCFG_LB_BASE; + break; + case 6: + reg_addr = IOCFG_RT_BASE; + break; + case 7: + reg_addr = IOCFG_LT_BASE; + break; + case 8: + reg_addr = IOCFG_TL_BASE; + break; + default: + break; + } + + return reg_addr; +} diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h new file mode 100644 index 0000000..d3aa24d --- /dev/null +++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_GPIO_H +#define MT_GPIO_H + +#include <mtgpio_common.h> + +/* Enumeration for GPIO pin */ +typedef enum GPIO_PIN { + GPIO_UNSUPPORTED = -1, + + GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, + GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15, + GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23, + GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31, + GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39, + GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47, + GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55, + GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63, + GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71, + GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79, + GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87, + GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95, + GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103, + GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111, + GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119, + GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127, + GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135, + GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143, + GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150, GPIO151, + GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158, GPIO159, + GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166, GPIO167, + GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174, GPIO175, + GPIO176, GPIO177, GPIO178, GPIO179, GPIO180, GPIO181, GPIO182, GPIO183, + GPIO184, GPIO185, GPIO186, GPIO187, GPIO188, GPIO189, GPIO190, GPIO191, + GPIO192, GPIO193, GPIO194, GPIO195, GPIO196, GPIO197, GPIO198, GPIO199, + GPIO200, GPIO201, GPIO202, GPIO203, GPIO204, GPIO205, GPIO206, GPIO207, + GPIO208, GPIO209, GPIO210, GPIO211, GPIO212, GPIO213, GPIO214, GPIO215, + GPIO216, GPIO217, GPIO218, GPIO219, + MT_GPIO_BASE_MAX +} GPIO_PIN; + +static const struct mt_pin_info mt_pin_infos[] = { + PIN(0, 0, 9, 0x23, 0xb0), + PIN(1, 0, 10, 0x23, 0xb0), + PIN(2, 0, 11, 0x23, 0xb0), + PIN(3, 0, 12, 0x23, 0xb0), + PIN(4, 0, 13, 0x23, 0xb0), + PIN(5, 0, 14, 0x23, 0xb0), + PIN(6, 0, 15, 0x23, 0xb0), + PIN(7, 0, 16, 0x23, 0xb0), + PIN(8, 0, 17, 0x23, 0xb0), + PIN(9, 0, 18, 0x23, 0xb0), + PIN(10, 1, 0, 0x15, 0x20), + PIN(11, 1, 1, 0x15, 0x20), + PIN(12, 1, 2, 0x15, 0x20), + PIN(13, 1, 3, 0x15, 0x20), + PIN(14, 1, 4, 0x15, 0x20), + PIN(15, 1, 5, 0x15, 0x20), + PIN(16, 0, 2, 0x17, 0x50), + PIN(17, 0, 3, 0x17, 0x50), + PIN(18, 0, 21, 0x36, 0xa0), + PIN(19, 0, 22, 0x36, 0xa0), + PIN(20, 0, 23, 0x36, 0xa0), + PIN(21, 0, 24, 0x36, 0xa0), + PIN(22, 0, 3, 0x21, 0x90), + PIN(23, 0, 4, 0x21, 0x90), + PIN(24, 0, 5, 0x21, 0x90), + PIN(25, 0, 6, 0x21, 0x90), + PIN(26, 0, 5, 0x22, 0x80), + PIN(27, 0, 6, 0x22, 0x80), + PIN(28, 0, 7, 0x22, 0x80), + PIN(29, 0, 8, 0x22, 0x80), + PIN(30, 0, 9, 0x22, 0x80), + PIN(31, 0, 27, 0x22, 0x70), + PIN(32, 0, 24, 0x22, 0x70), + PIN(33, 0, 26, 0x22, 0x70), + PIN(34, 0, 23, 0x22, 0x70), + PIN(35, 0, 25, 0x22, 0x70), + PIN(36, 0, 20, 0x21, 0x90), + PIN(37, 0, 21, 0x21, 0x90), + PIN(38, 0, 22, 0x21, 0x90), + PIN(39, 0, 23, 0x21, 0x90), + PIN(40, 0, 0, 0x17, 0x50), + PIN(41, 0, 1, 0x17, 0x50), + PIN(42, 0, 4, 0x17, 0x50), + PIN(43, 0, 25, 0x36, 0xa0), + PIN(44, 0, 26, 0x36, 0xa0), + PIN(45, 1, 9, 0x20, 0x60), + PIN(46, 1, 11, 0x20, 0x60), + PIN(47, 1, 10, 0x20, 0x60), + PIN(48, 1, 7, 0x20, 0x60), + PIN(49, 1, 8, 0x20, 0x60), + PIN(50, 1, 6, 0x20, 0x60), + PIN(51, 1, 0, 0x20, 0x60), + PIN(52, 1, 1, 0x20, 0x60), + PIN(53, 1, 5, 0x20, 0x60), + PIN(54, 1, 2, 0x20, 0x60), + PIN(55, 1, 4, 0x20, 0x60), + PIN(56, 1, 3, 0x20, 0x60), + PIN(57, 0, 1, 0x22, 0x80), + PIN(58, 0, 2, 0x22, 0x80), + PIN(59, 0, 3, 0x22, 0x80), + PIN(60, 0, 4, 0x22, 0x80), + PIN(61, 0, 28, 0x22, 0x70), + PIN(62, 0, 22, 0x22, 0x70), + PIN(63, 0, 0, 0x22, 0x70), + PIN(64, 0, 1, 0x22, 0x70), + PIN(65, 0, 12, 0x22, 0x70), + PIN(66, 0, 15, 0x22, 0x70), + PIN(67, 0, 16, 0x22, 0x70), + PIN(68, 0, 17, 0x22, 0x70), + PIN(69, 0, 18, 0x22, 0x70), + PIN(70, 0, 19, 0x22, 0x70), + PIN(71, 0, 20, 0x22, 0x70), + PIN(72, 0, 21, 0x22, 0x70), + PIN(73, 0, 2, 0x22, 0x70), + PIN(74, 0, 3, 0x22, 0x70), + PIN(75, 0, 4, 0x22, 0x70), + PIN(76, 0, 5, 0x22, 0x70), + PIN(77, 0, 6, 0x22, 0x70), + PIN(78, 0, 7, 0x22, 0x70), + PIN(79, 0, 8, 0x22, 0x70), + PIN(80, 0, 9, 0x22, 0x70), + PIN(81, 0, 10, 0x22, 0x70), + PIN(82, 0, 11, 0x22, 0x70), + PIN(83, 0, 13, 0x22, 0x70), + PIN(84, 0, 14, 0x22, 0x70), + PIN(85, 0, 31, 0x22, 0x70), + PIN(86, 0, 0, 0x22, 0x80), + PIN(87, 0, 29, 0x22, 0x70), + PIN(88, 0, 30, 0x22, 0x70), + PIN(89, 0, 24, 0x21, 0x90), + PIN(90, 0, 25, 0x21, 0x90), + PIN(91, 0, 0, 0x21, 0x90), + PIN(92, 0, 2, 0x21, 0xa0), + PIN(93, 0, 4, 0x21, 0xa0), + PIN(94, 0, 3, 0x21, 0xa0), + PIN(95, 0, 5, 0x21, 0xa0), + PIN(96, 0, 31, 0x21, 0x90), + PIN(97, 0, 26, 0x21, 0x90), + PIN(98, 0, 0, 0x21, 0xa0), + PIN(99, 0, 27, 0x21, 0x90), + PIN(100, 0, 28, 0x21, 0x90), + PIN(101, 0, 29, 0x21, 0x90), + PIN(102, 0, 30, 0x21, 0x90), + PIN(103, 0, 18, 0x21, 0x90), + PIN(104, 0, 17, 0x21, 0x90), + PIN(105, 0, 19, 0x21, 0x90), + PIN(106, 0, 16, 0x21, 0x90), + PIN(107, 0, 1, 0x21, 0x90), + PIN(108, 0, 2, 0x21, 0x90), + PIN(109, 0, 10, 0x21, 0x90), + PIN(110, 0, 7, 0x21, 0x90), + PIN(111, 0, 9, 0x21, 0x90), + PIN(112, 0, 11, 0x21, 0x90), + PIN(113, 0, 8, 0x21, 0x90), + PIN(114, 0, 14, 0x21, 0x90), + PIN(115, 0, 13, 0x21, 0x90), + PIN(116, 0, 15, 0x21, 0x90), + PIN(117, 0, 12, 0x21, 0x90), + PIN(118, 0, 23, 0x23, 0xb0), + PIN(119, 0, 29, 0x23, 0xb0), + PIN(120, 0, 28, 0x23, 0xb0), + PIN(121, 0, 2, 0x23, 0xc0), + PIN(122, 0, 27, 0x23, 0xb0), + PIN(123, 0, 1, 0x23, 0xc0), + PIN(124, 0, 26, 0x23, 0xb0), + PIN(125, 0, 0, 0x23, 0xc0), + PIN(126, 0, 19, 0x23, 0xb0), + PIN(127, 0, 20, 0x23, 0xb0), + PIN(128, 0, 21, 0x23, 0xb0), + PIN(129, 0, 22, 0x23, 0xb0), + PIN(130, 0, 6, 0x23, 0xb0), + PIN(131, 0, 7, 0x23, 0xb0), + PIN(132, 0, 8, 0x23, 0xb0), + PIN(133, 0, 3, 0x23, 0xb0), + PIN(134, 0, 4, 0x23, 0xb0), + PIN(135, 0, 5, 0x23, 0xb0), + PIN(136, 0, 0, 0x23, 0xb0), + PIN(137, 0, 1, 0x23, 0xb0), + PIN(138, 0, 2, 0x23, 0xb0), + PIN(139, 0, 25, 0x23, 0xb0), + PIN(140, 0, 31, 0x23, 0xb0), + PIN(141, 0, 24, 0x23, 0xb0), + PIN(142, 0, 30, 0x23, 0xb0), + PIN(143, 0, 6, 0x20, 0x70), + PIN(144, 0, 7, 0x20, 0x70), + PIN(145, 0, 8, 0x20, 0x70), + PIN(146, 0, 3, 0x20, 0x70), + PIN(147, 0, 4, 0x20, 0x70), + PIN(148, 0, 5, 0x20, 0x70), + PIN(149, 0, 0, 0x20, 0x70), + PIN(150, 0, 1, 0x20, 0x70), + PIN(151, 0, 2, 0x20, 0x70), + PIN(152, 1, 3, 0x36, 0x90), + PIN(153, 1, 2, 0x36, 0x90), + PIN(154, 1, 0, 0x36, 0x906), + PIN(155, 1, 1, 0x36, 0x90), + PIN(156, 0, 29, 0x36, 0xa0), + PIN(157, 0, 30, 0x36, 0xa0), + PIN(158, 0, 31, 0x36, 0xa0), + PIN(159, 0, 0, 0x36, 0xb0), + PIN(160, 0, 27, 0x36, 0xa04), + PIN(161, 0, 28, 0x36, 0xa0), + PIN(162, 0, 0, 0x36, 0xa0), + PIN(163, 0, 1, 0x36, 0xa0), + PIN(164, 0, 2, 0x36, 0xa0), + PIN(165, 0, 3, 0x36, 0xa0), + PIN(166, 0, 4, 0x36, 0xa0), + PIN(167, 0, 5, 0x36, 0xa0), + PIN(168, 0, 6, 0x36, 0xa0), + PIN(169, 0, 7, 0x36, 0xa0), + PIN(170, 0, 8, 0x36, 0xa0), + PIN(171, 0, 9, 0x36, 0xa0), + PIN(172, 0, 13, 0x36, 0xa0), + PIN(173, 0, 14, 0x36, 0xa0), + PIN(174, 0, 12, 0x36, 0xa0), + PIN(175, 0, 15, 0x36, 0xa0), + PIN(176, 0, 10, 0x36, 0xa0), + PIN(177, 0, 11, 0x36, 0xa0), + PIN(178, 0, 16, 0x36, 0xa0), + PIN(179, 0, 17, 0x36, 0xa0), + PIN(180, 0, 18, 0x36, 0xa0), + PIN(181, 0, 19, 0x36, 0xa0), + PIN(182, 0, 20, 0x36, 0xa0), + PIN(183, 1, 1, 0x18, 0x30), + PIN(184, 1, 2, 0x18, 0x30), + PIN(185, 1, 4, 0x18, 0x30), + PIN(186, 1, 6, 0x18, 0x30), + PIN(187, 1, 8, 0x18, 0x30), + PIN(188, 1, 3, 0x18, 0x30), + PIN(189, 1, 7, 0x18, 0x30), + PIN(190, 1, 9, 0x18, 0x30), + PIN(191, 1, 10, 0x18, 0x30), + PIN(192, 1, 0, 0x18, 0x30), + PIN(193, 1, 5, 0x18, 0x30), + PIN(194, 1, 11, 0x18, 0x30), + PIN(195, 0, 16, 0x14, 0x50), + PIN(196, 0, 6, 0x14, 0x50), + PIN(197, 0, 8, 0x14, 0x50), + PIN(198, 0, 7, 0x14, 0x50), + PIN(199, 0, 3, 0x14, 0x50), + PIN(200, 0, 6, 0x17, 0x50), + PIN(201, 0, 8, 0x17, 0x50), + PIN(202, 0, 15, 0x14, 0x50), + PIN(203, 0, 17, 0x14, 0x50), + PIN(204, 0, 5, 0x17, 0x50), + PIN(205, 0, 7, 0x17, 0x50), + PIN(206, 0, 18, 0x14, 0x50), + PIN(207, 0, 19, 0x14, 0x50), + PIN(208, 0, 20, 0x14, 0x50), + PIN(209, 0, 12, 0x14, 0x50), + PIN(210, 0, 11, 0x14, 0x50), + PIN(211, 0, 13, 0x14, 0x50), + PIN(212, 0, 10, 0x14, 0x50), + PIN(213, 0, 14, 0x14, 0x50), + PIN(214, 0, 0, 0x14, 0x50), + PIN(215, 0, 9, 0x14, 0x50), + PIN(216, 0, 4, 0x14, 0x50), + PIN(217, 0, 5, 0x14, 0x50), + PIN(218, 0, 1, 0x14, 0x50), + PIN(219, 0, 2, 0x14, 0x50), +}; +#endif /* MT_GPIO_H */ diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c new file mode 100644 index 0000000..b483c36 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stdint.h> + +#include <arch_helpers.h> +#include <lib/psci/psci.h> +#include <lib/spinlock.h> + +#include <mt_cpu_pm_cpc.h> +#include <mt_lp_irqremain.h> +#include <mt_lp_rm.h> +#include <mt_mcdi.h> +#include <plat_mtk_lpm.h> +#include <plat_pm.h> + +DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1); + +static int plat_mt_lp_cpu_rc; + +static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) +{ + return 0; +} + +static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) +{ + mtk_cpc_core_on_hint_clr(cpu); + + if (IS_SYSTEM_SUSPEND_STATE(state)) { + mtk_cpc_time_sync(); + } + + return 0; +} + +static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) +{ + return 0; +} + +static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) +{ + /* clear DBGPRCR.CORENPDRQ to allow CPU power down */ + write_dbgprcr_el1(0ULL); + + return 0; +} + +static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) +{ + return 0; +} + +static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) +{ + return 0; +} + +static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) +{ + if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { + return -1; + } + + mtk_cpc_mcusys_off_reflect(); + + return 0; +} + +static int pwr_mcusys_pwron_finished(unsigned int cpu, + const psci_power_state_t *state) +{ + int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS]; + + if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { + return -1; + } + + mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id); + mt_lp_irqremain_release(); + + return 0; +} + +static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state) +{ + int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS]; + + if (!IS_MCUSYS_OFF_STATE(state)) { + goto mt_pwr_mcusysoff_break; + } + + if (mcdi_try_init() != 0) { + goto mt_pwr_mcusysoff_break; + } + + if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) { + goto mt_pwr_mcusysoff_break; + } + + plat_mt_lp_cpu_rc = + mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL); + + if (plat_mt_lp_cpu_rc < 0) { + goto mt_pwr_mcusysoff_reflect; + } + + mt_lp_irqremain_aquire(); + + return 0; + +mt_pwr_mcusysoff_reflect: + mtk_cpc_mcusys_off_reflect(); + +mt_pwr_mcusysoff_break: + plat_mt_lp_cpu_rc = -1; + + return -1; +} + +static const struct mt_lpm_tz plat_pm = { + .pwr_prompt = pwr_state_prompt, + .pwr_reflect = pwr_state_reflect, + .pwr_cpu_on = pwr_cpu_pwron, + .pwr_cpu_dwn = pwr_cpu_pwrdwn, + .pwr_cluster_on = pwr_cluster_pwron, + .pwr_cluster_dwn = pwr_cluster_pwrdwn, + .pwr_mcusys_dwn = pwr_mcusys_pwrdwn, + .pwr_mcusys_on = pwr_mcusys_pwron, + .pwr_mcusys_on_finished = pwr_mcusys_pwron_finished +}; + +const struct mt_lpm_tz *mt_plat_cpu_pm_init(void) +{ + mtk_cpc_init(); + + if (mcdi_try_init() == 0) { + INFO("MCDI init done.\n"); + } + + mt_lp_irqremain_init(); + + return &plat_pm; +} diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c new file mode 100644 index 0000000..f8c51a1 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <string.h> + +#include <drivers/delay_timer.h> + +#include <mt_cpu_pm_cpc.h> +#include <mt_timer.h> + +struct mtk_cpc_dev { + int auto_off; + unsigned int auto_thres_tick; +}; + +static struct mtk_cpc_dev cpc; + +static int mtk_cpc_last_core_prot(uint32_t prot_req, + uint32_t resp_reg, uint32_t resp_ofs) +{ + uint32_t sta, retry; + + retry = 0U; + + while (retry++ < RETRY_CNT_MAX) { + + mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req); + + udelay(1U); + + sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK; + + if (sta == PROT_SUCCESS) { + return CPC_SUCCESS; + } else if (sta == PROT_GIVEUP) { + return CPC_ERR_FAIL; + } + } + + return CPC_ERR_TIMEOUT; +} + +int mtk_cpu_pm_mcusys_prot_aquire(void) +{ + return mtk_cpc_last_core_prot( + MCUSYS_PROT_SET, + CPC_MCUSYS_LAST_CORE_RESP, + MCUSYS_RESP_OFS); +} + +void mtk_cpu_pm_mcusys_prot_release(void) +{ + mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); +} + +int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster) +{ + return mtk_cpc_last_core_prot( + CPUSYS_PROT_SET, + CPC_MCUSYS_MP_LAST_CORE_RESP, + CPUSYS_RESP_OFS); +} + +void mtk_cpu_pm_cluster_prot_release(unsigned int cluster) +{ + mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); +} + +static void mtk_cpc_cluster_cnt_backup(void) +{ + uint32_t backup_cnt; + uint32_t curr_cnt; + uint32_t cnt_mask = GENMASK(14, 0); + uint32_t clr_mask = GENMASK(1, 0); + + /* Single Cluster */ + backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP); + curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER); + + /* Get off count if dormant count is 0 */ + if ((curr_cnt & cnt_mask) == 0U) { + curr_cnt = (curr_cnt >> 16) & cnt_mask; + } else { + curr_cnt = curr_cnt & cnt_mask; + } + + mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt); + mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask); +} + +static inline void mtk_cpc_mcusys_off_en(void) +{ + mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U); +} + +static inline void mtk_cpc_mcusys_off_dis(void) +{ + mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U); +} + +void mtk_cpc_mcusys_off_reflect(void) +{ + mtk_cpc_mcusys_off_dis(); + mtk_cpu_pm_mcusys_prot_release(); +} + +int mtk_cpc_mcusys_off_prepare(void) +{ + if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) { + return CPC_ERR_FAIL; + } + + mtk_cpc_cluster_cnt_backup(); + mtk_cpc_mcusys_off_en(); + + return CPC_SUCCESS; +} + +void mtk_cpc_core_on_hint_set(unsigned int cpu) +{ + mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu)); +} + +void mtk_cpc_core_on_hint_clr(unsigned int cpu) +{ + mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu)); +} + +static void mtk_cpc_dump_timestamp(void) +{ + uint32_t id; + + for (id = 0U; id < CPC_TRACE_ID_NUM; id++) { + mmio_write_32(CPC_MCUSYS_TRACE_SEL, id); + + memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id), + (const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA, + CPC_TRACE_SIZE); + } +} + +void mtk_cpc_time_sync(void) +{ + uint64_t kt; + uint32_t systime_l, systime_h; + + kt = sched_clock(); + systime_l = mmio_read_32(CNTSYS_L_REG); + systime_h = mmio_read_32(CNTSYS_H_REG); + + /* sync kernel timer to cpc */ + mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt); + mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32)); + /* sync system timer to cpc */ + mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l); + mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h); +} + +static void mtk_cpc_config(uint32_t cfg, uint32_t data) +{ + uint32_t val; + uint32_t reg = 0U; + + switch (cfg) { + case CPC_SMC_CONFIG_PROF: + reg = CPC_MCUSYS_CPC_DBG_SETTING; + val = mmio_read_32(reg); + val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN); + break; + case CPC_SMC_CONFIG_AUTO_OFF: + reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG; + val = mmio_read_32(reg); + if (data != 0U) { + val |= CPC_AUTO_OFF_EN; + cpc.auto_off = 1; + } else { + val &= ~CPC_AUTO_OFF_EN; + cpc.auto_off = 0; + } + break; + case CPC_SMC_CONFIG_AUTO_OFF_THRES: + reg = CPC_MCUSYS_CPC_OFF_THRES; + cpc.auto_thres_tick = us_to_ticks(data); + val = cpc.auto_thres_tick; + break; + case CPC_SMC_CONFIG_CNT_CLR: + reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR; + val = GENMASK(1, 0); /* clr_mask */ + break; + case CPC_SMC_CONFIG_TIME_SYNC: + mtk_cpc_time_sync(); + break; + default: + break; + } + + if (reg != 0U) { + mmio_write_32(reg, val); + } +} + +static uint32_t mtk_cpc_read_config(uint32_t cfg) +{ + uint32_t res = 0U; + + switch (cfg) { + case CPC_SMC_CONFIG_PROF: + res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? + 1U : 0U; + break; + case CPC_SMC_CONFIG_AUTO_OFF: + res = cpc.auto_off; + break; + case CPC_SMC_CONFIG_AUTO_OFF_THRES: + res = ticks_to_us(cpc.auto_thres_tick); + break; + case CPC_SMC_CONFIG_CNT_CLR: + break; + default: + break; + } + + return res; +} + +uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2) +{ + uint64_t res = 0ULL; + + switch (act) { + case CPC_SMC_EVENT_DUMP_TRACE_DATA: + mtk_cpc_dump_timestamp(); + break; + case CPC_SMC_EVENT_GIC_DPG_SET: + /* isolated_status = x2; */ + break; + case CPC_SMC_EVENT_CPC_CONFIG: + mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2); + break; + case CPC_SMC_EVENT_READ_CONFIG: + res = mtk_cpc_read_config((uint32_t)arg1); + break; + default: + break; + } + + return res; +} + +void mtk_cpc_init(void) +{ + mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING, + mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) + | CPC_DBG_EN + | CPC_CALC_EN); + + cpc.auto_off = 1; + cpc.auto_thres_tick = us_to_ticks(8000); + + mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, + mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG) + | CPC_OFF_PRE_EN + | (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U)); + + mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick); +} diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h new file mode 100644 index 0000000..19dd6a2 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_CPU_PM_CPC_H +#define MT_CPU_PM_CPC_H + +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <mcucfg.h> +#include <platform_def.h> + +#define NEED_CPUSYS_PROT_WORKAROUND 1 + +/* system sram registers */ +#define CPUIDLE_SRAM_REG(r) (uint32_t)(MTK_MCDI_SRAM_BASE + (r)) + +/* db dump */ +#define CPC_TRACE_SIZE U(0x20) +#define CPC_TRACE_ID_NUM U(10) +#define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE) + +/* buckup off count */ +#define CPC_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1F0) +#define CPC_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1F4) + +/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0xA814): debug setting */ +#define CPC_PWR_ON_SEQ_DIS BIT(1) +#define CPC_PWR_ON_PRIORITY BIT(2) +#define CPC_AUTO_OFF_EN BIT(5) +#define CPC_DORMANT_WAIT_EN BIT(14) +#define CPC_CTRL_EN BIT(16) +#define CPC_OFF_PRE_EN BIT(29) + +/* CPC_MCUSYS_LAST_CORE_REQ(0xA818) : last core protection */ +#define CPUSYS_PROT_SET BIT(0) +#define MCUSYS_PROT_SET BIT(8) +#define CPUSYS_PROT_CLR BIT(8) +#define MCUSYS_PROT_CLR BIT(9) + +#define CPC_PROT_RESP_MASK U(0x3) +#define CPUSYS_RESP_OFS U(16) +#define MCUSYS_RESP_OFS U(30) + +#define cpusys_resp(r) (((r) >> CPUSYS_RESP_OFS) & CPC_PROT_RESP_MASK) +#define mcusys_resp(r) (((r) >> MCUSYS_RESP_OFS) & CPC_PROT_RESP_MASK) + +#define RETRY_CNT_MAX U(1000) + +#define PROT_RETRY U(0) +#define PROT_SUCCESS U(1) +#define PROT_GIVEUP U(2) + +/* CPC_MCUSYS_CPC_DBG_SETTING(0xAB00): debug setting */ +#define CPC_PROF_EN BIT(0) +#define CPC_DBG_EN BIT(1) +#define CPC_FREEZE BIT(2) +#define CPC_CALC_EN BIT(3) + +enum { + CPC_SUCCESS = 0, + + CPC_ERR_FAIL, + CPC_ERR_TIMEOUT, + + NF_CPC_ERR +}; + +enum { + CPC_SMC_EVENT_DUMP_TRACE_DATA, + CPC_SMC_EVENT_GIC_DPG_SET, + CPC_SMC_EVENT_CPC_CONFIG, + CPC_SMC_EVENT_READ_CONFIG, + + NF_CPC_SMC_EVENT +}; + +enum { + CPC_SMC_CONFIG_PROF, + CPC_SMC_CONFIG_AUTO_OFF, + CPC_SMC_CONFIG_AUTO_OFF_THRES, + CPC_SMC_CONFIG_CNT_CLR, + CPC_SMC_CONFIG_TIME_SYNC, + + NF_CPC_SMC_CONFIG +}; + +#define us_to_ticks(us) ((us) * 13) +#define ticks_to_us(tick) ((tick) / 13) + +int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster); +void mtk_cpu_pm_cluster_prot_release(unsigned int cluster); + +void mtk_cpc_mcusys_off_reflect(void); +int mtk_cpc_mcusys_off_prepare(void); + +void mtk_cpc_core_on_hint_set(unsigned int cpu); +void mtk_cpc_core_on_hint_clr(unsigned int cpu); +void mtk_cpc_time_sync(void); + +uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2); +void mtk_cpc_init(void); + +#endif /* MT_CPU_PM_CPC_H */ diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c new file mode 100644 index 0000000..872f4d0 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <mt_cirq.h> +#include <mt_lp_irqremain.h> +#include <mt_lp_rm.h> +#include <plat_mtk_lpm.h> + +#define EDMA0_IRQ_ID U(448) +#define MDLA_IRQ_ID U(446) +#define MALI4_IRQ_ID U(399) +#define MALI3_IRQ_ID U(398) +#define MALI2_IRQ_ID U(397) +#define MALI1_IRQ_ID U(396) +#define MALI0_IRQ_ID U(395) +#define VPU_CORE1_IRQ_ID U(453) +#define VPU_CORE0_IRQ_ID U(452) +#define MD_WDT_IRQ_ID U(110) +#define KEYPAD_IRQ_ID U(106) + +#define MD_WDT_WAKESRC 0x2000000 +#define KEYPAD_WAKESRC 0x4 + +static struct mt_irqremain remain_irqs; + +int mt_lp_irqremain_submit(void) +{ + if (remain_irqs.count == 0) { + return -1; + } + + set_wakeup_sources(remain_irqs.irqs, remain_irqs.count); + mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs); + + return 0; +} + +int mt_lp_irqremain_aquire(void) +{ + if (remain_irqs.count == 0) { + return -1; + } + + mt_cirq_sw_reset(); + mt_cirq_clone_gic(); + mt_cirq_enable(); + + return 0; +} + +int mt_lp_irqremain_release(void) +{ + if (remain_irqs.count == 0) { + return -1; + } + + mt_cirq_flush(); + mt_cirq_disable(); + + return 0; +} + +void mt_lp_irqremain_init(void) +{ + uint32_t idx; + + remain_irqs.count = 0; + + /* level edma0 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = EDMA0_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level mdla */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = MDLA_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level mali4 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = MALI4_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level mali3 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = MALI3_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level mali2 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = MALI2_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level mali1 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = MALI1_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level mali0 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = MALI0_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level vpu core1 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = VPU_CORE1_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* level vpu core0 */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = VPU_CORE0_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = 0; + remain_irqs.count++; + + /* edge mdwdt */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = MD_WDT_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = MD_WDT_WAKESRC; + remain_irqs.count++; + + /* edge keypad */ + idx = remain_irqs.count; + remain_irqs.irqs[idx] = KEYPAD_IRQ_ID; + remain_irqs.wakeupsrc_cat[idx] = 0; + remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC; + remain_irqs.count++; + + mt_lp_irqremain_submit(); +} diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.h b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.h new file mode 100644 index 0000000..cbed967 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_LP_IRQREMAIN_H +#define MT_LP_IRQREMAIN_H + +extern int mt_lp_irqremain_submit(void); +extern int mt_lp_irqremain_aquire(void); +extern int mt_lp_irqremain_release(void); +extern void mt_lp_irqremain_init(void); +#endif /* MT_LP_IRQREMAIN_H */ diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c new file mode 100644 index 0000000..1635b67 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <cdefs.h> +#include <common/debug.h> + +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <mt_mcdi.h> + +/* Read/Write */ +#define APMCU_MCUPM_MBOX_AP_READY U(0) +#define APMCU_MCUPM_MBOX_RESERVED_1 U(1) +#define APMCU_MCUPM_MBOX_RESERVED_2 U(2) +#define APMCU_MCUPM_MBOX_RESERVED_3 U(3) +#define APMCU_MCUPM_MBOX_PWR_CTRL_EN U(4) +#define APMCU_MCUPM_MBOX_L3_CACHE_MODE U(5) +#define APMCU_MCUPM_MBOX_BUCK_MODE U(6) +#define APMCU_MCUPM_MBOX_ARMPLL_MODE U(7) +/* Read only */ +#define APMCU_MCUPM_MBOX_TASK_STA U(8) +#define APMCU_MCUPM_MBOX_RESERVED_9 U(9) +#define APMCU_MCUPM_MBOX_RESERVED_10 U(10) +#define APMCU_MCUPM_MBOX_RESERVED_11 U(11) + +/* CPC mode - Read/Write */ +#define APMCU_MCUPM_MBOX_WAKEUP_CPU U(12) + +/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN */ +#define MCUPM_MCUSYS_CTRL BIT(0) +#define MCUPM_BUCK_CTRL BIT(1) +#define MCUPM_ARMPLL_CTRL BIT(2) +#define MCUPM_CM_CTRL BIT(3) +#define MCUPM_PWR_CTRL_MASK GENMASK(3, 0) + +/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE */ +#define MCUPM_BUCK_NORMAL_MODE U(0) /* default */ +#define MCUPM_BUCK_LP_MODE U(1) +#define MCUPM_BUCK_OFF_MODE U(2) +#define NF_MCUPM_BUCK_MODE U(3) + +/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE */ +#define MCUPM_ARMPLL_ON U(0) /* default */ +#define MCUPM_ARMPLL_GATING U(1) +#define MCUPM_ARMPLL_OFF U(2) +#define NF_MCUPM_ARMPLL_MODE U(3) + +/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA */ +#define MCUPM_TASK_UNINIT U(0) +#define MCUPM_TASK_INIT U(1) +#define MCUPM_TASK_INIT_FINISH U(2) +#define MCUPM_TASK_WAIT U(3) +#define MCUPM_TASK_RUN U(4) +#define MCUPM_TASK_PAUSE U(5) + +#define SSPM_MBOX_3_BASE U(0x0c55fce0) + +#define MCDI_NOT_INIT 0 +#define MCDI_INIT_1 1 +#define MCDI_INIT_2 2 +#define MCDI_INIT_DONE 3 + +static int mcdi_init_status __section("tzfw_coherent_mem"); + +static inline uint32_t mcdi_mbox_read(uint32_t id) +{ + return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2)); +} + +static inline void mcdi_mbox_write(uint32_t id, uint32_t val) +{ + mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val); +} + +static void mtk_mcupm_pwr_ctrl_setting(uint32_t dev) +{ + mcdi_mbox_write(APMCU_MCUPM_MBOX_PWR_CTRL_EN, dev); +} + +static void mtk_set_mcupm_pll_mode(uint32_t mode) +{ + if (mode < NF_MCUPM_ARMPLL_MODE) { + mcdi_mbox_write(APMCU_MCUPM_MBOX_ARMPLL_MODE, mode); + } +} + +static void mtk_set_mcupm_buck_mode(uint32_t mode) +{ + if (mode < NF_MCUPM_BUCK_MODE) { + mcdi_mbox_write(APMCU_MCUPM_MBOX_BUCK_MODE, mode); + } +} + +static int mtk_mcupm_is_ready(void) +{ + unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA); + + return (sta == MCUPM_TASK_WAIT) || (sta == MCUPM_TASK_INIT_FINISH); +} + +static int mcdi_init_1(void) +{ + unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA); + + if (sta != MCUPM_TASK_INIT) { + return -1; + } + + mtk_set_mcupm_pll_mode(MCUPM_ARMPLL_OFF); + mtk_set_mcupm_buck_mode(MCUPM_BUCK_OFF_MODE); + + mtk_mcupm_pwr_ctrl_setting( + MCUPM_MCUSYS_CTRL | + MCUPM_BUCK_CTRL | + MCUPM_ARMPLL_CTRL); + + mcdi_mbox_write(APMCU_MCUPM_MBOX_AP_READY, 1); + + return 0; +} + +static int mcdi_init_2(void) +{ + return mtk_mcupm_is_ready() ? 0 : -1; +} + +int mcdi_try_init(void) +{ + if (mcdi_init_status == MCDI_INIT_DONE) { + return 0; + } + + if (mcdi_init_status == MCDI_NOT_INIT) { + mcdi_init_status = MCDI_INIT_1; + } + + if (mcdi_init_status == MCDI_INIT_1 && mcdi_init_1() == 0) { + mcdi_init_status = MCDI_INIT_2; + } + + if (mcdi_init_status == MCDI_INIT_2 && mcdi_init_2() == 0) { + mcdi_init_status = MCDI_INIT_DONE; + } + + INFO("mcdi ready for mcusys-off-idle and system suspend\n"); + + return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status; +} diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h new file mode 100644 index 0000000..f3545aa --- /dev/null +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_MCDI_H +#define MT_MCDI_H + +int mcdi_try_init(void); + +#endif /* MT_MCDI_H */ diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h new file mode 100644 index 0000000..b9ab586 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_WRAP_INIT_H +#define PMIC_WRAP_INIT_H + +#include <stdint.h> + +#include "platform_def.h" +#include <pmic_wrap_init_common.h> + +static struct mt8192_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; + +/* PMIC_WRAP registers */ +struct mt8192_pmic_wrap_regs { + uint32_t init_done; + uint32_t reserved[799]; + uint32_t wacs2_cmd; + uint32_t wacs2_wdata; + uint32_t reserved1[3]; + uint32_t wacs2_rdata; + uint32_t reserved2[3]; + uint32_t wacs2_vldclr; + uint32_t wacs2_sta; +}; + +#endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h new file mode 100644 index 0000000..92c71bc --- /dev/null +++ b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_PTP3_H +#define MTK_PTP3_H + +#include <lib/mmio.h> +#include <lib/utils_def.h> + +/************************************************ + * BIT Operation and REG r/w + ************************************************/ +#define ptp3_read(addr) mmio_read_32((uintptr_t)addr) +#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val) + +/************************************************ + * CPU info + ************************************************/ +#define NR_PTP3_CFG1_CPU U(8) +#define PTP3_CFG1_CPU_START_ID U(0) +#define PTP3_CFG1_MASK 0x00100000 + +#define NR_PTP3_CFG2_CPU U(4) +#define PTP3_CFG2_CPU_START_ID U(4) + +#define NR_PTP3_CFG3_CPU U(4) +#define PTP3_CFG3_CPU_START_ID U(4) + +/************************************************ + * config enum + ************************************************/ +enum PTP3_CFG { + PTP3_CFG_ADDR, + PTP3_CFG_VALUE, + NR_PTP3_CFG, +}; + +/************************************ + * prototype + ************************************/ +/* init trigger for ptp3 feature */ +extern void ptp3_init(unsigned int core); +extern void ptp3_deinit(unsigned int core); + +#endif /* MTK_PTP3_H */ diff --git a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c new file mode 100644 index 0000000..f1d8493 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. \ + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "mtk_ptp3_common.h" + +/************************************************ + * Central control: turn on sysPi protection + ************************************************/ +static unsigned int ptp3_cfg1[NR_PTP3_CFG1_CPU][NR_PTP3_CFG] = { + {0x0C530610, 0x110842}, + {0x0C530E10, 0x110842}, + {0x0C531610, 0x110842}, + {0x0C531E10, 0x110842}, + {0x0C532610, 0x110842}, + {0x0C532E10, 0x110842}, + {0x0C533610, 0x110842}, + {0x0C533E10, 0x110842} +}; +static unsigned int ptp3_cfg2[NR_PTP3_CFG2_CPU][NR_PTP3_CFG] = { + {0x0C53B830, 0x68000}, + {0x0C53BA30, 0x68000}, + {0x0C53BC30, 0x68000}, + {0x0C53BE30, 0x68000} +}; +static unsigned int ptp3_cfg3[NR_PTP3_CFG3_CPU][NR_PTP3_CFG] = { + {0x0C532480, 0x7C607C6}, + {0x0C532C80, 0x7C607C6}, + {0x0C533480, 0x7C607C6}, + {0x0C533C80, 0x7C607C6} +}; + +/************************************************ + * API + ************************************************/ +void ptp3_init(unsigned int core) +{ + unsigned int _core; + + /* Apply ptp3_cfg1 for core 0 to 7 */ + if (core < NR_PTP3_CFG1_CPU) { + /* update ptp3_cfg1 */ + ptp3_write( + ptp3_cfg1[core][PTP3_CFG_ADDR], + ptp3_cfg1[core][PTP3_CFG_VALUE]); + } + + /* Apply ptp3_cfg2 for core 4 to 7 */ + if (core >= PTP3_CFG2_CPU_START_ID) { + _core = core - PTP3_CFG2_CPU_START_ID; + + if (_core < NR_PTP3_CFG2_CPU) { + /* update ptp3_cfg2 */ + ptp3_write( + ptp3_cfg2[_core][PTP3_CFG_ADDR], + ptp3_cfg2[_core][PTP3_CFG_VALUE]); + } + } + + /* Apply ptp3_cfg3 for core 4 to 7 */ + if (core >= PTP3_CFG3_CPU_START_ID) { + _core = core - PTP3_CFG3_CPU_START_ID; + + if (_core < NR_PTP3_CFG3_CPU) { + /* update ptp3_cfg3 */ + ptp3_write( + ptp3_cfg3[_core][PTP3_CFG_ADDR], + ptp3_cfg3[_core][PTP3_CFG_VALUE]); + } + } +} + +void ptp3_deinit(unsigned int core) +{ + if (core < NR_PTP3_CFG1_CPU) { + /* update ptp3_cfg1 */ + ptp3_write( + ptp3_cfg1[core][PTP3_CFG_ADDR], + ptp3_cfg1[core][PTP3_CFG_VALUE] & + ~PTP3_CFG1_MASK); + } +} diff --git a/plat/mediatek/mt8192/drivers/spm/build.mk b/plat/mediatek/mt8192/drivers/spm/build.mk new file mode 100644 index 0000000..4153603 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/build.mk @@ -0,0 +1,68 @@ +# +# Copyright (c) 2020, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Enable or disable spm feature +MT_SPM_FEATURE_SUPPORT = yes + +# Enable or disable cirq restore +MT_SPM_CIRQ_FEATURE_SUPPORT = yes + +# sspm notifier support +MT_SPM_SSPM_NOTIFIER_SUPPORT = yes + +CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm + +# spm common files +PLAT_SPM_SOURCE_FILES_COMMON += \ + ${CUR_SPM_FOLDER}/mt_spm.c \ + ${CUR_SPM_FOLDER}/mt_spm_conservation.c \ + ${CUR_SPM_FOLDER}/mt_spm_internal.c \ + ${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c \ + ${CUR_SPM_FOLDER}/mt_spm_vcorefs.c + +# spm platform dependcy files +PLAT_SPM_SOURCE_FILES += \ + ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c \ + ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c \ + ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c \ + ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c \ + ${CUR_SPM_FOLDER}/mt_spm_cond.c \ + ${CUR_SPM_FOLDER}/mt_spm_suspend.c \ + ${CUR_SPM_FOLDER}/mt_spm_idle.c + +ifeq (${MT_SPM_FEATURE_SUPPORT}, no) +PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT +BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON} +else +BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \ + ${PLAT_SPM_SOURCE_FILES_COMMON} \ + ${PLAT_SPM_SOURCE_FILES} +endif + +ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no) +PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT +endif + +ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no) +PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT +else +BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \ + ${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c +endif + +$(info --------------------------------------) +$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS}) +$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}) +$(info --------------------------------------) + +# Common makefile for platform.mk +PLAT_INCLUDES += \ + ${PLAT_SPM_DEBUG_CFLAGS} \ + -I${CUR_SPM_FOLDER}/ \ + -I${CUR_SPM_FOLDER}/constraints/ \ + -I${CUR_SPM_FOLDER}/notifier/ + +PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES} diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c new file mode 100644 index 0000000..18c43b1 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <common/debug.h> + +#include <mt_lp_rm.h> +#include <mt_spm.h> +#include <mt_spm_cond.h> +#include <mt_spm_constraint.h> +#include <mt_spm_conservation.h> +#include <mt_spm_idle.h> +#include <mt_spm_internal.h> +#include <mt_spm_notifier.h> +#include <mt_spm_rc_internal.h> +#include <mt_spm_resource_req.h> +#include <mt_spm_reg.h> +#include <mt_spm_suspend.h> +#include <plat_pm.h> +#include <plat_mtk_lpm.h> + +#ifndef ATF_PLAT_CIRQ_UNSUPPORT +#include <mt_cirq.h> +#include <mt_gic_v3.h> +#endif + +#define CONSTRAINT_BUS26M_ALLOW \ + (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \ + MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \ + MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \ + MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \ + MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \ + MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF) + +#define CONSTRAINT_BUS26M_PCM_FLAG \ + (SPM_FLAG_DISABLE_INFRA_PDN | \ + SPM_FLAG_DISABLE_VCORE_DVS | \ + SPM_FLAG_DISABLE_VCORE_DFS | \ + SPM_FLAG_SRAM_SLEEP_CTRL | \ + SPM_FLAG_ENABLE_TIA_WORKAROUND | \ + SPM_FLAG_ENABLE_LVTS_WORKAROUND | \ + SPM_FLAG_KEEP_CSYSPWRACK_HIGH) + +#define CONSTRAINT_BUS26M_PCM_FLAG1 \ + (SPM_FLAG1_DISABLE_MD26M_CK_OFF) + +#define CONSTRAINT_BUS26M_RESOURCE_REQ 0U + +static unsigned int bus26m_ext_opand; +static struct mt_irqremain *refer2remain_irq; +static struct mt_spm_cond_tables cond_bus26m = { + .name = "bus26m", + .table_cg = { + 0x07CBF1FC, /* MTCMOS1 */ + 0x0A0D8856, /* INFRA0 */ + 0x03AF9A00, /* INFRA1 */ + 0x86000650, /* INFRA2 */ + 0xC800C000, /* INFRA3 */ + 0x00000000, /* INFRA4 */ + 0x4000007C, /* INFRA5 */ + 0x280E0800, /* MMSYS0 */ + 0x00000001, /* MMSYS1 */ + 0x00000000, /* MMSYS2 */ + }, + .table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL | + PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL | + PLL_BIT_MMPLL), +}; + +static struct mt_spm_cond_tables cond_bus26m_res = { + .table_cg = { 0U }, + .table_pll = 0U, +}; + +static struct constraint_status status = { + .id = MT_RM_CONSTRAINT_ID_BUS26M, + .valid = (MT_SPM_RC_VALID_SW | + MT_SPM_RC_VALID_COND_LATCH), + .cond_block = 0U, + .enter_cnt = 0U, + .cond_res = &cond_bus26m_res, +}; + +/* + * Cirq will take the place of gic when gic is off. + * However, cirq cannot work if 26m clk is turned off when system idle/suspend. + * Therefore, we need to set irq pending for specific wakeup source. + */ +#ifdef ATF_PLAT_CIRQ_UNSUPPORT +#define do_irqs_delivery() +#else +static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs, + unsigned int irq_index, + struct wake_status *wakeup) +{ + INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n", + wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta, + wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0, + wakeup->tr.comm.b_sw_flag1); + + INFO("irq:%u(0x%08x) set pending\n", + irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]); +} + +static void do_irqs_delivery(void) +{ + unsigned int idx; + int res = 0; + struct wake_status *wakeup = NULL; + struct mt_irqremain *irqs = refer2remain_irq; + + res = spm_conservation_get_result(&wakeup); + + if ((res != 0) && (irqs == NULL)) { + return; + } + + for (idx = 0U; idx < irqs->count; ++idx) { + if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) || + ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) { + if ((irqs->wakeupsrc_cat[idx] & + MT_IRQ_REMAIN_CAT_LOG) != 0U) { + mt_spm_irq_remain_dump(irqs, idx, wakeup); + } + + mt_irq_set_pending(irqs->irqs[idx]); + } + } +} +#endif + +static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp, + unsigned int *resource_req) +{ + spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG; + spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1; + *resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ; +} + +bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id) +{ + (void)cpu; + (void)state_id; + + return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid); +} + +int spm_update_rc_bus26m(int state_id, int type, const void *val) +{ + const struct mt_spm_cond_tables *tlb; + const struct mt_spm_cond_tables *tlb_check; + int res = MT_RM_STATUS_OK; + + if (val == NULL) { + return MT_RM_STATUS_BAD; + } + + if (type == PLAT_RC_UPDATE_CONDITION) { + tlb = (const struct mt_spm_cond_tables *)val; + tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m; + + status.cond_block = + mt_spm_cond_check(state_id, tlb, tlb_check, + ((status.valid & + MT_SPM_RC_VALID_COND_LATCH) != 0U) ? + &cond_bus26m_res : NULL); + } else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) { + refer2remain_irq = (struct mt_irqremain *)val; + } else { + res = MT_RM_STATUS_BAD; + } + + return res; +} + +unsigned int spm_allow_rc_bus26m(int state_id) +{ + (void)state_id; + + return CONSTRAINT_BUS26M_ALLOW; +} + +int spm_run_rc_bus26m(unsigned int cpu, int state_id) +{ + (void)cpu; + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW | + (IS_PLAT_SUSPEND_ID(state_id) ? + MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U)); +#endif + if (IS_PLAT_SUSPEND_ID(state_id)) { + mt_spm_suspend_enter(state_id, + (MT_SPM_EX_OP_SET_WDT | + MT_SPM_EX_OP_HW_S1_DETECT | + bus26m_ext_opand), + CONSTRAINT_BUS26M_RESOURCE_REQ); + } else { + mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT, + spm_bus26m_conduct); + } + + return 0; +} + +int spm_reset_rc_bus26m(unsigned int cpu, int state_id) +{ + unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; + + (void)cpu; + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U); +#endif + if (IS_PLAT_SUSPEND_ID(state_id)) { + ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT); + mt_spm_suspend_resume(state_id, ext_op, NULL); + bus26m_ext_opand = 0U; + } else { + mt_spm_idle_generic_resume(state_id, ext_op, NULL); + status.enter_cnt++; + } + + do_irqs_delivery(); + + return 0; +} diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c new file mode 100644 index 0000000..9618f3b --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <common/debug.h> + +#include <mt_spm.h> +#include <mt_spm_cond.h> +#include <mt_spm_constraint.h> +#include <mt_spm_conservation.h> +#include <mt_spm_idle.h> +#include <mt_spm_internal.h> +#include <mt_spm_notifier.h> +#include <mt_spm_rc_internal.h> +#include <mt_spm_resource_req.h> +#include <mt_spm_reg.h> +#include <mt_spm_suspend.h> +#include <plat_pm.h> + +#define CONSTRAINT_CPU_BUCK_PCM_FLAG \ + (SPM_FLAG_DISABLE_INFRA_PDN | \ + SPM_FLAG_DISABLE_VCORE_DVS | \ + SPM_FLAG_DISABLE_VCORE_DFS | \ + SPM_FLAG_SRAM_SLEEP_CTRL | \ + SPM_FLAG_KEEP_CSYSPWRACK_HIGH) + +#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 0U + +#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ \ + (MT_SPM_DRAM_S1 | \ + MT_SPM_DRAM_S0 | \ + MT_SPM_SYSPLL | \ + MT_SPM_INFRA | \ + MT_SPM_26M | \ + MT_SPM_XO_FPM) + + +static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW; +static unsigned int cpubuckldo_enter_cnt; + +static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp, + unsigned int *resource_req) +{ + spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG; + spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1; + *resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ; +} + +bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id) +{ + (void)cpu; + (void)state_id; + + return IS_MT_RM_RC_READY(cpubuckldo_status); +} + +unsigned int spm_allow_rc_cpu_buck_ldo(int state_id) +{ + (void)state_id; + + return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF; +} + +int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id) +{ + (void)cpu; + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, + (IS_PLAT_SUSPEND_ID(state_id) ? + MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U)); +#endif + if (IS_PLAT_SUSPEND_ID(state_id)) { + mt_spm_suspend_enter(state_id, + MT_SPM_EX_OP_SET_WDT, + CONSTRAINT_CPU_BUCK_RESOURCE_REQ); + } else { + mt_spm_idle_generic_enter(state_id, 0U, + spm_cpu_bcuk_ldo_conduct); + } + + cpubuckldo_enter_cnt++; + + return 0; +} + +int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id) +{ + (void)cpu; + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U); +#endif + if (IS_PLAT_SUSPEND_ID(state_id)) { + mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL); + } else { + mt_spm_idle_generic_resume(state_id, 0U, NULL); + } + + return 0; +} diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c new file mode 100644 index 0000000..34293c4 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <common/debug.h> + +#include <mt_lp_rm.h> +#include <mt_spm.h> +#include <mt_spm_cond.h> +#include <mt_spm_constraint.h> +#include <mt_spm_conservation.h> +#include <mt_spm_idle.h> +#include <mt_spm_internal.h> +#include <mt_spm_notifier.h> +#include <mt_spm_resource_req.h> +#include <mt_spm_reg.h> +#include <mt_spm_rc_internal.h> +#include <mt_spm_suspend.h> +#include <plat_pm.h> +#include <plat_mtk_lpm.h> + +#define CONSTRAINT_DRAM_ALLOW \ + (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \ + MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \ + MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF) + +#define CONSTRAINT_DRAM_PCM_FLAG \ + (SPM_FLAG_DISABLE_INFRA_PDN | \ + SPM_FLAG_DISABLE_VCORE_DVS | \ + SPM_FLAG_DISABLE_VCORE_DFS | \ + SPM_FLAG_SRAM_SLEEP_CTRL | \ + SPM_FLAG_KEEP_CSYSPWRACK_HIGH) + +#define CONSTRAINT_DRAM_PCM_FLAG1 0U + +#define CONSTRAINT_DRAM_RESOURCE_REQ \ + (MT_SPM_SYSPLL | \ + MT_SPM_INFRA | \ + MT_SPM_26M) + +static struct mt_spm_cond_tables cond_dram = { + .name = "dram", + .table_cg = { + 0x078BF1FC, /* MTCMOS1 */ + 0x080D8856, /* INFRA0 */ + 0x03AF9A00, /* INFRA1 */ + 0x86000640, /* INFRA2 */ + 0xC800C000, /* INFRA3 */ + 0x00000000, /* INFRA4 */ + 0x00000000, /* INFRA5 */ + 0x200C0000, /* MMSYS0 */ + 0x00000000, /* MMSYS1 */ + 0x00000000, /* MMSYS2 */ + }, + .table_pll = 0U, +}; + +static struct mt_spm_cond_tables cond_dram_res = { + .table_cg = { 0U }, + .table_pll = 0U, +}; + +static struct constraint_status status = { + .id = MT_RM_CONSTRAINT_ID_DRAM, + .valid = (MT_SPM_RC_VALID_SW | + MT_SPM_RC_VALID_COND_LATCH | + MT_SPM_RC_VALID_XSOC_BBLPM), + .cond_block = 0U, + .enter_cnt = 0U, + .cond_res = &cond_dram_res, +}; + +static void spm_dram_conduct(struct spm_lp_scen *spm_lp, + unsigned int *resource_req) +{ + spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG; + spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1; + *resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ; +} + +bool spm_is_valid_rc_dram(unsigned int cpu, int state_id) +{ + (void)cpu; + (void)state_id; + + return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid); +} + +int spm_update_rc_dram(int state_id, int type, const void *val) +{ + const struct mt_spm_cond_tables *tlb; + const struct mt_spm_cond_tables *tlb_check; + int res = MT_RM_STATUS_OK; + + if (val == NULL) { + return MT_RM_STATUS_BAD; + } + + if (type == PLAT_RC_UPDATE_CONDITION) { + tlb = (const struct mt_spm_cond_tables *)val; + tlb_check = (const struct mt_spm_cond_tables *)&cond_dram; + status.cond_block = + mt_spm_cond_check(state_id, tlb, tlb_check, + ((status.valid & + MT_SPM_RC_VALID_COND_LATCH) != 0U) ? + &cond_dram_res : NULL); + } else { + res = MT_RM_STATUS_BAD; + } + + return res; +} + +unsigned int spm_allow_rc_dram(int state_id) +{ + (void)state_id; + + return CONSTRAINT_DRAM_ALLOW; +} + +int spm_run_rc_dram(unsigned int cpu, int state_id) +{ + unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; + unsigned int allows = CONSTRAINT_DRAM_ALLOW; + + (void)cpu; + + if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) { +#ifdef MT_SPM_USING_SRCLKEN_RC + ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; +#else + allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; +#endif + } + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | + (IS_PLAT_SUSPEND_ID(state_id) ? + MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U)); +#else + (void)allows; +#endif + + if (IS_PLAT_SUSPEND_ID(state_id)) { + mt_spm_suspend_enter(state_id, + (MT_SPM_EX_OP_SET_WDT | + MT_SPM_EX_OP_HW_S1_DETECT), + CONSTRAINT_DRAM_RESOURCE_REQ); + } else { + mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct); + } + + return 0; +} + +int spm_reset_rc_dram(unsigned int cpu, int state_id) +{ + unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; + unsigned int allows = CONSTRAINT_DRAM_ALLOW; + + (void)cpu; + + if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) { +#ifdef MT_SPM_USING_SRCLKEN_RC + ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; +#else + allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; +#endif + } + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows); +#else + (void)allows; +#endif + + if (IS_PLAT_SUSPEND_ID(state_id)) { + mt_spm_suspend_resume(state_id, + (MT_SPM_EX_OP_SET_WDT | + MT_SPM_EX_OP_HW_S1_DETECT), + NULL); + } else { + mt_spm_idle_generic_resume(state_id, ext_op, NULL); + status.enter_cnt++; + } + + return 0; +} diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h new file mode 100644 index 0000000..aeb778a --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_RC_INTERNAL_H +#define MT_SPM_RC_INTERNAL_H + +#include <stdbool.h> + +#define SPM_FLAG_SRAM_SLEEP_CTRL \ + (SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP | \ + SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \ + SPM_FLAG_DISABLE_SYSRAM_SLEEP | \ + SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP | \ + SPM_FLAG_DISABLE_SRAM_EVENT) + +/* cpu buck/ldo constraint function */ +bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id); +unsigned int spm_allow_rc_cpu_buck_ldo(int state_id); +int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id); +int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id); + +/* spm resource dram constraint function */ +bool spm_is_valid_rc_dram(unsigned int cpu, int state_id); +int spm_update_rc_dram(int state_id, int type, const void *val); +unsigned int spm_allow_rc_dram(int state_id); +int spm_run_rc_dram(unsigned int cpu, int state_id); +int spm_reset_rc_dram(unsigned int cpu, int state_id); + +/* spm resource syspll constraint function */ +bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id); +int spm_update_rc_syspll(int state_id, int type, const void *val); +unsigned int spm_allow_rc_syspll(int state_id); +int spm_run_rc_syspll(unsigned int cpu, int state_id); +int spm_reset_rc_syspll(unsigned int cpu, int state_id); + +/* spm resource bus26m constraint function */ +bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id); +int spm_update_rc_bus26m(int state_id, int type, const void *val); +unsigned int spm_allow_rc_bus26m(int state_id); +int spm_run_rc_bus26m(unsigned int cpu, int state_id); +int spm_reset_rc_bus26m(unsigned int cpu, int state_id); +#endif /* MT_SPM_RC_INTERNAL_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c new file mode 100644 index 0000000..8d76d63 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> + +#include <mt_lp_rm.h> +#include <mt_spm.h> +#include <mt_spm_cond.h> +#include <mt_spm_constraint.h> +#include <mt_spm_conservation.h> +#include <mt_spm_idle.h> +#include <mt_spm_internal.h> +#include <mt_spm_notifier.h> +#include <mt_spm_rc_internal.h> +#include <mt_spm_reg.h> +#include <mt_spm_resource_req.h> +#include <mt_spm_suspend.h> +#include <plat_pm.h> +#include <plat_mtk_lpm.h> + +#define CONSTRAINT_SYSPLL_ALLOW \ + (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \ + MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \ + MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \ + MT_RM_CONSTRAINT_ALLOW_VCORE_LP) + +#define CONSTRAINT_SYSPLL_PCM_FLAG \ + (SPM_FLAG_DISABLE_INFRA_PDN | \ + SPM_FLAG_DISABLE_VCORE_DVS | \ + SPM_FLAG_DISABLE_VCORE_DFS | \ + SPM_FLAG_SRAM_SLEEP_CTRL | \ + SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \ + SPM_FLAG_ENABLE_6315_CTRL | \ + SPM_FLAG_USE_SRCCLKENO2) + +#define CONSTRAINT_SYSPLL_PCM_FLAG1 0U +#define CONSTRAINT_SYSPLL_RESOURCE_REQ \ + (MT_SPM_26M) + +static struct mt_spm_cond_tables cond_syspll = { + .name = "syspll", + .table_cg = { + 0x078BF1FC, /* MTCMOS1 */ + 0x080D8856, /* INFRA0 */ + 0x03AF9A00, /* INFRA1 */ + 0x86000640, /* INFRA2 */ + 0xC800C000, /* INFRA3 */ + 0x00000000, /* INFRA4 */ + 0x0000007C, /* INFRA5 */ + 0x280E0800, /* MMSYS0 */ + 0x00000001, /* MMSYS1 */ + 0x00000000, /* MMSYS2 */ + }, + .table_pll = 0U, +}; + +static struct mt_spm_cond_tables cond_syspll_res = { + .table_cg = { 0U }, + .table_pll = 0U, +}; + +static struct constraint_status status = { + .id = MT_RM_CONSTRAINT_ID_SYSPLL, + .valid = (MT_SPM_RC_VALID_SW | + MT_SPM_RC_VALID_COND_LATCH | + MT_SPM_RC_VALID_XSOC_BBLPM), + .cond_block = 0U, + .enter_cnt = 0U, + .cond_res = &cond_syspll_res, +}; + +static void spm_syspll_conduct(struct spm_lp_scen *spm_lp, + unsigned int *resource_req) +{ + spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG; + spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1; + *resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ; +} + +bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id) +{ + (void)cpu; + (void)state_id; + + return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid); +} + +int spm_update_rc_syspll(int state_id, int type, const void *val) +{ + const struct mt_spm_cond_tables *tlb; + const struct mt_spm_cond_tables *tlb_check; + int res = MT_RM_STATUS_OK; + + if (val == NULL) { + return MT_RM_STATUS_BAD; + } + + if (type == PLAT_RC_UPDATE_CONDITION) { + tlb = (const struct mt_spm_cond_tables *)val; + tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll; + + status.cond_block = + mt_spm_cond_check(state_id, tlb, tlb_check, + ((status.valid & + MT_SPM_RC_VALID_COND_LATCH) != 0U) ? + &cond_syspll_res : NULL); + } else { + res = MT_RM_STATUS_BAD; + } + + return res; +} + +unsigned int spm_allow_rc_syspll(int state_id) +{ + (void)state_id; + + return CONSTRAINT_SYSPLL_ALLOW; +} + +int spm_run_rc_syspll(unsigned int cpu, int state_id) +{ + unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; + unsigned int allows = CONSTRAINT_SYSPLL_ALLOW; + + (void)cpu; + + if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) { +#ifdef MT_SPM_USING_SRCLKEN_RC + ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; +#else + allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; +#endif + } + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | + (IS_PLAT_SUSPEND_ID(state_id) ? + MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U)); +#else + (void)allows; +#endif + + if (IS_PLAT_SUSPEND_ID(state_id)) { + mt_spm_suspend_enter(state_id, + (MT_SPM_EX_OP_SET_WDT | + MT_SPM_EX_OP_HW_S1_DETECT | + MT_SPM_EX_OP_SET_SUSPEND_MODE), + CONSTRAINT_SYSPLL_RESOURCE_REQ); + } else { + mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct); + } + + return 0; +} + +int spm_reset_rc_syspll(unsigned int cpu, int state_id) +{ + unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; + unsigned int allows = CONSTRAINT_SYSPLL_ALLOW; + + (void)cpu; + + if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) { +#ifdef MT_SPM_USING_SRCLKEN_RC + ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; +#else + allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; +#endif + } + +#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT + mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows); +#else + (void)allows; +#endif + if (IS_PLAT_SUSPEND_ID(state_id)) { + mt_spm_suspend_resume(state_id, + (MT_SPM_EX_OP_SET_SUSPEND_MODE | + MT_SPM_EX_OP_SET_WDT | + MT_SPM_EX_OP_HW_S1_DETECT), + NULL); + } else { + mt_spm_idle_generic_resume(state_id, ext_op, NULL); + status.enter_cnt++; + } + + return 0; +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm.c b/plat/mediatek/mt8192/drivers/spm/mt_spm.c new file mode 100644 index 0000000..f4505b6 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stddef.h> +#include <string.h> +#include <common/debug.h> +#include <lib/bakery_lock.h> +#include <lib/mmio.h> +#include <mt_lp_rm.h> +#include <mt_spm.h> +#include <mt_spm_cond.h> +#include <mt_spm_conservation.h> +#include <mt_spm_constraint.h> +#include <mt_spm_idle.h> +#include <mt_spm_internal.h> +#include <mt_spm_pmic_wrap.h> +#include <mt_spm_rc_internal.h> +#include <mt_spm_reg.h> +#include <mt_spm_resource_req.h> +#include <mt_spm_suspend.h> +#include <mtk_plat_common.h> +#include <plat_mtk_lpm.h> +#include <plat_pm.h> +#include <platform_def.h> +#include <sleep_def.h> + +#ifdef MT_SPM_USING_BAKERY_LOCK +DEFINE_BAKERY_LOCK(spm_lock); +#define plat_spm_lock_init() bakery_lock_init(&spm_lock) +#else +spinlock_t spm_lock; +#define plat_spm_lock_init() +#endif + +/* CLK_SCP_CFG_0 */ +#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200) +#define SPM_CK_CONTROL_EN 0x3FF + +/* CLK_SCP_CFG_1 */ +#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x210) +#define CLK_SCP_CFG_1_MASK 0x100C +#define CLK_SCP_CFG_1_SPM 0x3 + +struct mt_resource_constraint plat_constraint_bus26m = { + .is_valid = spm_is_valid_rc_bus26m, + .update = spm_update_rc_bus26m, + .allow = spm_allow_rc_bus26m, + .run = spm_run_rc_bus26m, + .reset = spm_reset_rc_bus26m, +}; + +struct mt_resource_constraint plat_constraint_syspll = { + .is_valid = spm_is_valid_rc_syspll, + .update = spm_update_rc_syspll, + .allow = spm_allow_rc_syspll, + .run = spm_run_rc_syspll, + .reset = spm_reset_rc_syspll, +}; + +struct mt_resource_constraint plat_constraint_dram = { + .is_valid = spm_is_valid_rc_dram, + .update = spm_update_rc_dram, + .allow = spm_allow_rc_dram, + .run = spm_run_rc_dram, + .reset = spm_reset_rc_dram, +}; + +struct mt_resource_constraint plat_constraint_cpu = { + .is_valid = spm_is_valid_rc_cpu_buck_ldo, + .update = NULL, + .allow = spm_allow_rc_cpu_buck_ldo, + .run = spm_run_rc_cpu_buck_ldo, + .reset = spm_reset_rc_cpu_buck_ldo, +}; + +struct mt_resource_constraint *plat_constraints[] = { + &plat_constraint_bus26m, + &plat_constraint_syspll, + &plat_constraint_dram, + &plat_constraint_cpu, + NULL, +}; + +struct mt_resource_manager plat_mt8192_rm = { + .update = mt_spm_cond_update, + .consts = plat_constraints, +}; + +void spm_boot_init(void) +{ + /* switch ck_off/axi_26m control to SPM */ + mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN); + mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK, + CLK_SCP_CFG_1_SPM); + + plat_spm_lock_init(); + mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); + mt_lp_rm_register(&plat_mt8192_rm); + mt_spm_idle_generic_init(); + mt_spm_suspend_init(); +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm.h b/plat/mediatek/mt8192/drivers/spm/mt_spm.h new file mode 100644 index 0000000..b147fe2 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_H +#define MT_SPM_H + +#include <lib/bakery_lock.h> +#include <lib/spinlock.h> + +#include <plat_mtk_lpm.h> + +/* + * ARM v8.2, the cache will turn off automatically when cpu + * power down. So, there is no doubt to use the spin_lock here + */ +#if !HW_ASSISTED_COHERENCY +#define MT_SPM_USING_BAKERY_LOCK +#endif + +#ifdef MT_SPM_USING_BAKERY_LOCK +DECLARE_BAKERY_LOCK(spm_lock); +#define plat_spm_lock() bakery_lock_get(&spm_lock) +#define plat_spm_unlock() bakery_lock_release(&spm_lock) +#else +extern spinlock_t spm_lock; +#define plat_spm_lock() spin_lock(&spm_lock) +#define plat_spm_unlock() spin_unlock(&spm_lock) +#endif + +#define MT_SPM_USING_SRCLKEN_RC + +/* spm extern operand definition */ +#define MT_SPM_EX_OP_CLR_26M_RECORD (1U << 0) +#define MT_SPM_EX_OP_SET_WDT (1U << 1) +#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ (1U << 2) +#define MT_SPM_EX_OP_SET_SUSPEND_MODE (1U << 3) +#define MT_SPM_EX_OP_SET_IS_ADSP (1U << 4) +#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM (1U << 5) +#define MT_SPM_EX_OP_HW_S1_DETECT (1U << 6) + +typedef enum { + WR_NONE = 0, + WR_UART_BUSY = 1, + WR_ABORT = 2, + WR_PCM_TIMER = 3, + WR_WAKE_SRC = 4, + WR_DVFSRC = 5, + WR_TWAM = 6, + WR_PMSR = 7, + WR_SPM_ACK_CHK = 8, + WR_UNKNOWN = 9, +} wake_reason_t; + +static inline void spm_lock_get(void) +{ + plat_spm_lock(); +} + +static inline void spm_lock_release(void) +{ + plat_spm_unlock(); +} + +extern void spm_boot_init(void); +#endif /* MT_SPM_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c new file mode 100644 index 0000000..2d67fdf --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> + +#include <common/debug.h> +#include <lib/mmio.h> + +#include <mt_spm_cond.h> +#include <mt_spm_conservation.h> +#include <mt_spm_constraint.h> +#include <plat_mtk_lpm.h> +#include <plat_pm.h> +#include <platform_def.h> + +#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs) +#define MT_LP_TZ_MM_REG(ofs) (MMSYS_BASE + ofs) +#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs) +#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEN_BASE + ofs) +#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs) + +#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C) +#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170) +#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0094) +#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0090) +#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC) +#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8) +#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00D8) +#define INFRA_SW_CG5 MT_LP_TZ_INFRA_REG(0x00E8) +#define MMSYS_CG_CON0 MT_LP_TZ_MM_REG(0x100) +#define MMSYS_CG_CON1 MT_LP_TZ_MM_REG(0x110) +#define MMSYS_CG_CON2 MT_LP_TZ_MM_REG(0x1A0) + +/*********************************************************** + * Check clkmux registers + ***********************************************************/ +#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x20 + id * 0x10) +#define PDN_CHECK BIT(7) +#define CLK_CHECK BIT(31) + +enum { + CLKMUX_DISP = 0, + CLKMUX_MDP = 1, + CLKMUX_IMG1 = 2, + CLKMUX_IMG2 = 3, + NF_CLKMUX, +}; + +static bool is_clkmux_pdn(unsigned int clkmux_id) +{ + unsigned int reg, val, idx; + + if ((clkmux_id & CLK_CHECK) != 0U) { + clkmux_id = (clkmux_id & ~CLK_CHECK); + reg = clkmux_id / 4U; + val = mmio_read_32(CLK_CFG(reg)); + idx = clkmux_id % 4U; + val = (val >> (idx * 8U)) & PDN_CHECK; + return (val != 0U); + } + + return false; +} + +static struct mt_spm_cond_tables spm_cond_t; + +struct idle_cond_info { + unsigned int subsys_mask; + uintptr_t addr; + bool bBitflip; + unsigned int clkmux_id; +}; + +#define IDLE_CG(mask, addr, bitflip, clkmux) \ + {mask, (uintptr_t)addr, bitflip, clkmux} + +static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = { + IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U), + IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U), + IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U), + IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U), + IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U), + IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U), + IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U), + IDLE_CG(0x00100000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)), + IDLE_CG(0x00100000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)), + IDLE_CG(0x00100000, MMSYS_CG_CON2, true, (CLK_CHECK | CLKMUX_DISP)), +}; + +/*********************************************************** + * Check pll idle condition + ***********************************************************/ +#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x268) +#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x360) +#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x308) +#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x350) +#define PLL_TVDPLL MT_LP_TZ_APMIXEDSYS(0x380) + +unsigned int mt_spm_cond_check(int state_id, + const struct mt_spm_cond_tables *src, + const struct mt_spm_cond_tables *dest, + struct mt_spm_cond_tables *res) +{ + unsigned int blocked = 0U, i; + bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id); + + if ((src == NULL) || (dest == NULL)) { + return SPM_COND_CHECK_FAIL; + } + + for (i = 0U; i < PLAT_SPM_COND_MAX; i++) { + if (res != NULL) { + res->table_cg[i] = + (src->table_cg[i] & dest->table_cg[i]); + + if (is_system_suspend && (res->table_cg[i] != 0U)) { + INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n", + dest->name, i, idle_cg_info[i].addr, + res->table_cg[i]); + } + + if (res->table_cg[i] != 0U) { + blocked |= (1U << i); + } + } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) { + blocked |= (1U << i); + break; + } + } + + if (res != NULL) { + res->table_pll = (src->table_pll & dest->table_pll); + + if (res->table_pll != 0U) { + blocked |= + (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | + SPM_COND_CHECK_BLOCKED_PLL; + } + } else if ((src->table_pll & dest->table_pll) != 0U) { + blocked |= SPM_COND_CHECK_BLOCKED_PLL; + } + + if (is_system_suspend && (blocked != 0U)) { + INFO("suspend: %s total blocked = 0x%08x\n", + dest->name, blocked); + } + + return blocked; +} + +#define IS_MT_SPM_PWR_OFF(mask) \ + (((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \ + ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U)) + +int mt_spm_cond_update(struct mt_resource_constraint **con, + int stateid, void *priv) +{ + int res; + uint32_t i; + struct mt_resource_constraint *const *rc; + + /* read all cg state */ + for (i = 0U; i < PLAT_SPM_COND_MAX; i++) { + spm_cond_t.table_cg[i] = 0U; + + /* check mtcmos, if off set idle_value and clk to 0 disable */ + if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) { + continue; + } + + /* check clkmux */ + if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) { + continue; + } + + spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ? + ~mmio_read_32(idle_cg_info[i].addr) : + mmio_read_32(idle_cg_info[i].addr); + } + + spm_cond_t.table_pll = 0U; + if ((mmio_read_32(PLL_MFGPLL) & 0x1) != 0U) { + spm_cond_t.table_pll |= PLL_BIT_MFGPLL; + } + + if ((mmio_read_32(PLL_MMPLL) & 0x1) != 0U) { + spm_cond_t.table_pll |= PLL_BIT_MMPLL; + } + + if ((mmio_read_32(PLL_UNIVPLL) & 0x1) != 0U) { + spm_cond_t.table_pll |= PLL_BIT_UNIVPLL; + } + + if ((mmio_read_32(PLL_MSDCPLL) & 0x1) != 0U) { + spm_cond_t.table_pll |= PLL_BIT_MSDCPLL; + } + + if ((mmio_read_32(PLL_TVDPLL) & 0x1) != 0U) { + spm_cond_t.table_pll |= PLL_BIT_TVDPLL; + } + + spm_cond_t.priv = priv; + for (rc = con; *rc != NULL; rc++) { + if (((*rc)->update) == NULL) { + continue; + } + + res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION, + (void const *)&spm_cond_t); + if (res != MT_RM_STATUS_OK) { + break; + } + } + + return 0; +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h new file mode 100644 index 0000000..91ebdd9 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_CONDIT_H +#define MT_SPM_CONDIT_H + +#include <mt_lp_rm.h> + +enum PLAT_SPM_COND { + PLAT_SPM_COND_MTCMOS1 = 0, + PLAT_SPM_COND_CG_INFRA_0, + PLAT_SPM_COND_CG_INFRA_1, + PLAT_SPM_COND_CG_INFRA_2, + PLAT_SPM_COND_CG_INFRA_3, + PLAT_SPM_COND_CG_INFRA_4, + PLAT_SPM_COND_CG_INFRA_5, + PLAT_SPM_COND_CG_MMSYS_0, + PLAT_SPM_COND_CG_MMSYS_1, + PLAT_SPM_COND_CG_MMSYS_2, + PLAT_SPM_COND_MAX, +}; + +#define PLL_BIT_UNIVPLL BIT(0) +#define PLL_BIT_MFGPLL BIT(1) +#define PLL_BIT_MSDCPLL BIT(2) +#define PLL_BIT_TVDPLL BIT(3) +#define PLL_BIT_MMPLL BIT(4) + +/* Definition about SPM_COND_CHECK_BLOCKED + * bit [00 ~ 15]: cg blocking index + * bit [16 ~ 29]: pll blocking index + * bit [30] : pll blocking information + * bit [31] : idle condition check fail + */ +#define SPM_COND_BLOCKED_CG_IDX U(0) +#define SPM_COND_BLOCKED_PLL_IDX U(16) +#define SPM_COND_CHECK_BLOCKED_PLL BIT(30) +#define SPM_COND_CHECK_FAIL BIT(31) + +struct mt_spm_cond_tables { + char *name; + unsigned int table_cg[PLAT_SPM_COND_MAX]; + unsigned int table_pll; + void *priv; +}; + +extern unsigned int mt_spm_cond_check(int state_id, + const struct mt_spm_cond_tables *src, + const struct mt_spm_cond_tables *dest, + struct mt_spm_cond_tables *res); +extern int mt_spm_cond_update(struct mt_resource_constraint **con, + int stateid, void *priv); +#endif /* MT_SPM_CONDIT_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.c new file mode 100644 index 0000000..f9e6654 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/mmio.h> + +#include <mt_spm.h> +#include <mt_spm_conservation.h> +#include <mt_spm_internal.h> +#include <mt_spm_reg.h> +#include <mt_spm_vcorefs.h> +#include <plat_mtk_lpm.h> +#include <plat_pm.h> +#include <plat/common/platform.h> +#include <platform_def.h> + +struct wake_status spm_wakesta; /* record last wakesta */ + +static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand, + struct spm_lp_scen *spm_lp, + unsigned int resource_req) +{ + int ret = 0; + struct pwr_ctrl *pwrctrl; + uint32_t cpu = plat_my_core_pos(); + + pwrctrl = spm_lp->pwrctrl; + + __spm_set_cpu_status(cpu); + __spm_set_power_control(pwrctrl); + __spm_set_wakeup_event(pwrctrl); + __spm_sync_vcore_dvfs_power_control(pwrctrl, __spm_vcorefs.pwrctrl); + __spm_set_pcm_flags(pwrctrl); + __spm_src_req_update(pwrctrl, resource_req); + + if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) { + __spm_set_pcm_wdt(1); + } + + if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) { + __spm_xo_soc_bblpm(1); + } + + if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) { + spm_hw_s1_state_monitor_resume(); + } + + /* Disable auto resume by PCM in system suspend stage */ + if (IS_PLAT_SUSPEND_ID(state_id)) { + __spm_disable_pcm_timer(); + __spm_set_pcm_wdt(0); + } + + __spm_send_cpu_wakeup_event(); + + INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n", + cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE), + mmio_read_32(PCM_TIMER_VAL) / 32768); + INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n", + pwrctrl->pcm_flags, pwrctrl->pcm_flags1, + mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS), + mmio_read_32(PWR_STATUS_2ND)); + + return ret; +} + +static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand, + struct spm_lp_scen *spm_lp, + struct wake_status **status) +{ + unsigned int ext_status = 0U; + + /* system watchdog will be resumed at kernel stage */ + if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) { + __spm_set_pcm_wdt(0); + } + + if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) { + __spm_xo_soc_bblpm(0); + } + + if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) { + spm_hw_s1_state_monitor_pause(&ext_status); + } + + __spm_ext_int_wakeup_req_clr(); + __spm_get_wakeup_status(&spm_wakesta, ext_status); + + if (status != NULL) { + *status = &spm_wakesta; + } + + __spm_clean_after_wakeup(); + + if (IS_PLAT_SUSPEND_ID(state_id)) { + __spm_output_wake_reason(state_id, &spm_wakesta); + } +} + +int spm_conservation(int state_id, unsigned int ext_opand, + struct spm_lp_scen *spm_lp, unsigned int resource_req) +{ + if (spm_lp == NULL) { + return -1; + } + + spm_lock_get(); + go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req); + spm_lock_release(); + + return 0; +} + +void spm_conservation_finish(int state_id, unsigned int ext_opand, + struct spm_lp_scen *spm_lp, + struct wake_status **status) +{ + spm_lock_get(); + go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status); + spm_lock_release(); +} + +int spm_conservation_get_result(struct wake_status **res) +{ + if (res == NULL) { + return -1; + } + + *res = &spm_wakesta; + + return 0; +} + +#define GPIO_BANK (GPIO_BASE + 0x6F0) +#define TRAP_UFS_FIRST BIT(11) /* bit 11, 0: UFS, 1: eMMC */ + +void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl) +{ + if (pwrctrl == NULL) { + return; + } + + /* For ufs, emmc storage type */ + if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) { + /* If eMMC is used, mask UFS req */ + pwrctrl->reg_ufs_srcclkena_mask_b = 0; + pwrctrl->reg_ufs_infra_req_mask_b = 0; + pwrctrl->reg_ufs_apsrc_req_mask_b = 0; + pwrctrl->reg_ufs_vrf18_req_mask_b = 0; + pwrctrl->reg_ufs_ddr_en_mask_b = 0; + } +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h new file mode 100644 index 0000000..c5e97db --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_CONSERVATION_H +#define MT_SPM_CONSERVATION_H + +#include <mt_spm_internal.h> + +extern int spm_conservation(int state_id, unsigned int ext_opand, + struct spm_lp_scen *spm_lp, + unsigned int resource_req); +extern void spm_conservation_finish(int state_id, unsigned int ext_opand, + struct spm_lp_scen *spm_lp, + struct wake_status **status); +extern int spm_conservation_get_result(struct wake_status **res); +extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl); +#endif /* MT_SPM_CONSERVATION_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h new file mode 100644 index 0000000..a3409f7 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_CONSTRAINT_H +#define MT_SPM_CONSTRAINT_H + +#include <mt_lp_rm.h> + +#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0) +#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1) +#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2) +#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3) +#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4) +#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5) +#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6) +#define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7) +#define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8) +#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9) +#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10) + +#define MT_SPM_RC_INVALID 0x0 +#define MT_SPM_RC_VALID_SW (1U << 0) +#define MT_SPM_RC_VALID_FW (1U << 1) +#define MT_SPM_RC_VALID_RESIDNECY (1U << 2) +#define MT_SPM_RC_VALID_COND_CHECK (1U << 3) +#define MT_SPM_RC_VALID_COND_LATCH (1U << 4) +#define MT_SPM_RC_VALID_UFS_H8 (1U << 5) +#define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6) +#define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7) +#define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8) + +#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW) + +#define IS_MT_RM_RC_READY(status) \ + ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID) + +#define MT_SPM_RC_BBLPM_MODE \ + (MT_SPM_RC_VALID_UFS_H8 | \ + MT_SPM_RC_VALID_FLIGHTMODE | \ + MT_SPM_RC_VALID_XSOC_BBLPM) + +#define IS_MT_SPM_RC_BBLPM_MODE(st) \ + ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE) + +struct constraint_status { + uint16_t id; + uint16_t valid; + uint32_t cond_block; + uint32_t enter_cnt; + struct mt_spm_cond_tables *cond_res; +}; + +enum MT_SPM_RM_RC_TYPE { + MT_RM_CONSTRAINT_ID_BUS26M, + MT_RM_CONSTRAINT_ID_SYSPLL, + MT_RM_CONSTRAINT_ID_DRAM, + MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO, + MT_RM_CONSTRAINT_ID_ALL, +}; +#endif /* MT_SPM_CONSTRAINT_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c new file mode 100644 index 0000000..3540ec2 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/mmio.h> + +#include <mt_spm.h> +#include <mt_spm_conservation.h> +#include <mt_spm_idle.h> +#include <mt_spm_internal.h> +#include <mt_spm_reg.h> +#include <mt_spm_resource_req.h> +#include <plat_pm.h> + +#define __WAKE_SRC_FOR_IDLE_COMMON__ \ + (R12_PCM_TIMER | \ + R12_KP_IRQ_B | \ + R12_APWDT_EVENT_B | \ + R12_APXGPT1_EVENT_B | \ + R12_CONN2AP_SPM_WAKEUP_B | \ + R12_EINT_EVENT_B | \ + R12_CONN_WDT_IRQ_B | \ + R12_CCIF0_EVENT_B | \ + R12_SSPM2SPM_WAKEUP_B | \ + R12_SCP2SPM_WAKEUP_B | \ + R12_ADSP2SPM_WAKEUP_B | \ + R12_USBX_CDSC_B | \ + R12_USBX_POWERDWN_B | \ + R12_SYS_TIMER_EVENT_B | \ + R12_EINT_EVENT_SECURE_B | \ + R12_CCIF1_EVENT_B | \ + R12_AFE_IRQ_MCU_B | \ + R12_SYS_CIRQ_IRQ_B | \ + R12_MD2AP_PEER_EVENT_B | \ + R12_MD1_WDT_B | \ + R12_CLDMA_EVENT_B | \ + R12_REG_CPU_WAKEUP | \ + R12_APUSYS_WAKE_HOST_B | \ + R12_PCIE_BRIDGE_IRQ | \ + R12_PCIE_IRQ) + +#if defined(CFG_MICROTRUST_TEE_SUPPORT) +#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__) +#else +#define WAKE_SRC_FOR_IDLE \ + (__WAKE_SRC_FOR_IDLE_COMMON__ | \ + R12_SEJ_EVENT_B) +#endif + +static struct pwr_ctrl idle_spm_pwr = { + .timer_val = 0x28000, + .wake_src = WAKE_SRC_FOR_IDLE, + + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC6_MASK */ + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddr_en_mask_b = 1, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 1, + .reg_spm_f26m_req = 1, + .reg_spm_infra_req = 1, + .reg_spm_vrf18_req = 1, + .reg_spm_ddr_en_req = 1, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC_MASK */ + .reg_md_srcclkena_0_mask_b = 1, + .reg_md_srcclkena2infra_req_0_mask_b = 0, + .reg_md_apsrc2infra_req_0_mask_b = 1, + .reg_md_apsrc_req_0_mask_b = 1, + .reg_md_vrf18_req_0_mask_b = 1, + .reg_md_ddr_en_0_mask_b = 1, + .reg_md_srcclkena_1_mask_b = 0, + .reg_md_srcclkena2infra_req_1_mask_b = 0, + .reg_md_apsrc2infra_req_1_mask_b = 0, + .reg_md_apsrc_req_1_mask_b = 0, + .reg_md_vrf18_req_1_mask_b = 0, + .reg_md_ddr_en_1_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddr_en_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni0_srcclkena_mask_b = 1, + .reg_srcclkeni0_infra_req_mask_b = 1, + .reg_srcclkeni1_srcclkena_mask_b = 0, + .reg_srcclkeni1_infra_req_mask_b = 0, + .reg_srcclkeni2_srcclkena_mask_b = 0, + .reg_srcclkeni2_infra_req_mask_b = 0, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddr_en_mask_b = 1, + .reg_md32_srcclkena_mask_b = 1, + .reg_md32_infra_req_mask_b = 1, + .reg_md32_apsrc_req_mask_b = 1, + .reg_md32_vrf18_req_mask_b = 1, + .reg_md32_ddr_en_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddr_en_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddr_en_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddr_en_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddr_en_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddr_en_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddr_en_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_apu_ddr_en_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddr_en_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_int0_mask_b = 0, + .reg_sw2spm_int1_mask_b = 0, + .reg_sw2spm_int2_mask_b = 0, + .reg_sw2spm_int3_mask_b = 0, + .reg_sc_adsp2spm_wakeup_mask_b = 0, + .reg_sc_sspm2spm_wakeup_mask_b = 0, + .reg_sc_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrreq_mask = 1, + .reg_spm_srcclkena_reserved_mask_b = 0, + .reg_spm_infra_req_reserved_mask_b = 0, + .reg_spm_apsrc_req_reserved_mask_b = 0, + .reg_spm_vrf18_req_reserved_mask_b = 0, + .reg_spm_ddr_en_reserved_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddr_en_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddr_en_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddr_en_mask_b = 1, + + /* SPM_SRC4_MASK */ + .ccif_event_mask_b = 0xFFF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddr_en_mask_b = 0, + .reg_dramc0_md32_infra_req_mask_b = 1, + .reg_dramc0_md32_vrf18_req_mask_b = 0, + .reg_dramc1_md32_infra_req_mask_b = 1, + .reg_dramc1_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc0_md32_wakeup_mask = 1, + .reg_dramc1_md32_wakeup_mask = 1, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x11, + .reg_mcusys_merge_ddr_en_mask_b = 0x11, + .reg_msdc2_srcclkena_mask_b = 1, + .reg_msdc2_infra_req_mask_b = 1, + .reg_msdc2_apsrc_req_mask_b = 1, + .reg_msdc2_vrf18_req_mask_b = 1, + .reg_msdc2_ddr_en_mask_b = 1, + .reg_pcie_srcclkena_mask_b = 1, + .reg_pcie_infra_req_mask_b = 1, + .reg_pcie_apsrc_req_mask_b = 1, + .reg_pcie_vrf18_req_mask_b = 1, + .reg_pcie_ddr_en_mask_b = 1, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0x01282202, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* Auto-gen End */ +}; + +struct spm_lp_scen idle_spm_lp = { + .pwrctrl = &idle_spm_pwr, +}; + +int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, + spm_idle_conduct fn) +{ + unsigned int src_req = 0; + + if (fn != NULL) { + fn(&idle_spm_lp, &src_req); + } + + return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req); +} +void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand, + struct wake_status **status) +{ + spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status); +} + +void mt_spm_idle_generic_init(void) +{ + spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl); +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h new file mode 100644 index 0000000..3d42cf1 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_IDLE_H +#define MT_SPM_IDLE_H + +typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp, + unsigned int *resource_req); +int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, + spm_idle_conduct fn); +void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand, + struct wake_status **status); +void mt_spm_idle_generic_init(void); +#endif /* MT_SPM_IDLE_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c new file mode 100644 index 0000000..40be027 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stddef.h> + +#include <assert.h> +#include <common/debug.h> +#include <lib/mmio.h> + +#include <mt_spm.h> +#include <mt_spm_internal.h> +#include <mt_spm_pmic_wrap.h> +#include <mt_spm_reg.h> +#include <mt_spm_resource_req.h> +#include <platform_def.h> +#include <plat_pm.h> + +/************************************** + * Define and Declare + **************************************/ +#define ROOT_CORE_ADDR_OFFSET 0x20000000 +#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff +#define SPM_INIT_DONE_US 20 + +static unsigned int mt_spm_bblpm_cnt; + +const char *wakeup_src_str[32] = { + [0] = "R12_PCM_TIMER", + [1] = "R12_RESERVED_DEBUG_B", + [2] = "R12_KP_IRQ_B", + [3] = "R12_APWDT_EVENT_B", + [4] = "R12_APXGPT1_EVENT_B", + [5] = "R12_CONN2AP_SPM_WAKEUP_B", + [6] = "R12_EINT_EVENT_B", + [7] = "R12_CONN_WDT_IRQ_B", + [8] = "R12_CCIF0_EVENT_B", + [9] = "R12_LOWBATTERY_IRQ_B", + [10] = "R12_SC_SSPM2SPM_WAKEUP_B", + [11] = "R12_SC_SCP2SPM_WAKEUP_B", + [12] = "R12_SC_ADSP2SPM_WAKEUP_B", + [13] = "R12_PCM_WDT_WAKEUP_B", + [14] = "R12_USB_CDSC_B", + [15] = "R12_USB_POWERDWN_B", + [16] = "R12_SYS_TIMER_EVENT_B", + [17] = "R12_EINT_EVENT_SECURE_B", + [18] = "R12_CCIF1_EVENT_B", + [19] = "R12_UART0_IRQ_B", + [20] = "R12_AFE_IRQ_MCU_B", + [21] = "R12_THERM_CTRL_EVENT_B", + [22] = "R12_SYS_CIRQ_IRQ_B", + [23] = "R12_MD2AP_PEER_EVENT_B", + [24] = "R12_CSYSPWREQ_B", + [25] = "R12_MD1_WDT_B", + [26] = "R12_AP2AP_PEER_WAKEUPEVENT_B", + [27] = "R12_SEJ_EVENT_B", + [28] = "R12_SPM_CPU_WAKEUPEVENT_B", + [29] = "R12_APUSYS", + [30] = "R12_PCIE_BRIDGE_IRQ", + [31] = "R12_PCIE_IRQ", +}; + +/************************************** + * Function and API + **************************************/ + +wake_reason_t __spm_output_wake_reason(int state_id, + const struct wake_status *wakesta) +{ + uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U; + wake_reason_t wr = WR_UNKNOWN; + + if (wakesta == NULL) { + return WR_UNKNOWN; + } + + if (wakesta->abort != 0U) { + ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n", + wakesta->abort, wakesta->timer_out); + } else { + for (i = 0U; i < 32U; i++) { + if ((wakesta->r12 & (1U << i)) != 0U) { + INFO("wake up by %s, timer_out = %u\n", + wakeup_src_str[i], wakesta->timer_out); + wr = WR_WAKE_SRC; + break; + } + } + } + + INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", + wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag, + wakesta->debug_flag1); + INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n", + wakesta->raw_sta, wakesta->md32pcm_wakeup_sta, + wakesta->md32pcm_event_sta, wakesta->idle_sta, + wakesta->cg_check_sta); + INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n", + wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2, + wakesta->req_sta3, wakesta->req_sta4, wakesta->isr); + INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n", + wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2); + INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n", + wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta); + INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n", + wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1, + wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req); + INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n", + wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), + mmio_read_32(SYS_TIMER_VALUE_H)); + + if (wakesta->timer_out != 0U) { + bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); + spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out; + INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct); + } + + return wr; +} + +void __spm_set_cpu_status(unsigned int cpu) +{ + uint32_t root_core_addr; + + if (cpu < 8U) { + mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu)); + root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4); + root_core_addr += ROOT_CORE_ADDR_OFFSET; + mmio_write_32(ROOT_CORE_ADDR, root_core_addr); + /* Notify MCUPM that preferred cpu wakeup */ + mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu); + } else { + ERROR("%s: error cpu number %d\n", __func__, cpu); + } +} + +void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, + unsigned int resource_usage) +{ + uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ? + 1 : pwrctrl->reg_spm_apsrc_req; + uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ? + 1 : pwrctrl->reg_spm_ddr_en_req; + uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ? + 1 : pwrctrl->reg_spm_vrf18_req; + uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ? + 1 : pwrctrl->reg_spm_infra_req; + uint8_t f26m_req = ((resource_usage & + (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ? + 1 : pwrctrl->reg_spm_f26m_req; + + mmio_write_32(SPM_SRC_REQ, + ((apsrc_req & 0x1) << 0) | + ((f26m_req & 0x1) << 1) | + ((infra_req & 0x1) << 3) | + ((vrf18_req & 0x1) << 4) | + ((ddr_en_req & 0x1) << 7) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); +} + +void __spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + mmio_write_32(SPM_AP_STANDBY_CON, + ((pwrctrl->reg_wfi_op & 0x1) << 0) | + ((pwrctrl->reg_wfi_type & 0x1) << 1) | + ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | + ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | + ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | + ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | + ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | + ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); + + /* SPM_SRC6_MASK */ + mmio_write_32(SPM_SRC6_MASK, + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4)); + + /* SPM_SRC_REQ */ + mmio_write_32(SPM_SRC_REQ, + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | + ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); + + /* SPM_SRC_MASK */ + mmio_write_32(SPM_SRC_MASK, + ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) | + ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) | + ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) | + ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) | + ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) | + ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) | + ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) | + ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) | + ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) | + ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) | + ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC2_MASK */ + mmio_write_32(SPM_SRC2_MASK, + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC3_MASK */ + mmio_write_32(SPM_SRC3_MASK, + ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | + ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) | + ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) | + ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) | + ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) | + ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) | + ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) | + ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) | + ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) | + ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) | + ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) | + ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | + ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) | + ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC4_MASK */ + mmio_write_32(SPM_SRC4_MASK, + ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) | + ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | + ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) | + ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | + ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) | + ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27)); + + /* SPM_SRC5_MASK */ + mmio_write_32(SPM_SRC5_MASK, + ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | + ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) | + ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) | + ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) | + ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27)); + + /* SPM_WAKEUP_EVENT_MASK */ + mmio_write_32(SPM_WAKEUP_EVENT_MASK, + ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, + ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); + + /* Auto-gen End */ +} + +void __spm_disable_pcm_timer(void) +{ + mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); +} + +void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + uint32_t val, mask; + + /* toggle event counter clear */ + mmio_setbits_32(PCM_CON1, + SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); + + /* toggle for reset SYS TIMER start point */ + mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); + + if (pwrctrl->timer_val_cust == 0U) { + val = pwrctrl->timer_val; + } else { + val = pwrctrl->timer_val_cust; + } + + mmio_write_32(PCM_TIMER_VAL, val); + mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB); + + /* unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0U) { + mask = pwrctrl->wake_src; + } else { + mask = pwrctrl->wake_src_cust; + } + + if (pwrctrl->reg_csyspwrreq_mask != 0U) { + mask &= ~R12_CSYSPWREQ_B; + } + + mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); + + /* unmask SPM ISR (keep TWAM setting) */ + mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX); + + /* toggle event counter clear */ + mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB, + SPM_REGWR_CFG_KEY); + /* toggle for reset SYS TIMER start point */ + mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB); +} + +void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) +{ + /* set PCM flags and data */ + if (pwrctrl->pcm_flags_cust_clr != 0U) { + pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; + } + + if (pwrctrl->pcm_flags_cust_set != 0U) { + pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; + } + + if (pwrctrl->pcm_flags1_cust_clr != 0U) { + pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; + } + + if (pwrctrl->pcm_flags1_cust_set != 0U) { + pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; + } + + mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags); + mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1); + mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags); + mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1); +} + +void __spm_get_wakeup_status(struct wake_status *wakesta, + unsigned int ext_status) +{ + wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); + wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); + wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA); + wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0); + wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1); + wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2); + wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3); + wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4); + wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); + wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); + + if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) { + wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE | + SPM_DBG_DEBUG_IDX_DDREN_SLEEP); + mmio_write_32(PCM_WDT_LATCH_SPARE_0, + wakesta->tr.comm.debug_flag); + } + + wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); + wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); + + /* record below spm info for debug */ + wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT); + wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA); + wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); + wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); + wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA); + wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA); + wakesta->src_req = mmio_read_32(SPM_SRC_REQ); + + /* backup of SPM_WAKEUP_MISC */ + wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); + + /* get sleep time, backup of PCM_TIMER_OUT */ + wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER); + + /* get other SYS and co-clock status */ + wakesta->r13 = mmio_read_32(PCM_REG13_DATA); + wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); + wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0); + wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1); + wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2); + wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3); + wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4); + + /* get HW CG check status */ + wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA); + + /* get debug flag for PCM execution check */ + wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0); + wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1); + + /* get backup SW flag status */ + wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); + wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); + + wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2); + wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3); + wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4); + wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5); + wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6); + + /* get ISR status */ + wakesta->isr = mmio_read_32(SPM_IRQ_STA); + + /* get SW flag status */ + wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0); + wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1); + + /* get CLK SETTLE */ + wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE); + + /* check abort */ + wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) | + (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1); +} + +void __spm_clean_after_wakeup(void) +{ + mmio_write_32(SPM_BK_WAKE_EVENT, + mmio_read_32(SPM_WAKEUP_STA) | + mmio_read_32(SPM_BK_WAKE_EVENT)); + mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); + + /* + * clean wakeup event raw status (for edge trigger event) + * bit[28] for cpu wake up event + */ + mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK); + + /* clean ISR status (except TWAM) */ + mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); + mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); + mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); +} + +void __spm_set_pcm_wdt(int en) +{ + mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB, + SPM_REGWR_CFG_KEY); + + if (en == 1) { + mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB, + SPM_REGWR_CFG_KEY); + + if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) { + mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); + } + + mmio_write_32(PCM_WDT_VAL, + mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); + mmio_setbits_32(PCM_CON1, + SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB); + } +} + +void __spm_send_cpu_wakeup_event(void) +{ + /* SPM will clear SPM_CPU_WAKEUP_EVENT */ + mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); +} + +void __spm_ext_int_wakeup_req_clr(void) +{ + mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR)); + + /* Clear spm2mcupm wakeup interrupt status */ + mmio_write_32(SPM2MCUPM_CON, 0); +} + +void __spm_xo_soc_bblpm(int en) +{ + if (en == 1) { + mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG, + RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC); + assert(mt_spm_bblpm_cnt == 0); + mt_spm_bblpm_cnt += 1; + } else { + mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG, + RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM); + mt_spm_bblpm_cnt -= 1; + } +} + +void __spm_hw_s1_state_monitor(int en, unsigned int *status) +{ + unsigned int reg; + + reg = mmio_read_32(SPM_ACK_CHK_CON_3); + + if (en == 1) { + reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL; + mmio_write_32(SPM_ACK_CHK_CON_3, reg); + reg |= SPM_ACK_CHK_3_CON_EN; + mmio_write_32(SPM_ACK_CHK_CON_3, reg); + } else { + if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) && + (status != NULL)) { + *status |= SPM_INTERNAL_STATUS_HW_S1; + } + + mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG | + SPM_ACK_CHK_3_CON_CLR_ALL); + } +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h new file mode 100644 index 0000000..1d0f783 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h @@ -0,0 +1,637 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_INTERNAL_H +#define MT_SPM_INTERNAL_H + +#include "mt_spm.h" + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL0_DEF 0x0000F100 +#define POWER_ON_VAL1_DEF 0x80015860 +#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Define and Declare + **************************************/ +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT0 (1U << 0) +#define PCM_SW_INT1 (1U << 1) +#define PCM_SW_INT2 (1U << 2) +#define PCM_SW_INT3 (1U << 3) +#define PCM_SW_INT4 (1U << 4) +#define PCM_SW_INT5 (1U << 5) +#define PCM_SW_INT6 (1U << 6) +#define PCM_SW_INT7 (1U << 7) +#define PCM_SW_INT8 (1U << 8) +#define PCM_SW_INT9 (1U << 9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) + +/* SPM_AP_STANDBY_CON */ +#define WFI_OP_AND 1 +#define WFI_OP_OR 0 + +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ0 (1U << 8) +#define ISRM_RET_IRQ1 (1U << 9) +#define ISRM_RET_IRQ2 (1U << 10) +#define ISRM_RET_IRQ3 (1U << 11) +#define ISRM_RET_IRQ4 (1U << 12) +#define ISRM_RET_IRQ5 (1U << 13) +#define ISRM_RET_IRQ6 (1U << 14) +#define ISRM_RET_IRQ7 (1U << 15) +#define ISRM_RET_IRQ8 (1U << 16) +#define ISRM_RET_IRQ9 (1U << 17) +#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \ + (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \ + (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \ + (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \ + (ISRM_RET_IRQ1)) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_WAKEUP_MISC */ +#define WAKE_MISC_GIC_WAKEUP 0x3FF +#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB +#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB +#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB +#define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20)) +#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB +#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB +#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB +#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB +#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB +#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB +#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB +#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB +#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB +#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB +#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB + +/* ABORT MASK for DEBUG FOORTPRINT */ +#define DEBUG_ABORT_MASK \ + (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \ + SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN) + +#define DEBUG_ABORT_MASK_1 \ + (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \ + SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \ + SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \ + SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \ + SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \ + SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \ + SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT) + +#define MCUPM_MBOX_WAKEUP_CPU 0x0C55FD10 + +struct pwr_ctrl { + uint32_t pcm_flags; + uint32_t pcm_flags_cust; + uint32_t pcm_flags_cust_set; + uint32_t pcm_flags_cust_clr; + uint32_t pcm_flags1; + uint32_t pcm_flags1_cust; + uint32_t pcm_flags1_cust_set; + uint32_t pcm_flags1_cust_clr; + uint32_t timer_val; + uint32_t timer_val_cust; + uint32_t timer_val_ramp_en; + uint32_t timer_val_ramp_en_sec; + uint32_t wake_src; + uint32_t wake_src_cust; + uint32_t wakelock_timer_val; + uint8_t wdt_disable; + + /* Auto-gen Start */ + + /* SPM_CLK_CON */ + uint8_t reg_srcclken0_ctl; + uint8_t reg_srcclken1_ctl; + uint8_t reg_spm_lock_infra_dcm; + uint8_t reg_srcclken_mask; + uint8_t reg_md1_c32rm_en; + uint8_t reg_md2_c32rm_en; + uint8_t reg_clksq0_sel_ctrl; + uint8_t reg_clksq1_sel_ctrl; + uint8_t reg_srcclken0_en; + uint8_t reg_srcclken1_en; + uint32_t reg_sysclk0_src_mask_b; + uint32_t reg_sysclk1_src_mask_b; + + /* SPM_AP_STANDBY_CON */ + uint8_t reg_wfi_op; + uint8_t reg_wfi_type; + uint8_t reg_mp0_cputop_idle_mask; + uint8_t reg_mp1_cputop_idle_mask; + uint8_t reg_mcusys_idle_mask; + uint8_t reg_md_apsrc_1_sel; + uint8_t reg_md_apsrc_0_sel; + uint8_t reg_conn_apsrc_sel; + + /* SPM_SRC6_MASK */ + uint8_t reg_dpmaif_srcclkena_mask_b; + uint8_t reg_dpmaif_infra_req_mask_b; + uint8_t reg_dpmaif_apsrc_req_mask_b; + uint8_t reg_dpmaif_vrf18_req_mask_b; + uint8_t reg_dpmaif_ddr_en_mask_b; + /* SPM_SRC_REQ */ + uint8_t reg_spm_apsrc_req; + uint8_t reg_spm_f26m_req; + uint8_t reg_spm_infra_req; + uint8_t reg_spm_vrf18_req; + uint8_t reg_spm_ddr_en_req; + uint8_t reg_spm_dvfs_req; + uint8_t reg_spm_sw_mailbox_req; + uint8_t reg_spm_sspm_mailbox_req; + uint8_t reg_spm_adsp_mailbox_req; + uint8_t reg_spm_scp_mailbox_req; + + /* SPM_SRC_MASK */ + uint8_t reg_md_srcclkena_0_mask_b; + uint8_t reg_md_srcclkena2infra_req_0_mask_b; + uint8_t reg_md_apsrc2infra_req_0_mask_b; + uint8_t reg_md_apsrc_req_0_mask_b; + uint8_t reg_md_vrf18_req_0_mask_b; + uint8_t reg_md_ddr_en_0_mask_b; + uint8_t reg_md_srcclkena_1_mask_b; + uint8_t reg_md_srcclkena2infra_req_1_mask_b; + uint8_t reg_md_apsrc2infra_req_1_mask_b; + uint8_t reg_md_apsrc_req_1_mask_b; + uint8_t reg_md_vrf18_req_1_mask_b; + uint8_t reg_md_ddr_en_1_mask_b; + uint8_t reg_conn_srcclkena_mask_b; + uint8_t reg_conn_srcclkenb_mask_b; + uint8_t reg_conn_infra_req_mask_b; + uint8_t reg_conn_apsrc_req_mask_b; + uint8_t reg_conn_vrf18_req_mask_b; + uint8_t reg_conn_ddr_en_mask_b; + uint8_t reg_conn_vfe28_mask_b; + uint8_t reg_srcclkeni0_srcclkena_mask_b; + uint8_t reg_srcclkeni0_infra_req_mask_b; + uint8_t reg_srcclkeni1_srcclkena_mask_b; + uint8_t reg_srcclkeni1_infra_req_mask_b; + uint8_t reg_srcclkeni2_srcclkena_mask_b; + uint8_t reg_srcclkeni2_infra_req_mask_b; + uint8_t reg_infrasys_apsrc_req_mask_b; + uint8_t reg_infrasys_ddr_en_mask_b; + uint8_t reg_md32_srcclkena_mask_b; + uint8_t reg_md32_infra_req_mask_b; + uint8_t reg_md32_apsrc_req_mask_b; + uint8_t reg_md32_vrf18_req_mask_b; + uint8_t reg_md32_ddr_en_mask_b; + + /* SPM_SRC2_MASK */ + uint8_t reg_scp_srcclkena_mask_b; + uint8_t reg_scp_infra_req_mask_b; + uint8_t reg_scp_apsrc_req_mask_b; + uint8_t reg_scp_vrf18_req_mask_b; + uint8_t reg_scp_ddr_en_mask_b; + uint8_t reg_audio_dsp_srcclkena_mask_b; + uint8_t reg_audio_dsp_infra_req_mask_b; + uint8_t reg_audio_dsp_apsrc_req_mask_b; + uint8_t reg_audio_dsp_vrf18_req_mask_b; + uint8_t reg_audio_dsp_ddr_en_mask_b; + uint8_t reg_ufs_srcclkena_mask_b; + uint8_t reg_ufs_infra_req_mask_b; + uint8_t reg_ufs_apsrc_req_mask_b; + uint8_t reg_ufs_vrf18_req_mask_b; + uint8_t reg_ufs_ddr_en_mask_b; + uint8_t reg_disp0_apsrc_req_mask_b; + uint8_t reg_disp0_ddr_en_mask_b; + uint8_t reg_disp1_apsrc_req_mask_b; + uint8_t reg_disp1_ddr_en_mask_b; + uint8_t reg_gce_infra_req_mask_b; + uint8_t reg_gce_apsrc_req_mask_b; + uint8_t reg_gce_vrf18_req_mask_b; + uint8_t reg_gce_ddr_en_mask_b; + uint8_t reg_apu_srcclkena_mask_b; + uint8_t reg_apu_infra_req_mask_b; + uint8_t reg_apu_apsrc_req_mask_b; + uint8_t reg_apu_vrf18_req_mask_b; + uint8_t reg_apu_ddr_en_mask_b; + uint8_t reg_cg_check_srcclkena_mask_b; + uint8_t reg_cg_check_apsrc_req_mask_b; + uint8_t reg_cg_check_vrf18_req_mask_b; + uint8_t reg_cg_check_ddr_en_mask_b; + + /* SPM_SRC3_MASK */ + uint8_t reg_dvfsrc_event_trigger_mask_b; + uint8_t reg_sw2spm_int0_mask_b; + uint8_t reg_sw2spm_int1_mask_b; + uint8_t reg_sw2spm_int2_mask_b; + uint8_t reg_sw2spm_int3_mask_b; + uint8_t reg_sc_adsp2spm_wakeup_mask_b; + uint8_t reg_sc_sspm2spm_wakeup_mask_b; + uint8_t reg_sc_scp2spm_wakeup_mask_b; + uint8_t reg_csyspwrreq_mask; + uint8_t reg_spm_srcclkena_reserved_mask_b; + uint8_t reg_spm_infra_req_reserved_mask_b; + uint8_t reg_spm_apsrc_req_reserved_mask_b; + uint8_t reg_spm_vrf18_req_reserved_mask_b; + uint8_t reg_spm_ddr_en_reserved_mask_b; + uint8_t reg_mcupm_srcclkena_mask_b; + uint8_t reg_mcupm_infra_req_mask_b; + uint8_t reg_mcupm_apsrc_req_mask_b; + uint8_t reg_mcupm_vrf18_req_mask_b; + uint8_t reg_mcupm_ddr_en_mask_b; + uint8_t reg_msdc0_srcclkena_mask_b; + uint8_t reg_msdc0_infra_req_mask_b; + uint8_t reg_msdc0_apsrc_req_mask_b; + uint8_t reg_msdc0_vrf18_req_mask_b; + uint8_t reg_msdc0_ddr_en_mask_b; + uint8_t reg_msdc1_srcclkena_mask_b; + uint8_t reg_msdc1_infra_req_mask_b; + uint8_t reg_msdc1_apsrc_req_mask_b; + uint8_t reg_msdc1_vrf18_req_mask_b; + uint8_t reg_msdc1_ddr_en_mask_b; + + /* SPM_SRC4_MASK */ + uint32_t ccif_event_mask_b; + uint8_t reg_bak_psri_srcclkena_mask_b; + uint8_t reg_bak_psri_infra_req_mask_b; + uint8_t reg_bak_psri_apsrc_req_mask_b; + uint8_t reg_bak_psri_vrf18_req_mask_b; + uint8_t reg_bak_psri_ddr_en_mask_b; + uint8_t reg_dramc0_md32_infra_req_mask_b; + uint8_t reg_dramc0_md32_vrf18_req_mask_b; + uint8_t reg_dramc1_md32_infra_req_mask_b; + uint8_t reg_dramc1_md32_vrf18_req_mask_b; + uint8_t reg_conn_srcclkenb2pwrap_mask_b; + uint8_t reg_dramc0_md32_wakeup_mask; + uint8_t reg_dramc1_md32_wakeup_mask; + + /* SPM_SRC5_MASK */ + uint32_t reg_mcusys_merge_apsrc_req_mask_b; + uint32_t reg_mcusys_merge_ddr_en_mask_b; + uint8_t reg_msdc2_srcclkena_mask_b; + uint8_t reg_msdc2_infra_req_mask_b; + uint8_t reg_msdc2_apsrc_req_mask_b; + uint8_t reg_msdc2_vrf18_req_mask_b; + uint8_t reg_msdc2_ddr_en_mask_b; + uint8_t reg_pcie_srcclkena_mask_b; + uint8_t reg_pcie_infra_req_mask_b; + uint8_t reg_pcie_apsrc_req_mask_b; + uint8_t reg_pcie_vrf18_req_mask_b; + uint8_t reg_pcie_ddr_en_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + uint32_t reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + uint32_t reg_ext_wakeup_event_mask; + + /* Auto-gen End */ +}; + +/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */ +enum pwr_ctrl_enum { + PW_PCM_FLAGS, + PW_PCM_FLAGS_CUST, + PW_PCM_FLAGS_CUST_SET, + PW_PCM_FLAGS_CUST_CLR, + PW_PCM_FLAGS1, + PW_PCM_FLAGS1_CUST, + PW_PCM_FLAGS1_CUST_SET, + PW_PCM_FLAGS1_CUST_CLR, + PW_TIMER_VAL, + PW_TIMER_VAL_CUST, + PW_TIMER_VAL_RAMP_EN, + PW_TIMER_VAL_RAMP_EN_SEC, + PW_WAKE_SRC, + PW_WAKE_SRC_CUST, + PW_WAKELOCK_TIMER_VAL, + PW_WDT_DISABLE, + + /* SPM_CLK_CON */ + PW_REG_SRCCLKEN0_CTL, + PW_REG_SRCCLKEN1_CTL, + PW_REG_SPM_LOCK_INFRA_DCM, + PW_REG_SRCCLKEN_MASK, + PW_REG_MD1_C32RM_EN, + PW_REG_MD2_C32RM_EN, + PW_REG_CLKSQ0_SEL_CTRL, + PW_REG_CLKSQ1_SEL_CTRL, + PW_REG_SRCCLKEN0_EN, + PW_REG_SRCCLKEN1_EN, + PW_REG_SYSCLK0_SRC_MASK_B, + PW_REG_SYSCLK1_SRC_MASK_B, + + /* SPM_AP_STANDBY_CON */ + PW_REG_WFI_OP, + PW_REG_WFI_TYPE, + PW_REG_MP0_CPUTOP_IDLE_MASK, + PW_REG_MP1_CPUTOP_IDLE_MASK, + PW_REG_MCUSYS_IDLE_MASK, + PW_REG_MD_APSRC_1_SEL, + PW_REG_MD_APSRC_0_SEL, + PW_REG_CONN_APSRC_SEL, + + /* SPM_SRC6_MASK */ + PW_REG_DPMAIF_SRCCLKENA_MASK_B, + PW_REG_DPMAIF_INFRA_REQ_MASK_B, + PW_REG_DPMAIF_APSRC_REQ_MASK_B, + PW_REG_DPMAIF_VRF18_REQ_MASK_B, + PW_REG_DPMAIF_DDR_EN_MASK_B, + + /* SPM_SRC_REQ */ + PW_REG_SPM_APSRC_REQ, + PW_REG_SPM_F26M_REQ, + PW_REG_SPM_INFRA_REQ, + PW_REG_SPM_VRF18_REQ, + PW_REG_SPM_DDR_EN_REQ, + PW_REG_SPM_DVFS_REQ, + PW_REG_SPM_SW_MAILBOX_REQ, + PW_REG_SPM_SSPM_MAILBOX_REQ, + PW_REG_SPM_ADSP_MAILBOX_REQ, + PW_REG_SPM_SCP_MAILBOX_REQ, + + /* SPM_SRC_MASK */ + PW_REG_MD_SRCCLKENA_0_MASK_B, + PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B, + PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B, + PW_REG_MD_APSRC_REQ_0_MASK_B, + PW_REG_MD_VRF18_REQ_0_MASK_B, + PW_REG_MD_DDR_EN_0_MASK_B, + PW_REG_MD_SRCCLKENA_1_MASK_B, + PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B, + PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B, + PW_REG_MD_APSRC_REQ_1_MASK_B, + PW_REG_MD_VRF18_REQ_1_MASK_B, + PW_REG_MD_DDR_EN_1_MASK_B, + PW_REG_CONN_SRCCLKENA_MASK_B, + PW_REG_CONN_SRCCLKENB_MASK_B, + PW_REG_CONN_INFRA_REQ_MASK_B, + PW_REG_CONN_APSRC_REQ_MASK_B, + PW_REG_CONN_VRF18_REQ_MASK_B, + PW_REG_CONN_DDR_EN_MASK_B, + PW_REG_CONN_VFE28_MASK_B, + PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B, + PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B, + PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B, + PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B, + PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B, + PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B, + PW_REG_INFRASYS_APSRC_REQ_MASK_B, + PW_REG_INFRASYS_DDR_EN_MASK_B, + PW_REG_MD32_SRCCLKENA_MASK_B, + PW_REG_MD32_INFRA_REQ_MASK_B, + PW_REG_MD32_APSRC_REQ_MASK_B, + PW_REG_MD32_VRF18_REQ_MASK_B, + PW_REG_MD32_DDR_EN_MASK_B, + + /* SPM_SRC2_MASK */ + PW_REG_SCP_SRCCLKENA_MASK_B, + PW_REG_SCP_INFRA_REQ_MASK_B, + PW_REG_SCP_APSRC_REQ_MASK_B, + PW_REG_SCP_VRF18_REQ_MASK_B, + PW_REG_SCP_DDR_EN_MASK_B, + PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B, + PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B, + PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B, + PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B, + PW_REG_AUDIO_DSP_DDR_EN_MASK_B, + PW_REG_UFS_SRCCLKENA_MASK_B, + PW_REG_UFS_INFRA_REQ_MASK_B, + PW_REG_UFS_APSRC_REQ_MASK_B, + PW_REG_UFS_VRF18_REQ_MASK_B, + PW_REG_UFS_DDR_EN_MASK_B, + PW_REG_DISP0_APSRC_REQ_MASK_B, + PW_REG_DISP0_DDR_EN_MASK_B, + PW_REG_DISP1_APSRC_REQ_MASK_B, + PW_REG_DISP1_DDR_EN_MASK_B, + PW_REG_GCE_INFRA_REQ_MASK_B, + PW_REG_GCE_APSRC_REQ_MASK_B, + PW_REG_GCE_VRF18_REQ_MASK_B, + PW_REG_GCE_DDR_EN_MASK_B, + PW_REG_APU_SRCCLKENA_MASK_B, + PW_REG_APU_INFRA_REQ_MASK_B, + PW_REG_APU_APSRC_REQ_MASK_B, + PW_REG_APU_VRF18_REQ_MASK_B, + PW_REG_APU_DDR_EN_MASK_B, + PW_REG_CG_CHECK_SRCCLKENA_MASK_B, + PW_REG_CG_CHECK_APSRC_REQ_MASK_B, + PW_REG_CG_CHECK_VRF18_REQ_MASK_B, + PW_REG_CG_CHECK_DDR_EN_MASK_B, + + /* SPM_SRC3_MASK */ + PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B, + PW_REG_SW2SPM_INT0_MASK_B, + PW_REG_SW2SPM_INT1_MASK_B, + PW_REG_SW2SPM_INT2_MASK_B, + PW_REG_SW2SPM_INT3_MASK_B, + PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B, + PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B, + PW_REG_SC_SCP2SPM_WAKEUP_MASK_B, + PW_REG_CSYSPWRREQ_MASK, + PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B, + PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B, + PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B, + PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B, + PW_REG_SPM_DDR_EN_RESERVED_MASK_B, + PW_REG_MCUPM_SRCCLKENA_MASK_B, + PW_REG_MCUPM_INFRA_REQ_MASK_B, + PW_REG_MCUPM_APSRC_REQ_MASK_B, + PW_REG_MCUPM_VRF18_REQ_MASK_B, + PW_REG_MCUPM_DDR_EN_MASK_B, + PW_REG_MSDC0_SRCCLKENA_MASK_B, + PW_REG_MSDC0_INFRA_REQ_MASK_B, + PW_REG_MSDC0_APSRC_REQ_MASK_B, + PW_REG_MSDC0_VRF18_REQ_MASK_B, + PW_REG_MSDC0_DDR_EN_MASK_B, + PW_REG_MSDC1_SRCCLKENA_MASK_B, + PW_REG_MSDC1_INFRA_REQ_MASK_B, + PW_REG_MSDC1_APSRC_REQ_MASK_B, + PW_REG_MSDC1_VRF18_REQ_MASK_B, + PW_REG_MSDC1_DDR_EN_MASK_B, + + /* SPM_SRC4_MASK */ + PW_CCIF_EVENT_MASK_B, + PW_REG_BAK_PSRI_SRCCLKENA_MASK_B, + PW_REG_BAK_PSRI_INFRA_REQ_MASK_B, + PW_REG_BAK_PSRI_APSRC_REQ_MASK_B, + PW_REG_BAK_PSRI_VRF18_REQ_MASK_B, + PW_REG_BAK_PSRI_DDR_EN_MASK_B, + PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B, + PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B, + PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B, + PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B, + PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B, + PW_REG_DRAMC0_MD32_WAKEUP_MASK, + PW_REG_DRAMC1_MD32_WAKEUP_MASK, + + /* SPM_SRC5_MASK */ + PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B, + PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B, + PW_REG_MSDC2_SRCCLKENA_MASK_B, + PW_REG_MSDC2_INFRA_REQ_MASK_B, + PW_REG_MSDC2_APSRC_REQ_MASK_B, + PW_REG_MSDC2_VRF18_REQ_MASK_B, + PW_REG_MSDC2_DDR_EN_MASK_B, + PW_REG_PCIE_SRCCLKENA_MASK_B, + PW_REG_PCIE_INFRA_REQ_MASK_B, + PW_REG_PCIE_APSRC_REQ_MASK_B, + PW_REG_PCIE_VRF18_REQ_MASK_B, + PW_REG_PCIE_DDR_EN_MASK_B, + + /* SPM_WAKEUP_EVENT_MASK */ + PW_REG_WAKEUP_EVENT_MASK, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + PW_REG_EXT_WAKEUP_EVENT_MASK, + + PW_MAX_COUNT, +}; + +#define SPM_INTERNAL_STATUS_HW_S1 (1U << 0) +#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098 +#define SPM_ACK_CHK_3_HW_S1_CNT 1 +#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800 +#define SPM_ACK_CHK_3_CON_EN 0x110 +#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2 +#define SPM_ACK_CHK_3_CON_RESULT 0x8000 + +struct wake_status_trace_comm { + uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */ + uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */ + uint32_t timer_out; /* SPM_SW_RSV_6*/ + uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */ + uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */ + uint32_t r12; /* SPM_SW_RSV_0 */ + uint32_t r13; /* PCM_REG13_DATA */ + uint32_t req_sta0; /* SRC_REQ_STA_0 */ + uint32_t req_sta1; /* SRC_REQ_STA_1 */ + uint32_t req_sta2; /* SRC_REQ_STA_2 */ + uint32_t req_sta3; /* SRC_REQ_STA_3 */ + uint32_t req_sta4; /* SRC_REQ_STA_4 */ +}; + +struct wake_status_trace { + struct wake_status_trace_comm comm; +}; + +struct wake_status { + struct wake_status_trace tr; + uint32_t r12; /* SPM_BK_WAKE_EVENT */ + uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */ + uint32_t raw_sta; /* SPM_WAKEUP_STA */ + uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */ + uint32_t md32pcm_wakeup_sta; /* MD32CPM_WAKEUP_STA */ + uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */ + uint32_t wake_misc; /* SPM_BK_WAKE_MISC */ + uint32_t timer_out; /* SPM_BK_PCM_TIMER */ + uint32_t r13; /* PCM_REG13_DATA */ + uint32_t idle_sta; /* SUBSYS_IDLE_STA */ + uint32_t req_sta0; /* SRC_REQ_STA_0 */ + uint32_t req_sta1; /* SRC_REQ_STA_1 */ + uint32_t req_sta2; /* SRC_REQ_STA_2 */ + uint32_t req_sta3; /* SRC_REQ_STA_3 */ + uint32_t req_sta4; /* SRC_REQ_STA_4 */ + uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */ + uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */ + uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */ + uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */ + uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */ + uint32_t isr; /* SPM_IRQ_STA */ + uint32_t sw_flag0; /* SPM_SW_FLAG_0 */ + uint32_t sw_flag1; /* SPM_SW_FLAG_1 */ + uint32_t clk_settle; /* SPM_CLK_SETTLE */ + uint32_t src_req; /* SPM_SRC_REQ */ + uint32_t log_index; + uint32_t abort; + uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */ + uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */ + uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */ + uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */ + uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */ + uint32_t mcupm_req_sta; +}; + +struct spm_lp_scen { + struct pcm_desc *pcmdesc; + struct pwr_ctrl *pwrctrl; +}; + +extern struct spm_lp_scen __spm_vcorefs; +extern void __spm_set_cpu_status(unsigned int cpu); +extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc); +extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc); +extern void __spm_init_pcm_register(void); +extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, + unsigned int resource_usage); +extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl); +extern void __spm_disable_pcm_timer(void); +extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); +extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); +extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl); +extern void __spm_send_cpu_wakeup_event(void); +extern void __spm_get_wakeup_status(struct wake_status *wakesta, + unsigned int ext_status); +extern void __spm_clean_after_wakeup(void); +extern wake_reason_t +__spm_output_wake_reason(int state_id, const struct wake_status *wakesta); +extern void +__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl, + const struct pwr_ctrl *src_pwr_ctrl); +extern void __spm_set_pcm_wdt(int en); +extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr); +extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl); +extern void __spm_ext_int_wakeup_req_clr(void); +extern void __spm_xo_soc_bblpm(int en); + +static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, + uint32_t flags) +{ + if (pwrctrl->pcm_flags_cust == 0U) { + pwrctrl->pcm_flags = flags; + } else { + pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; + } +} + +static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl, + uint32_t flags) +{ + if (pwrctrl->pcm_flags1_cust == 0U) { + pwrctrl->pcm_flags1 = flags; + } else { + pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust; + } +} + +extern void __spm_hw_s1_state_monitor(int en, unsigned int *status); + +static inline void spm_hw_s1_state_monitor_resume(void) +{ + __spm_hw_s1_state_monitor(1, NULL); +} + +static inline void spm_hw_s1_state_monitor_pause(unsigned int *status) +{ + __spm_hw_s1_state_monitor(0, status); +} +#endif /* MT_SPM_INTERNAL_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c new file mode 100644 index 0000000..4e5f6a0 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <string.h> + +#include <common/debug.h> +#include <lib/mmio.h> + +#include <mt_spm.h> +#include <mt_spm_internal.h> +#include <mt_spm_pmic_wrap.h> +#include <mt_spm_reg.h> +#include <plat_pm.h> +#include <platform_def.h> + +/* PMIC_WRAP MT6359 */ +#define VCORE_BASE_UV 40000 +#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) +#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV) + +#define NR_PMIC_WRAP_CMD (NR_IDX_ALL) +#define SPM_DATA_SHIFT 16 + +#define BUCK_VGPU11_ELR0 0x15B4 +#define TOP_SPI_CON0 0x0456 +#define BUCK_TOP_CON1 0x1443 +#define TOP_CON 0x0013 +#define TOP_DIG_WPK 0x03a9 +#define TOP_CON_LOCK 0x03a8 +#define TOP_CLK_CON0 0x0134 + +struct pmic_wrap_cmd { + unsigned long cmd_addr; + unsigned long cmd_wdata; +}; + +struct pmic_wrap_setting { + enum pmic_wrap_phase_id phase; + struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD]; + struct { + struct { + unsigned long cmd_addr; + unsigned long cmd_wdata; + } _[NR_PMIC_WRAP_CMD]; + const int nr_idx; + } set[NR_PMIC_WRAP_PHASE]; +}; + +static struct pmic_wrap_setting pw = { + .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */ + .addr = { {0UL, 0UL} }, + .set[PMIC_WRAP_PHASE_ALLINONE] = { + ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(72500),}, + ._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),}, + ._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),}, + ._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(57500),}, + ._[CMD_4] = {TOP_SPI_CON0, 0x1,}, + ._[CMD_5] = {TOP_SPI_CON0, 0x0,}, + ._[CMD_6] = {BUCK_TOP_CON1, 0x0,}, + ._[CMD_7] = {BUCK_TOP_CON1, 0xf,}, + ._[CMD_8] = {TOP_CON, 0x3,}, + ._[CMD_9] = {TOP_CON, 0x0,}, + ._[CMD_10] = {TOP_DIG_WPK, 0x63,}, + ._[CMD_11] = {TOP_CON_LOCK, 0x15,}, + ._[CMD_12] = {TOP_DIG_WPK, 0x0,}, + ._[CMD_13] = {TOP_CON_LOCK, 0x0,}, + ._[CMD_14] = {TOP_CLK_CON0, 0x40,}, + ._[CMD_15] = {TOP_CLK_CON0, 0x0,}, + .nr_idx = NR_IDX_ALL, + }, +}; + +void _mt_spm_pmic_table_init(void) +{ + struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = { + {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,}, + {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,}, + {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,}, + {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,}, + {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,}, + {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,}, + {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,}, + {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,}, + {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,}, + {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,}, + {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,}, + {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,}, + {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,}, + {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,}, + {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,}, + {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,}, + }; + + memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); +} + +void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) +{ + uint32_t idx, addr, data; + + if (phase >= NR_PMIC_WRAP_PHASE) { + return; + } + + if (pw.phase == phase) { + return; + } + + if (pw.addr[0].cmd_addr == 0UL) { + _mt_spm_pmic_table_init(); + } + + pw.phase = phase; + mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { + addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; + data = pw.set[phase]._[idx].cmd_wdata; + mmio_write_32(pw.addr[idx].cmd_addr, addr | data); + } +} + +void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, + uint32_t cmd_wdata) +{ + uint32_t addr; + + if (phase >= NR_PMIC_WRAP_PHASE) { + return; + } + + if (idx >= pw.set[phase].nr_idx) { + return; + } + + pw.set[phase]._[idx].cmd_wdata = cmd_wdata; + mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + if (pw.phase == phase) { + addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; + mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); + } +} + +uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx) +{ + if (phase >= NR_PMIC_WRAP_PHASE) { + return 0UL; + } + + if (idx >= pw.set[phase].nr_idx) { + return 0UL; + } + + return pw.set[phase]._[idx].cmd_wdata; +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h new file mode 100644 index 0000000..6e20916 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/**************************************************************** + * Auto generated by DE, please DO NOT modify this file directly. + *****************************************************************/ +#ifndef MT_SPM_PMIC_WRAP_H +#define MT_SPM_PMIC_WRAP_H + +enum pmic_wrap_phase_id { + PMIC_WRAP_PHASE_ALLINONE, + NR_PMIC_WRAP_PHASE, +}; + +/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */ +enum { + CMD_0, /* 0x0 */ + CMD_1, /* 0x1 */ + CMD_2, /* 0x2 */ + CMD_3, /* 0x3 */ + CMD_4, /* 0x4 */ + CMD_5, /* 0x5 */ + CMD_6, /* 0x6 */ + CMD_7, /* 0x7 */ + CMD_8, /* 0x8 */ + CMD_9, /* 0x9 */ + CMD_10, /* 0xA */ + CMD_11, /* 0xB */ + CMD_12, /* 0xC */ + CMD_13, /* 0xD */ + CMD_14, /* 0xE */ + CMD_15, /* 0xF */ + NR_IDX_ALL, +}; + +/* APIs */ +extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); +extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, + uint32_t idx, uint32_t cmd_wdata); +extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, + uint32_t idx); +#endif /* MT_SPM_PMIC_WRAP_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h new file mode 100644 index 0000000..fba011d --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h @@ -0,0 +1,2919 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/**************************************************************** + * Auto generated by DE, please DO NOT modify this file directly. + *****************************************************************/ +#ifndef MT_SPM_REG +#define MT_SPM_REG + +#include "pcm_def.h" +#include <platform_def.h> +#include "sleep_def.h" + +/************************************** + * Define and Declare + **************************************/ +#define POWERON_CONFIG_EN (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) +#define SPM_CLK_CON (SPM_BASE + 0x00C) +#define SPM_CLK_SETTLE (SPM_BASE + 0x010) +#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) +#define PCM_CON0 (SPM_BASE + 0x018) +#define PCM_CON1 (SPM_BASE + 0x01C) +#define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) +#define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) +#define PCM_REG_DATA_INI (SPM_BASE + 0x028) +#define PCM_PWR_IO_EN (SPM_BASE + 0x02C) +#define PCM_TIMER_VAL (SPM_BASE + 0x030) +#define PCM_WDT_VAL (SPM_BASE + 0x034) +#define SPM_SRC6_MASK (SPM_BASE + 0x038) +#define SPM_SW_RST_CON (SPM_BASE + 0x040) +#define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) +#define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) +#define VS1_PSR_MASK_B (SPM_BASE + 0x04C) +#define VS2_PSR_MASK_B (SPM_BASE + 0x050) +#define MD32_CLK_CON (SPM_BASE + 0x084) +#define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) +#define SPM_SWINT (SPM_BASE + 0x08C) +#define SPM_SWINT_SET (SPM_BASE + 0x090) +#define SPM_SWINT_CLR (SPM_BASE + 0x094) +#define SPM_SCP_MAILBOX (SPM_BASE + 0x098) +#define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) +#define SPM_TWAM_CON (SPM_BASE + 0x0A0) +#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) +#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) +#define SPM_SCP_IRQ (SPM_BASE + 0x0AC) +#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) +#define SPM_IRQ_MASK (SPM_BASE + 0x0B4) +#define SPM_SRC_REQ (SPM_BASE + 0x0B8) +#define SPM_SRC_MASK (SPM_BASE + 0x0BC) +#define SPM_SRC2_MASK (SPM_BASE + 0x0C0) +#define SPM_SRC3_MASK (SPM_BASE + 0x0C4) +#define SPM_SRC4_MASK (SPM_BASE + 0x0C8) +#define SPM_SRC5_MASK (SPM_BASE + 0x0CC) +#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0D0) +#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0D4) +#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0D8) +#define SCP_CLK_CON (SPM_BASE + 0x0DC) +#define PCM_DEBUG_CON (SPM_BASE + 0x0E0) +#define AHB_BUS_CON (SPM_BASE + 0x0E4) +#define DDR_EN_DBC_CON0 (SPM_BASE + 0x0E8) +#define DDR_EN_DBC_CON1 (SPM_BASE + 0x0EC) +#define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0F0) +#define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0F4) +#define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0F8) +#define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0FC) +#define PCM_REG0_DATA (SPM_BASE + 0x100) +#define PCM_REG2_DATA (SPM_BASE + 0x104) +#define PCM_REG6_DATA (SPM_BASE + 0x108) +#define PCM_REG7_DATA (SPM_BASE + 0x10C) +#define PCM_REG13_DATA (SPM_BASE + 0x110) +#define SRC_REQ_STA_0 (SPM_BASE + 0x114) +#define SRC_REQ_STA_1 (SPM_BASE + 0x118) +#define SRC_REQ_STA_2 (SPM_BASE + 0x11C) +#define PCM_TIMER_OUT (SPM_BASE + 0x120) +#define PCM_WDT_OUT (SPM_BASE + 0x124) +#define SPM_IRQ_STA (SPM_BASE + 0x128) +#define SRC_REQ_STA_4 (SPM_BASE + 0x12C) +#define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130) +#define MD32PCM_EVENT_STA (SPM_BASE + 0x134) +#define SPM_WAKEUP_STA (SPM_BASE + 0x138) +#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x13C) +#define SPM_WAKEUP_MISC (SPM_BASE + 0x140) +#define MM_DVFS_HALT (SPM_BASE + 0x144) +#define BUS_PROTECT_RDY (SPM_BASE + 0x150) +#define BUS_PROTECT1_RDY (SPM_BASE + 0x154) +#define BUS_PROTECT2_RDY (SPM_BASE + 0x158) +#define BUS_PROTECT3_RDY (SPM_BASE + 0x15C) +#define SUBSYS_IDLE_STA (SPM_BASE + 0x160) +#define PCM_STA (SPM_BASE + 0x164) +#define SRC_REQ_STA_3 (SPM_BASE + 0x168) +#define PWR_STATUS (SPM_BASE + 0x16C) +#define PWR_STATUS_2ND (SPM_BASE + 0x170) +#define CPU_PWR_STATUS (SPM_BASE + 0x174) +#define OTHER_PWR_STATUS (SPM_BASE + 0x178) +#define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) +#define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) +#define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) +#define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) +#define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) +#define MD32PCM_STA (SPM_BASE + 0x190) +#define MD32PCM_PC (SPM_BASE + 0x194) +#define DVFSRC_EVENT_STA (SPM_BASE + 0x1A4) +#define BUS_PROTECT4_RDY (SPM_BASE + 0x1A8) +#define BUS_PROTECT5_RDY (SPM_BASE + 0x1AC) +#define BUS_PROTECT6_RDY (SPM_BASE + 0x1B0) +#define BUS_PROTECT7_RDY (SPM_BASE + 0x1B4) +#define BUS_PROTECT8_RDY (SPM_BASE + 0x1B8) +#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) +#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) +#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) +#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) +#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) +#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) +#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) +#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) +#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) +#define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) +#define SPM_DVFS_STA (SPM_BASE + 0x1F8) +#define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) +#define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x200) +#define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x204) +#define SPM_CPU0_PWR_CON (SPM_BASE + 0x208) +#define SPM_CPU1_PWR_CON (SPM_BASE + 0x20C) +#define SPM_CPU2_PWR_CON (SPM_BASE + 0x210) +#define SPM_CPU3_PWR_CON (SPM_BASE + 0x214) +#define SPM_CPU4_PWR_CON (SPM_BASE + 0x218) +#define SPM_CPU5_PWR_CON (SPM_BASE + 0x21C) +#define SPM_CPU6_PWR_CON (SPM_BASE + 0x220) +#define SPM_CPU7_PWR_CON (SPM_BASE + 0x224) +#define ARMPLL_CLK_CON (SPM_BASE + 0x22C) +#define MCUSYS_IDLE_STA (SPM_BASE + 0x230) +#define GIC_WAKEUP_STA (SPM_BASE + 0x234) +#define CPU_SPARE_CON (SPM_BASE + 0x238) +#define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) +#define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) +#define ARMPLL_CLK_SEL (SPM_BASE + 0x244) +#define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) +#define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) +#define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) +#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x260) +#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x264) +#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x268) +#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x26C) +#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x270) +#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x274) +#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x278) +#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x27C) +#define MP0_CPU0_WFI_EN (SPM_BASE + 0x280) +#define MP0_CPU1_WFI_EN (SPM_BASE + 0x284) +#define MP0_CPU2_WFI_EN (SPM_BASE + 0x288) +#define MP0_CPU3_WFI_EN (SPM_BASE + 0x28C) +#define MP0_CPU4_WFI_EN (SPM_BASE + 0x290) +#define MP0_CPU5_WFI_EN (SPM_BASE + 0x294) +#define MP0_CPU6_WFI_EN (SPM_BASE + 0x298) +#define MP0_CPU7_WFI_EN (SPM_BASE + 0x29C) +#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) +#define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) +#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) +#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) +#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) +#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) +#define SW2SPM_INT (SPM_BASE + 0x2E0) +#define SW2SPM_INT_SET (SPM_BASE + 0x2E4) +#define SW2SPM_INT_CLR (SPM_BASE + 0x2E8) +#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) +#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) +#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) +#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) +#define SW2SPM_CFG (SPM_BASE + 0x2FC) +#define MD1_PWR_CON (SPM_BASE + 0x300) +#define CONN_PWR_CON (SPM_BASE + 0x304) +#define MFG0_PWR_CON (SPM_BASE + 0x308) +#define MFG1_PWR_CON (SPM_BASE + 0x30C) +#define MFG2_PWR_CON (SPM_BASE + 0x310) +#define MFG3_PWR_CON (SPM_BASE + 0x314) +#define MFG4_PWR_CON (SPM_BASE + 0x318) +#define MFG5_PWR_CON (SPM_BASE + 0x31C) +#define MFG6_PWR_CON (SPM_BASE + 0x320) +#define IFR_PWR_CON (SPM_BASE + 0x324) +#define IFR_SUB_PWR_CON (SPM_BASE + 0x328) +#define DPY_PWR_CON (SPM_BASE + 0x32C) +#define ISP_PWR_CON (SPM_BASE + 0x330) +#define ISP2_PWR_CON (SPM_BASE + 0x334) +#define IPE_PWR_CON (SPM_BASE + 0x338) +#define VDE_PWR_CON (SPM_BASE + 0x33C) +#define VDE2_PWR_CON (SPM_BASE + 0x340) +#define VEN_PWR_CON (SPM_BASE + 0x344) +#define VEN_CORE1_PWR_CON (SPM_BASE + 0x348) +#define MDP_PWR_CON (SPM_BASE + 0x34C) +#define DIS_PWR_CON (SPM_BASE + 0x350) +#define AUDIO_PWR_CON (SPM_BASE + 0x354) +#define ADSP_PWR_CON (SPM_BASE + 0x358) +#define CAM_PWR_CON (SPM_BASE + 0x35C) +#define CAM_RAWA_PWR_CON (SPM_BASE + 0x360) +#define CAM_RAWB_PWR_CON (SPM_BASE + 0x364) +#define CAM_RAWC_PWR_CON (SPM_BASE + 0x368) +#define SYSRAM_CON (SPM_BASE + 0x36C) +#define SYSROM_CON (SPM_BASE + 0x370) +#define SSPM_SRAM_CON (SPM_BASE + 0x374) +#define SCP_SRAM_CON (SPM_BASE + 0x378) +#define DPY_SHU_SRAM_CON (SPM_BASE + 0x37C) +#define UFS_SRAM_CON (SPM_BASE + 0x380) +#define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x384) +#define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x388) +#define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x38C) +#define USB_SRAM_CON (SPM_BASE + 0x390) +#define DUMMY_SRAM_CON (SPM_BASE + 0x394) +#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x398) +#define EXT_BUCK_ISO (SPM_BASE + 0x39C) +#define DXCC_SRAM_CON (SPM_BASE + 0x3A0) +#define MSDC_SRAM_CON (SPM_BASE + 0x3A4) +#define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3A8) +#define DP_TX_PWR_CON (SPM_BASE + 0x3AC) +#define DPMAIF_SRAM_CON (SPM_BASE + 0x3B0) +#define DPY_SHU2_SRAM_CON (SPM_BASE + 0x3B4) +#define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x3B8) +#define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x3BC) +#define MCUPM_SRAM_CON (SPM_BASE + 0x3C0) +#define DPY2_PWR_CON (SPM_BASE + 0x3C4) +#define PERI_PWR_CON (SPM_BASE + 0x3C8) +#define SPM_MEM_CK_SEL (SPM_BASE + 0x400) +#define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) +#define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) +#define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) +#define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) +#define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) +#define SPM_EMI_BW_MODE (SPM_BASE + 0x418) +#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x41C) +#define ULPOSC_CON (SPM_BASE + 0x420) +#define SPM2MM_CON (SPM_BASE + 0x424) +#define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x428) +#define SPM2MCUPM_CON (SPM_BASE + 0x42C) +#define AP_MDSRC_REQ (SPM_BASE + 0x430) +#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x434) +#define SPM2MD_DVFS_CON (SPM_BASE + 0x438) +#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) +#define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x440) +#define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x444) +#define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x448) +#define SPM_PLL_CON (SPM_BASE + 0x44C) +#define CPU_DVFS_REQ (SPM_BASE + 0x450) +#define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x454) +#define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x458) +#define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x45C) +#define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x460) +#define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x464) +#define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x468) +#define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x46C) +#define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x470) +#define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x474) +#define RELAY_DVFS_LEVEL (SPM_BASE + 0x478) +#define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x480) +#define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x484) +#define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x488) +#define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x48C) +#define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x490) +#define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x494) +#define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x498) +#define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x49C) +#define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x4A0) +#define SPM_DVFS_LEVEL (SPM_BASE + 0x4A4) +#define SPM_CIRQ_CON (SPM_BASE + 0x4A8) +#define SPM_DVFS_MISC (SPM_BASE + 0x4AC) +#define SPM_VS1_VS2_RC_CON (SPM_BASE + 0x4B0) +#define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4B4) +#define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4B8) +#define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4BC) +#define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4C0) +#define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4C4) +#define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4C8) +#define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4CC) +#define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4D0) +#define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4D4) +#define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4D8) +#define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4DC) +#define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4E0) +#define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4E4) +#define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4E8) +#define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4EC) +#define SPM_CG_CHECK_CON (SPM_BASE + 0x4F0) +#define SPM_SRC_RDY_STA (SPM_BASE + 0x4F4) +#define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4F8) +#define SPM_FORCE_DVFS (SPM_BASE + 0x4FC) +#define SRCLKEN_RC_CFG (SPM_BASE + 0x500) +#define RC_CENTRAL_CFG1 (SPM_BASE + 0x504) +#define RC_CENTRAL_CFG2 (SPM_BASE + 0x508) +#define RC_CMD_ARB_CFG (SPM_BASE + 0x50C) +#define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510) +#define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514) +#define RC_DCXO_FPM_CFG (SPM_BASE + 0x518) +#define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C) +#define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520) +#define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524) +#define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528) +#define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C) +#define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530) +#define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534) +#define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538) +#define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C) +#define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540) +#define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544) +#define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548) +#define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C) +#define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550) +#define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554) +#define RC_CENTRAL_CFG4 (SPM_BASE + 0x558) +#define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560) +#define RC_DEBUG_CFG (SPM_BASE + 0x564) +#define RC_MISC_0 (SPM_BASE + 0x5B4) +#define RC_SPM_CTRL (SPM_BASE + 0x5B8) +#define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC) +#define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0) +#define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4) +#define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8) +#define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC) +#define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0) +#define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4) +#define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8) +#define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC) +#define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0) +#define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4) +#define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC) +#define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0) +#define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4) +#define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8) +#define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC) +#define SPM_SW_FLAG_0 (SPM_BASE + 0x600) +#define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) +#define SPM_SW_FLAG_1 (SPM_BASE + 0x608) +#define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) +#define SPM_SW_RSV_0 (SPM_BASE + 0x610) +#define SPM_SW_RSV_1 (SPM_BASE + 0x614) +#define SPM_SW_RSV_2 (SPM_BASE + 0x618) +#define SPM_SW_RSV_3 (SPM_BASE + 0x61C) +#define SPM_SW_RSV_4 (SPM_BASE + 0x620) +#define SPM_SW_RSV_5 (SPM_BASE + 0x624) +#define SPM_SW_RSV_6 (SPM_BASE + 0x628) +#define SPM_SW_RSV_7 (SPM_BASE + 0x62C) +#define SPM_SW_RSV_8 (SPM_BASE + 0x630) +#define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) +#define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) +#define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) +#define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) +#define SPM_RSV_CON_0 (SPM_BASE + 0x650) +#define SPM_RSV_CON_1 (SPM_BASE + 0x654) +#define SPM_RSV_STA_0 (SPM_BASE + 0x658) +#define SPM_RSV_STA_1 (SPM_BASE + 0x65C) +#define SPM_SPARE_CON (SPM_BASE + 0x660) +#define SPM_SPARE_CON_SET (SPM_BASE + 0x664) +#define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) +#define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) +#define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) +#define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) +#define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) +#define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) +#define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) +#define SPARE_ACK_MASK (SPM_BASE + 0x684) +#define SPM_CROSS_WAKE_M04_REQ (SPM_BASE + 0x688) +#define SPM_DV_CON_0 (SPM_BASE + 0x68C) +#define SPM_DV_CON_1 (SPM_BASE + 0x690) +#define SPM_DV_STA (SPM_BASE + 0x694) +#define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) +#define SPM_SEMA_M0 (SPM_BASE + 0x69C) +#define SPM_SEMA_M1 (SPM_BASE + 0x6A0) +#define SPM_SEMA_M2 (SPM_BASE + 0x6A4) +#define SPM_SEMA_M3 (SPM_BASE + 0x6A8) +#define SPM_SEMA_M4 (SPM_BASE + 0x6AC) +#define SPM_SEMA_M5 (SPM_BASE + 0x6B0) +#define SPM_SEMA_M6 (SPM_BASE + 0x6B4) +#define SPM_SEMA_M7 (SPM_BASE + 0x6B8) +#define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) +#define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) +#define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) +#define SPM_MD32_IRQ (SPM_BASE + 0x6C8) +#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) +#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) +#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) +#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) +#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) +#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) +#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) +#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) +#define UFS_PSRI_SW (SPM_BASE + 0x6EC) +#define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0) +#define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4) +#define SPM_AP_SEMA (SPM_BASE + 0x6F8) +#define SPM_SPM_SEMA (SPM_BASE + 0x6FC) +#define SPM_DVFS_CON (SPM_BASE + 0x700) +#define SPM_DVFS_CON_STA (SPM_BASE + 0x704) +#define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) +#define SPM_DVFS_CMD0 (SPM_BASE + 0x710) +#define SPM_DVFS_CMD1 (SPM_BASE + 0x714) +#define SPM_DVFS_CMD2 (SPM_BASE + 0x718) +#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) +#define SPM_DVFS_CMD4 (SPM_BASE + 0x720) +#define SPM_DVFS_CMD5 (SPM_BASE + 0x724) +#define SPM_DVFS_CMD6 (SPM_BASE + 0x728) +#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) +#define SPM_DVFS_CMD8 (SPM_BASE + 0x730) +#define SPM_DVFS_CMD9 (SPM_BASE + 0x734) +#define SPM_DVFS_CMD10 (SPM_BASE + 0x738) +#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) +#define SPM_DVFS_CMD12 (SPM_BASE + 0x740) +#define SPM_DVFS_CMD13 (SPM_BASE + 0x744) +#define SPM_DVFS_CMD14 (SPM_BASE + 0x748) +#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) +#define SPM_DVFS_CMD16 (SPM_BASE + 0x750) +#define SPM_DVFS_CMD17 (SPM_BASE + 0x754) +#define SPM_DVFS_CMD18 (SPM_BASE + 0x758) +#define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) +#define SPM_DVFS_CMD20 (SPM_BASE + 0x760) +#define SPM_DVFS_CMD21 (SPM_BASE + 0x764) +#define SPM_DVFS_CMD22 (SPM_BASE + 0x768) +#define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) +#define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) +#define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) +#define SYS_TIMER_START_L (SPM_BASE + 0x778) +#define SYS_TIMER_START_H (SPM_BASE + 0x77C) +#define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) +#define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) +#define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) +#define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) +#define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) +#define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) +#define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) +#define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) +#define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) +#define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) +#define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) +#define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) +#define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) +#define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) +#define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) +#define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) +#define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) +#define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) +#define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) +#define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) +#define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) +#define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) +#define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) +#define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) +#define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) +#define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) +#define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) +#define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) +#define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) +#define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) +#define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) +#define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) +#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) +#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) +#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) +#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) +#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) +#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) +#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) +#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) +#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) +#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) +#define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) +#define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) +#define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) +#define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) +#define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) +#define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) +#define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) +#define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) +#define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) +#define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) +#define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) +#define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) +#define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870) +#define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874) +#define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878) +#define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) +#define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) +#define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) +#define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) +#define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) +#define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) +#define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8) +#define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) +#define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) +#define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) +#define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) +#define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) +#define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) +#define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) +#define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920) +#define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924) +#define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928) +#define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C) +#define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930) +#define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934) +#define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940) +#define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944) +#define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948) +#define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C) +#define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950) +#define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954) +#define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) +#define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964) +#define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968) +#define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C) +#define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970) +#define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974) +#define SPM_COUNTER_0 (SPM_BASE + 0x978) +#define SPM_COUNTER_1 (SPM_BASE + 0x97C) +#define SPM_COUNTER_2 (SPM_BASE + 0x980) +#define SYS_TIMER_CON (SPM_BASE + 0x98C) +#define RC_FSM_STA_0 (SPM_BASE + 0xE00) +#define RC_CMD_STA_0 (SPM_BASE + 0xE04) +#define RC_CMD_STA_1 (SPM_BASE + 0xE08) +#define RC_SPI_STA_0 (SPM_BASE + 0xE0C) +#define RC_PI_PO_STA_0 (SPM_BASE + 0xE10) +#define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14) +#define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C) +#define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20) +#define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24) +#define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28) +#define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C) +#define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30) +#define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34) +#define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38) +#define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C) +#define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40) +#define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44) +#define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48) +#define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C) +#define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50) +#define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54) +#define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C) +#define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60) +#define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64) +#define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C) +#define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70) +#define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74) +#define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78) +#define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C) +#define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80) +#define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84) +#define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88) +#define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C) +#define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90) +#define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94) +#define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98) +#define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C) +#define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0) +#define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4) +#define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8) +#define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC) +#define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0) +#define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4) +#define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8) +#define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC) +#define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0) +#define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4) +#define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8) +#define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC) +#define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0) +#define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4) +#define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8) +#define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC) +#define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0) +#define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4) +#define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8) +#define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC) +#define PMSR_LAST_DAT (SPM_BASE + 0xF00) +#define PMSR_LAST_CNT (SPM_BASE + 0xF04) +#define PMSR_LAST_ACK (SPM_BASE + 0xF08) +#define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10) +#define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14) +#define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18) +#define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C) +#define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20) +#define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24) +#define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28) +#define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C) +#define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30) +#define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34) +#define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C) +#define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40) +#define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8) +#define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC) +#define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0) +#define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4) +#define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8) +#define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC) +#define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0) +#define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4) +#define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8) +#define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC) +#define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0) +#define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4) +#define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8) +#define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC) +#define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0) +#define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ +#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ +/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ +#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */ +#define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */ +#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ +#define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ +#define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */ +#define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */ +#define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ +#define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */ +#define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */ +#define SCP_DCM_EN_LSB (1U << 15) /* 1b */ +#define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */ +#define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */ +/* SPM_CLK_SETTLE (0x10006000+0x010) */ +#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ +/* SPM_AP_STANDBY_CON (0x10006000+0x014) */ +#define REG_WFI_OP_LSB (1U << 0) /* 1b */ +#define REG_WFI_TYPE_LSB (1U << 1) /* 1b */ +#define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ +#define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */ +#define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ +#define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ +#define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ +#define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ +#define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* PCM_CON1 (0x10006000+0x01C) */ +#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ +#define RG_IM_SLEEP_LSB (1U << 1) /* 1b */ +#define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */ +#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ +#define RG_IM_PDN_LSB (1U << 4) /* 1b */ +#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ +#define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ +#define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ +#define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */ +#define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_POWER_ON_VAL2 (0x10006000+0x020) */ +#define POWER_ON_VAL2_LSB (1U << 0) /* 32b */ +/* SPM_POWER_ON_VAL3 (0x10006000+0x024) */ +#define POWER_ON_VAL3_LSB (1U << 0) /* 32b */ +/* PCM_REG_DATA_INI (0x10006000+0x028) */ +#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ +/* PCM_PWR_IO_EN (0x10006000+0x02C) */ +#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ +#define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */ +/* PCM_TIMER_VAL (0x10006000+0x030) */ +#define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ +/* PCM_WDT_VAL (0x10006000+0x034) */ +#define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */ +/* SPM_SRC6_MASK (0x10006000+0x038) */ +#define REG_DPMAIF_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ +#define REG_DPMAIF_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ +#define REG_DPMAIF_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ +#define REG_DPMAIF_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define REG_DPMAIF_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ +/* SPM_SW_RST_CON (0x10006000+0x040) */ +#define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */ +#define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_SW_RST_CON_SET (0x10006000+0x044) */ +#define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */ +#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* SPM_SW_RST_CON_CLR (0x10006000+0x048) */ +#define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */ +#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */ +/* VS1_PSR_MASK_B (0x10006000+0x04C) */ +#define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ +#define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ +/* VS2_PSR_MASK_B (0x10006000+0x050) */ +#define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ +#define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ +#define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */ +/* MD32_CLK_CON (0x10006000+0x084) */ +#define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */ +#define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */ +/* SPM_SRAM_RSV_CON (0x10006000+0x088) */ +#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ +/* SPM_SWINT (0x10006000+0x08C) */ +#define SPM_SWINT_LSB (1U << 0) /* 32b */ +/* SPM_SWINT_SET (0x10006000+0x090) */ +#define SPM_SWINT_SET_LSB (1U << 0) /* 32b */ +/* SPM_SWINT_CLR (0x10006000+0x094) */ +#define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */ +/* SPM_SCP_MAILBOX (0x10006000+0x098) */ +#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ +/* SCP_SPM_MAILBOX (0x10006000+0x09C) */ +#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CON (0x10006000+0x0A0) */ +#define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */ +#define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */ +#define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */ +#define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */ +#define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */ +#define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */ +#define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */ +#define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */ +/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ +#define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ +#define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */ +#define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */ +#define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */ +#define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */ +/* SPM_SCP_IRQ (0x10006000+0x0AC) */ +#define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */ +#define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ +/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ +#define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */ +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */ +/* SPM_SRC_REQ (0x10006000+0x0B8) */ +#define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ +#define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */ +#define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ +#define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ +#define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */ +#define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */ +#define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */ +#define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */ +#define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */ +#define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */ +/* SPM_SRC_MASK (0x10006000+0x0BC) */ +#define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */ +#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */ +#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */ +#define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */ +#define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */ +#define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */ +#define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */ +#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */ +#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */ +#define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */ +#define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */ +#define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */ +#define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ +#define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */ +#define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */ +#define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ +#define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */ +#define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */ +#define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */ +#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */ +#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */ +#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ +#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ +#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ +#define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ +#define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ +#define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ +#define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ +#define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ +/* SPM_SRC2_MASK (0x10006000+0x0C0) */ +#define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ +#define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ +#define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ +#define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ +#define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ +#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ +#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ +#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ +#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ +#define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */ +#define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ +#define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ +#define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */ +#define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */ +#define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */ +#define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ +#define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ +#define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */ +#define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */ +#define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ +#define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ +#define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ +#define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ +#define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ +#define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ +#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */ +#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ +#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ +#define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ +/* SPM_SRC3_MASK (0x10006000+0x0C4) */ +#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */ +#define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */ +#define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */ +#define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */ +#define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */ +#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */ +#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */ +#define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */ +#define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */ +#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */ +#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */ +#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */ +#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */ +#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */ +#define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ +#define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */ +#define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */ +#define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */ +#define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */ +#define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ +#define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ +#define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ +#define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ +#define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ +#define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ +#define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ +/* SPM_SRC4_MASK (0x10006000+0x0C8) */ +#define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */ +#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */ +#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */ +#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */ +#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */ +#define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */ +#define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */ +#define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */ +#define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ +#define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */ +#define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */ +#define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */ +/* SPM_SRC5_MASK (0x10006000+0x0CC) */ +#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */ +#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */ +#define REG_MSDC2_SRCCLKENA_MASK_B_LSB (1U << 18) /* 1b */ +#define REG_MSDC2_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ +#define REG_MSDC2_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ +#define REG_MSDC2_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ +#define REG_MSDC2_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ +#define REG_PCIE_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ +#define REG_PCIE_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ +#define REG_PCIE_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ +#define REG_PCIE_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ +#define REG_PCIE_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ +#define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */ +#define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */ +#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ +/* SCP_CLK_CON (0x10006000+0x0DC) */ +#define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ +#define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */ +#define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */ +#define SCP_SLP_REQ_LSB (1U << 3) /* 1b */ +#define SCP_SLP_ACK_LSB (1U << 4) /* 1b */ +/* PCM_DEBUG_CON (0x10006000+0x0E0) */ +#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ +/* AHB_BUS_CON (0x10006000+0x0E4) */ +#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ +#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ +/* DDR_EN_DBC_CON0 (0x10006000+0x0E8) */ +#define REG_ALL_DDR_EN_DBC_LEN_LSB (1U << 0) /* 10b */ +#define REG_MD_DDR_EN_0_DBC_LEN_LSB (1U << 10) /* 10b */ +#define REG_HW_S1_DBC_LEN_LSB (1U << 20) /* 10b */ +/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */ +#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */ +#define REG_MD_DDR_EN_0_DBC_EN_LSB (1U << 1) /* 1b */ +#define REG_HW_S1_DBC_EN_LSB (1U << 2) /* 1b */ +/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */ +#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */ +#define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */ +#define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */ +#define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */ +#define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */ +#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */ +#define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */ +#define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */ +#define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */ +#define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */ +#define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ +#define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ +#define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ +#define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ +#define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ +#define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ +#define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ +#define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ +#define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ +#define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ +#define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ +#define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ +#define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ +#define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ +#define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ +#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */ +#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */ +#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */ +#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */ +#define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */ +#define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ +#define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */ +/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */ +#define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ +#define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ +#define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ +#define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ +#define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */ +#define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ +#define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ +#define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ +#define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ +#define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */ +#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ +#define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ +#define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ +#define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ +#define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ +#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ +#define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ +#define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ +#define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ +#define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ +#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ +#define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ +#define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ +#define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ +#define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ +#define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ +#define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */ +#define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */ +#define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */ +#define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */ +#define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ +/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */ +#define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ +#define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */ +#define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */ +#define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */ +/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */ +#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ +#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */ +#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */ +#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */ +#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */ +#define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */ +#define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB (1U << 13) /* 1b */ +#define REG_MSDC2_INFRA_ACK_MASK_LSB (1U << 14) /* 1b */ +#define REG_MSDC2_APSRC_ACK_MASK_LSB (1U << 15) /* 1b */ +#define REG_MSDC2_VRF18_ACK_MASK_LSB (1U << 16) /* 1b */ +#define REG_MSDC2_DDR_EN_ACK_MASK_LSB (1U << 17) /* 1b */ +#define REG_PCIE_SRCCLKENA_ACK_MASK_LSB (1U << 18) /* 1b */ +#define REG_PCIE_INFRA_ACK_MASK_LSB (1U << 19) /* 1b */ +#define REG_PCIE_APSRC_ACK_MASK_LSB (1U << 20) /* 1b */ +#define REG_PCIE_VRF18_ACK_MASK_LSB (1U << 21) /* 1b */ +#define REG_PCIE_DDR_EN_ACK_MASK_LSB (1U << 22) /* 1b */ +#define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB (1U << 23) /* 1b */ +#define REG_DPMAIF_INFRA_ACK_MASK_LSB (1U << 24) /* 1b */ +#define REG_DPMAIF_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ +#define REG_DPMAIF_VRF18_ACK_MASK_LSB (1U << 26) /* 1b */ +#define REG_DPMAIF_DDR_EN_ACK_MASK_LSB (1U << 27) /* 1b */ +/* PCM_REG0_DATA (0x10006000+0x100) */ +#define PCM_REG0_RF_LSB (1U << 0) /* 32b */ +/* PCM_REG2_DATA (0x10006000+0x104) */ +#define PCM_REG2_RF_LSB (1U << 0) /* 32b */ +/* PCM_REG6_DATA (0x10006000+0x108) */ +#define PCM_REG6_RF_LSB (1U << 0) /* 32b */ +/* PCM_REG7_DATA (0x10006000+0x10C) */ +#define PCM_REG7_RF_LSB (1U << 0) /* 32b */ +/* PCM_REG13_DATA (0x10006000+0x110) */ +#define PCM_REG13_RF_LSB (1U << 0) /* 32b */ +/* SRC_REQ_STA_0 (0x10006000+0x114) */ +#define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */ +#define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */ +#define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */ +#define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */ +#define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */ +#define MD_DDR_EN_0_LSB (1U << 5) /* 1b */ +#define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */ +#define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */ +#define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */ +#define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */ +#define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */ +#define MD_DDR_EN_1_LSB (1U << 11) /* 1b */ +#define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */ +#define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */ +#define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */ +#define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */ +#define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */ +#define CONN_DDR_EN_LSB (1U << 17) /* 1b */ +#define SRCCLKENI_LSB (1U << 18) /* 3b */ +#define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */ +#define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */ +#define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */ +#define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */ +#define MD32_DDR_EN_LSB (1U << 25) /* 1b */ +#define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */ +#define DISP0_DDR_EN_LSB (1U << 27) /* 1b */ +#define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */ +#define DISP1_DDR_EN_LSB (1U << 29) /* 1b */ +#define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */ +/* SRC_REQ_STA_1 (0x10006000+0x118) */ +#define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */ +#define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */ +#define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */ +#define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */ +#define SCP_DDR_EN_LSB (1U << 4) /* 1b */ +#define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */ +#define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */ +#define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */ +#define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */ +#define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */ +#define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */ +#define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */ +#define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */ +#define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */ +#define UFS_DDR_EN_LSB (1U << 14) /* 1b */ +#define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */ +#define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */ +#define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */ +#define GCE_DDR_EN_LSB (1U << 18) /* 1b */ +#define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */ +#define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */ +#define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */ +#define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */ +#define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */ +#define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */ +#define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */ +#define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */ +#define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */ +#define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */ +#define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */ +#define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */ +/* SRC_REQ_STA_2 (0x10006000+0x11C) */ +#define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */ +#define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */ +#define SW2SPM_INT_LSB (1U << 11) /* 4b */ +#define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */ +#define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */ +#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */ +#define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */ +#define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */ +#define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */ +#define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */ +#define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */ +#define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */ +#define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */ +#define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */ +#define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */ +#define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */ +/* PCM_TIMER_OUT (0x10006000+0x120) */ +#define PCM_TIMER_LSB (1U << 0) /* 32b */ +/* PCM_WDT_OUT (0x10006000+0x124) */ +#define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */ +/* SPM_IRQ_STA (0x10006000+0x128) */ +#define TWAM_IRQ_LSB (1U << 2) /* 1b */ +#define PCM_IRQ_LSB (1U << 3) /* 1b */ +/* SRC_REQ_STA_4 (0x10006000+0x12C) */ +#define APU_SRCCLKENA_LSB (1U << 0) /* 1b */ +#define APU_INFRA_REQ_LSB (1U << 1) /* 1b */ +#define APU_APSRC_REQ_LSB (1U << 2) /* 1b */ +#define APU_VRF18_REQ_LSB (1U << 3) /* 1b */ +#define APU_DDR_EN_LSB (1U << 4) /* 1b */ +#define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */ +#define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */ +#define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */ +#define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */ +#define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */ +#define MSDC2_SRCCLKENA_LSB (1U << 10) /* 1b */ +#define MSDC2_INFRA_REQ_LSB (1U << 11) /* 1b */ +#define MSDC2_APSRC_REQ_LSB (1U << 12) /* 1b */ +#define MSDC2_VRF18_REQ_LSB (1U << 13) /* 1b */ +#define MSDC2_DDR_EN_LSB (1U << 14) /* 1b */ +#define PCIE_SRCCLKENA_LSB (1U << 15) /* 1b */ +#define PCIE_INFRA_REQ_LSB (1U << 16) /* 1b */ +#define PCIE_APSRC_REQ_LSB (1U << 17) /* 1b */ +#define PCIE_VRF18_REQ_LSB (1U << 18) /* 1b */ +#define PCIE_DDR_EN_LSB (1U << 19) /* 1b */ +#define DPMAIF_SRCCLKENA_LSB (1U << 20) /* 1b */ +#define DPMAIF_INFRA_REQ_LSB (1U << 21) /* 1b */ +#define DPMAIF_APSRC_REQ_LSB (1U << 22) /* 1b */ +#define DPMAIF_VRF18_REQ_LSB (1U << 23) /* 1b */ +#define DPMAIF_DDR_EN_LSB (1U << 24) /* 1b */ +/* MD32PCM_WAKEUP_STA (0x10006000+0x130) */ +#define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */ +/* MD32PCM_EVENT_STA (0x10006000+0x134) */ +#define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_STA (0x10006000+0x138) */ +#define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */ +#define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */ +/* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */ +#define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */ +/* SPM_WAKEUP_MISC (0x10006000+0x140) */ +#define GIC_WAKEUP_LSB (1U << 0) /* 10b */ +#define DVFSRC_IRQ_LSB (1U << 16) /* 1b */ +#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */ +#define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */ +#define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */ +#define TWAM_IRQ_B_LSB (1U << 21) /* 1b */ +#define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */ +#define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */ +#define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */ +#define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */ +#define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */ +/* MM_DVFS_HALT (0x10006000+0x144) */ +#define MM_DVFS_HALT_LSB (1U << 0) /* 5b */ +/* BUS_PROTECT_RDY (0x10006000+0x150) */ +#define PROTECT_READY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT1_RDY (0x10006000+0x154) */ +#define PROTECT1_READY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT2_RDY (0x10006000+0x158) */ +#define PROTECT2_READY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT3_RDY (0x10006000+0x15C) */ +#define PROTECT3_READY_LSB (1U << 0) /* 32b */ +/* SUBSYS_IDLE_STA (0x10006000+0x160) */ +#define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */ +/* PCM_STA (0x10006000+0x164) */ +#define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */ +#define EXT_SRC_STA_LSB (1U << 4) /* 3b */ +/* SRC_REQ_STA_3 (0x10006000+0x168) */ +#define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */ +#define F26M_STATE_LSB (1U << 16) /* 1b */ +#define INFRA_STATE_LSB (1U << 17) /* 1b */ +#define APSRC_STATE_LSB (1U << 18) /* 1b */ +#define VRF18_STATE_LSB (1U << 19) /* 1b */ +#define DDR_EN_STATE_LSB (1U << 20) /* 1b */ +#define DVFS_STATE_LSB (1U << 21) /* 1b */ +#define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */ +#define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */ +#define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */ +#define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */ +/* PWR_STATUS (0x10006000+0x16C) */ +#define PWR_STATUS_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_2ND (0x10006000+0x170) */ +#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ +/* CPU_PWR_STATUS (0x10006000+0x174) */ +#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */ +#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */ +#define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */ +/* OTHER_PWR_STATUS (0x10006000+0x178) */ +#define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */ +/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */ +#define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */ +#define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */ +/* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */ +#define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ +#define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */ +/* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */ +#define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */ +#define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */ +/* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */ +#define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */ +#define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */ +/* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */ +#define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */ +#define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */ +/* MD32PCM_STA (0x10006000+0x190) */ +#define MD32PCM_HALT_LSB (1U << 0) /* 1b */ +#define MD32PCM_GATED_LSB (1U << 1) /* 1b */ +/* MD32PCM_PC (0x10006000+0x194) */ +#define MON_PC_LSB (1U << 0) /* 32b */ +/* DVFSRC_EVENT_STA (0x10006000+0x1A4) */ +#define DVFSRC_EVENT_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT4_RDY (0x10006000+0x1A8) */ +#define PROTECT4_READY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT5_RDY (0x10006000+0x1AC) */ +#define PROTECT5_READY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT6_RDY (0x10006000+0x1B0) */ +#define PROTECT6_READY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT7_RDY (0x10006000+0x1B4) */ +#define PROTECT7_READY_LSB (1U << 0) /* 32b */ +/* BUS_PROTECT8_RDY (0x10006000+0x1B8) */ +#define PROTECT8_READY_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */ +#define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */ +#define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */ +#define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */ +#define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */ +#define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */ +#define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */ +#define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */ +#define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */ +/* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */ +#define TWAM_TIMER_LSB (1U << 0) /* 32b */ +/* SPM_CG_CHECK_STA (0x10006000+0x1F4) */ +#define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */ +#define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */ +#define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */ +/* SPM_DVFS_STA (0x10006000+0x1F8) */ +#define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */ +#define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */ +#define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */ +#define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */ +/* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */ +#define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */ +#define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */ +#define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ +#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */ +/* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */ +#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */ +#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */ +#define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ +#define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */ +#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */ +/* SPM_CPU0_PWR_CON (0x10006000+0x208) */ +#define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */ +#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */ +/* SPM_CPU1_PWR_CON (0x10006000+0x20C) */ +#define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */ +#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */ +/* SPM_CPU2_PWR_CON (0x10006000+0x210) */ +#define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */ +#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */ +/* SPM_CPU3_PWR_CON (0x10006000+0x214) */ +#define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */ +#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */ +/* SPM_CPU4_PWR_CON (0x10006000+0x218) */ +#define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */ +#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */ +/* SPM_CPU5_PWR_CON (0x10006000+0x21C) */ +#define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */ +#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */ +/* SPM_CPU6_PWR_CON (0x10006000+0x220) */ +#define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */ +#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */ +/* SPM_CPU7_PWR_CON (0x10006000+0x224) */ +#define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */ +#define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */ +#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */ +#define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */ +#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */ +/* ARMPLL_CLK_CON (0x10006000+0x22C) */ +#define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */ +#define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */ +#define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */ +#define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */ +#define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */ +#define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */ +#define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */ +#define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */ +#define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */ +#define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */ +#define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */ +#define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */ +#define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */ +#define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */ +#define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */ +#define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */ +#define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */ +#define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */ +#define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */ +#define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */ +/* MCUSYS_IDLE_STA (0x10006000+0x230) */ +#define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */ +#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */ +#define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */ +#define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */ +#define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */ +#define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */ +#define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */ +#define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */ +#define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */ +#define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */ +#define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */ +#define WFI_AF_SEL_LSB (1U << 24) /* 8b */ +/* GIC_WAKEUP_STA (0x10006000+0x234) */ +#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */ +/* CPU_SPARE_CON (0x10006000+0x238) */ +#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_SET (0x10006000+0x23C) */ +#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* CPU_SPARE_CON_CLR (0x10006000+0x240) */ +#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* ARMPLL_CLK_SEL (0x10006000+0x244) */ +#define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */ +/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */ +#define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */ +/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */ +#define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */ +/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */ +#define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */ +/* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */ +#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */ +#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */ +#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */ +#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */ +#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */ +#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */ +#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ +/* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */ +#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ +#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ +/* MP0_CPU0_WFI_EN (0x10006000+0x280) */ +#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU1_WFI_EN (0x10006000+0x284) */ +#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU2_WFI_EN (0x10006000+0x288) */ +#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU3_WFI_EN (0x10006000+0x28C) */ +#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU4_WFI_EN (0x10006000+0x290) */ +#define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU5_WFI_EN (0x10006000+0x294) */ +#define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU6_WFI_EN (0x10006000+0x298) */ +#define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */ +/* MP0_CPU7_WFI_EN (0x10006000+0x29C) */ +#define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */ +/* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */ +#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ +/* ROOT_CORE_ADDR (0x10006000+0x2A4) */ +#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */ +#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */ +#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */ +#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */ +#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_INT (0x10006000+0x2E0) */ +#define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_SET (0x10006000+0x2E4) */ +#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ +/* SW2SPM_INT_CLR (0x10006000+0x2E8) */ +#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ +/* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */ +#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */ +#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */ +#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */ +#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* SW2SPM_CFG (0x10006000+0x2FC) */ +#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ +/* MD1_PWR_CON (0x10006000+0x300) */ +#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MD1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* CONN_PWR_CON (0x10006000+0x304) */ +#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CONN_PWR_ON_LSB (1U << 2) /* 1b */ +#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +/* MFG0_PWR_CON (0x10006000+0x308) */ +#define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG0_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* MFG1_PWR_CON (0x10006000+0x30C) */ +#define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG1_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* MFG2_PWR_CON (0x10006000+0x310) */ +#define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG2_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* MFG3_PWR_CON (0x10006000+0x314) */ +#define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG3_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* MFG4_PWR_CON (0x10006000+0x318) */ +#define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG4_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* MFG5_PWR_CON (0x10006000+0x31C) */ +#define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG5_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* MFG6_PWR_CON (0x10006000+0x320) */ +#define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MFG6_PWR_ON_LSB (1U << 2) /* 1b */ +#define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* IFR_PWR_CON (0x10006000+0x324) */ +#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IFR_PWR_ON_LSB (1U << 2) /* 1b */ +#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* IFR_SUB_PWR_CON (0x10006000+0x328) */ +#define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */ +#define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* DPY_PWR_CON (0x10006000+0x32C) */ +#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DPY_PWR_ON_LSB (1U << 2) /* 1b */ +#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* ISP_PWR_CON (0x10006000+0x330) */ +#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ISP_PWR_ON_LSB (1U << 2) /* 1b */ +#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* ISP2_PWR_CON (0x10006000+0x334) */ +#define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ISP2_PWR_ON_LSB (1U << 2) /* 1b */ +#define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* IPE_PWR_CON (0x10006000+0x338) */ +#define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define IPE_PWR_ISO_LSB (1U << 1) /* 1b */ +#define IPE_PWR_ON_LSB (1U << 2) /* 1b */ +#define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VDE_PWR_CON (0x10006000+0x33C) */ +#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VDE_PWR_ON_LSB (1U << 2) /* 1b */ +#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VDE2_PWR_CON (0x10006000+0x340) */ +#define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VDE2_PWR_ON_LSB (1U << 2) /* 1b */ +#define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VEN_PWR_CON (0x10006000+0x344) */ +#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VEN_PWR_ON_LSB (1U << 2) /* 1b */ +#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* VEN_CORE1_PWR_CON (0x10006000+0x348) */ +#define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ +#define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ +#define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* MDP_PWR_CON (0x10006000+0x34C) */ +#define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MDP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MDP_PWR_ON_LSB (1U << 2) /* 1b */ +#define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* DIS_PWR_CON (0x10006000+0x350) */ +#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DIS_PWR_ON_LSB (1U << 2) /* 1b */ +#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* AUDIO_PWR_CON (0x10006000+0x354) */ +#define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */ +#define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */ +#define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* ADSP_PWR_CON (0x10006000+0x358) */ +#define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */ +#define ADSP_PWR_ON_LSB (1U << 2) /* 1b */ +#define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ +#define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ +/* CAM_PWR_CON (0x10006000+0x35C) */ +#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* CAM_RAWA_PWR_CON (0x10006000+0x360) */ +#define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* CAM_RAWB_PWR_CON (0x10006000+0x364) */ +#define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* CAM_RAWC_PWR_CON (0x10006000+0x368) */ +#define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */ +#define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* SYSRAM_CON (0x10006000+0x36C) */ +#define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */ +#define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */ +/* SYSROM_CON (0x10006000+0x370) */ +#define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */ +/* SSPM_SRAM_CON (0x10006000+0x374) */ +#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* SCP_SRAM_CON (0x10006000+0x378) */ +#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* DPY_SHU_SRAM_CON (0x10006000+0x37C) */ +#define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ +#define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */ +/* UFS_SRAM_CON (0x10006000+0x380) */ +#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ +#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ +/* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */ +#define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ +#define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */ +/* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */ +#define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ +#define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */ +/* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */ +#define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ +#define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */ +/* USB_SRAM_CON (0x10006000+0x390) */ +#define USB_SRAM_PDN_LSB (1U << 0) /* 7b */ +/* DUMMY_SRAM_CON (0x10006000+0x394) */ +#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ +#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ +/* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */ +#define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ +#define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ +/* EXT_BUCK_ISO (0x10006000+0x39C) */ +#define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ +#define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ +#define ADSP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ +#define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */ +/* DXCC_SRAM_CON (0x10006000+0x3A0) */ +#define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* MSDC_SRAM_CON (0x10006000+0x3A4) */ +#define MSDC_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MSDC_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MSDC_PWR_ON_LSB (1U << 2) /* 1b */ +#define MSDC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MSDC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MSDC_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MSDC_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MSDC_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MSDC_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ +#define SC_MSDC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +#define SC_MSDC_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ +/* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */ +#define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */ +/* DP_TX_PWR_CON (0x10006000+0x3AC) */ +#define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */ +#define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* DPMAIF_SRAM_CON (0x10006000+0x3B0) */ +#define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */ +#define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ +#define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */ +/* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */ +#define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */ +#define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */ +#define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ +#define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ +#define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */ +/* MCUPM_SRAM_CON (0x10006000+0x3C0) */ +#define MCUPM_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define MCUPM_PWR_ISO_LSB (1U << 1) /* 1b */ +#define MCUPM_PWR_ON_LSB (1U << 2) /* 1b */ +#define MCUPM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define MCUPM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define MCUPM_SRAM_CKISO_LSB (1U << 5) /* 1b */ +#define MCUPM_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ +#define MCUPM_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define MCUPM_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ +#define SC_MCUPM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +#define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ +/* DPY2_PWR_CON (0x10006000+0x3C4) */ +#define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */ +#define DPY2_PWR_ON_LSB (1U << 2) /* 1b */ +#define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* PERI_PWR_CON (0x10006000+0x3C8) */ +#define PERI_PWR_RST_B_LSB (1U << 0) /* 1b */ +#define PERI_PWR_ISO_LSB (1U << 1) /* 1b */ +#define PERI_PWR_ON_LSB (1U << 2) /* 1b */ +#define PERI_PWR_ON_2ND_LSB (1U << 3) /* 1b */ +#define PERI_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ +#define PERI_SRAM_PDN_LSB (1U << 8) /* 1b */ +#define SC_PERI_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ +/* SPM_MEM_CK_SEL (0x10006000+0x400) */ +#define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */ +#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */ +/* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */ +#define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */ +#define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */ +#define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */ +#define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */ +#define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_EMI_BW_MODE (0x10006000+0x418) */ +#define EMI_BW_MODE_LSB (1U << 0) /* 1b */ +#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ +#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ +#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ +/* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */ +#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ +/* ULPOSC_CON (0x10006000+0x420) */ +#define ULPOSC_EN_LSB (1U << 0) /* 1b */ +#define ULPOSC_RST_LSB (1U << 1) /* 1b */ +#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ +#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ +/* SPM2MM_CON (0x10006000+0x424) */ +#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ +#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ +#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ +#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ +#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ +#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */ +#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */ +#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ +#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ +#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ +/* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */ +#define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM2MCUPM_CON (0x10006000+0x42C) */ +#define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */ +#define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */ +/* AP_MDSRC_REQ (0x10006000+0x430) */ +#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ +#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ +#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ +#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ +#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ +#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ +/* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */ +#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ +/* SPM2MD_DVFS_CON (0x10006000+0x438) */ +#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ +/* MD2SPM_DVFS_CON (0x10006000+0x43C) */ +#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ +/* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */ +#define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */ +#define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */ +#define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_PLL_CON (0x10006000+0x44C) */ +#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ +#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ +#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ +#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ +#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ +#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ +#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ +#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ +#define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */ +#define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */ +/* CPU_DVFS_REQ (0x10006000+0x450) */ +#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ +/* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */ +#define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */ +#define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */ +/* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */ +#define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */ +/* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */ +#define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */ +/* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */ +#define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */ +/* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */ +#define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */ +/* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */ +#define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */ +#define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */ +/* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */ +#define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */ +/* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */ +#define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */ +/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */ +#define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */ +#define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */ +#define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */ +#define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */ +#define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */ +#define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */ +/* RELAY_DVFS_LEVEL (0x10006000+0x478) */ +#define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */ +/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */ +#define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */ +#define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */ +#define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */ +#define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */ +#define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */ +#define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */ +#define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */ +#define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */ +#define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */ +#define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */ +#define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */ +#define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */ +#define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */ +#define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */ +#define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */ +#define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */ +#define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */ +#define SW_DMYRD_EN_LSB (1U << 6) /* 2b */ +#define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */ +#define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */ +#define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */ +#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */ +#define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */ +#define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */ +#define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */ +#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */ +#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */ +/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */ +#define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */ +#define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */ +#define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */ +#define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */ +#define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */ +#define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */ +#define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */ +#define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */ +#define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */ +#define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */ +#define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */ +#define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */ +#define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */ +#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */ +#define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */ +#define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */ +#define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */ +#define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */ +#define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */ +/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */ +#define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */ +#define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */ +#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */ +#define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */ +#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */ +#define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */ +#define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */ +#define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */ +#define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */ +#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */ +#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */ +#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */ +#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */ +#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */ +#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */ +#define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */ +#define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */ +#define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */ +#define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */ +#define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */ +#define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */ +#define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */ +#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */ +#define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */ +#define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */ +#define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */ +#define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */ +#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */ +/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */ +#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */ +#define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */ +#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */ +#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */ +#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */ +#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */ +#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */ +#define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */ +#define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */ +#define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */ +#define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */ +/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */ +#define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */ +#define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */ +#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */ +#define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */ +#define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */ +#define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */ +#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */ +#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */ +/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */ +#define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */ +#define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */ +#define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */ +#define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */ +#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */ +#define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */ +#define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */ +#define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */ +#define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */ +#define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */ +#define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */ +#define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */ +#define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */ +#define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */ +#define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */ +#define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */ +#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */ +#define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */ +#define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */ +#define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */ +#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */ +#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */ +/* SPM_DVFS_LEVEL (0x10006000+0x4A4) */ +#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */ +/* SPM_CIRQ_CON (0x10006000+0x4A8) */ +#define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */ +/* SPM_DVFS_MISC (0x10006000+0x4AC) */ +#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ +#define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */ +#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ +#define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */ +#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ +#define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */ +#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */ +#define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */ +#define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */ +#define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */ +/* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */ +#define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */ +#define VS1_INIT_LSB (1U << 2) /* 1b */ +#define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */ +#define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */ +#define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */ +#define VS1_TRIGGER_LSB (1U << 9) /* 1b */ +#define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */ +#define VS2_INIT_LSB (1U << 13) /* 1b */ +#define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */ +#define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */ +#define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */ +#define VS2_TRIGGER_LSB (1U << 23) /* 1b */ +#define VS1_FORCE_LSB (1U << 24) /* 1b */ +#define VS2_FORCE_LSB (1U << 25) /* 1b */ +#define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */ +#define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */ +/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */ +#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */ +#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */ +#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */ +#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */ +#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */ +#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */ +#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */ +#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */ +#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */ +#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */ +#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */ +/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */ +#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */ +#define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */ +#define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */ +/* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */ +#define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */ +/* SPM_CG_CHECK_CON (0x10006000+0x4F0) */ +#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */ +#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */ +#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */ +#define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */ +#define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */ +#define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */ +#define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */ +#define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */ +#define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */ +/* SPM_SRC_RDY_STA (0x10006000+0x4F4) */ +#define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */ +#define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */ +/* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */ +#define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */ +#define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */ +/* SPM_FORCE_DVFS (0x10006000+0x4FC) */ +#define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */ +/* SRCLKEN_RC_CFG (0x10006000+0x500) */ +#define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */ +/* RC_CENTRAL_CFG1 (0x10006000+0x504) */ +#define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */ +/* RC_CENTRAL_CFG2 (0x10006000+0x508) */ +#define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */ +/* RC_CMD_ARB_CFG (0x10006000+0x50C) */ +#define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */ +/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */ +#define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */ +#define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */ +/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */ +#define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */ +#define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */ +/* RC_DCXO_FPM_CFG (0x10006000+0x518) */ +#define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */ +/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */ +#define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */ +/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */ +#define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +#define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */ +#define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */ +/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */ +#define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */ +#define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */ +#define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */ +#define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */ +#define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */ +#define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */ +#define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */ +#define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */ +#define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */ +#define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */ +#define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */ +#define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ +/* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */ +#define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */ +/* RC_CENTRAL_CFG4 (0x10006000+0x558) */ +#define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */ +/* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */ +#define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_CFG (0x10006000+0x564) */ +#define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */ +/* RC_MISC_0 (0x10006000+0x5B4) */ +#define SRCCLKENO_LSB (1U << 0) /* 2b */ +#define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */ +#define RC_VREQ_LSB (1U << 5) /* 1b */ +#define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */ +/* RC_SPM_CTRL (0x10006000+0x5B8) */ +#define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */ +#define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */ +#define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */ +/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */ +#define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */ +#define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */ +/* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */ +#define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */ +#define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */ +#define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */ +#define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */ +#define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */ +#define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */ +#define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */ +#define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */ +#define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */ +#define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */ +#define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */ +#define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */ +#define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */ +#define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */ +#define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */ +/* SPM_SW_FLAG_0 (0x10006000+0x600) */ +#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ +/* SPM_SW_DEBUG_0 (0x10006000+0x604) */ +#define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */ +/* SPM_SW_FLAG_1 (0x10006000+0x608) */ +#define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */ +/* SPM_SW_DEBUG_1 (0x10006000+0x60C) */ +#define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_0 (0x10006000+0x610) */ +#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_1 (0x10006000+0x614) */ +#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_2 (0x10006000+0x618) */ +#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_3 (0x10006000+0x61C) */ +#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_4 (0x10006000+0x620) */ +#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_5 (0x10006000+0x624) */ +#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_6 (0x10006000+0x628) */ +#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_7 (0x10006000+0x62C) */ +#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ +/* SPM_SW_RSV_8 (0x10006000+0x630) */ +#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ +/* SPM_BK_WAKE_EVENT (0x10006000+0x634) */ +#define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */ +/* SPM_BK_VTCXO_DUR (0x10006000+0x638) */ +#define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */ +/* SPM_BK_WAKE_MISC (0x10006000+0x63C) */ +#define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */ +/* SPM_BK_PCM_TIMER (0x10006000+0x640) */ +#define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */ +/* SPM_RSV_CON_0 (0x10006000+0x650) */ +#define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */ +/* SPM_RSV_CON_1 (0x10006000+0x654) */ +#define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */ +/* SPM_RSV_STA_0 (0x10006000+0x658) */ +#define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */ +/* SPM_RSV_STA_1 (0x10006000+0x65C) */ +#define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON (0x10006000+0x660) */ +#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_SET (0x10006000+0x664) */ +#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ +/* SPM_SPARE_CON_CLR (0x10006000+0x668) */ +#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ +/* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */ +#define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 5b */ +#define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 8) /* 5b */ +/* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */ +#define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 5b */ +#define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 8) /* 5b */ +/* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */ +#define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 5b */ +#define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 8) /* 5b */ +/* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */ +#define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 5b */ +#define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 8) /* 5b */ +/* SCP_VCORE_LEVEL (0x10006000+0x67C) */ +#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */ +/* SC_MM_CK_SEL_CON (0x10006000+0x680) */ +#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ +#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ +/* SPARE_ACK_MASK (0x10006000+0x684) */ +#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_CROSS_WAKE_M04_REQ (0x10006000+0x688) */ +#define SPM_CROSS_WAKE_M04_REQ_LSB (1U << 0) /* 5b */ +#define SPM_CROSS_WAKE_M04_CHK_LSB (1U << 8) /* 5b */ +/* SPM_DV_CON_0 (0x10006000+0x68C) */ +#define SPM_DV_CON_0_LSB (1U << 0) /* 32b */ +/* SPM_DV_CON_1 (0x10006000+0x690) */ +#define SPM_DV_CON_1_LSB (1U << 0) /* 32b */ +/* SPM_DV_STA (0x10006000+0x694) */ +#define SPM_DV_STA_LSB (1U << 0) /* 32b */ +/* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */ +#define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */ +/* SPM_SEMA_M0 (0x10006000+0x69C) */ +#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M1 (0x10006000+0x6A0) */ +#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M2 (0x10006000+0x6A4) */ +#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M3 (0x10006000+0x6A8) */ +#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M4 (0x10006000+0x6AC) */ +#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M5 (0x10006000+0x6B0) */ +#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M6 (0x10006000+0x6B4) */ +#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ +/* SPM_SEMA_M7 (0x10006000+0x6B8) */ +#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ +/* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */ +#define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */ +/* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */ +#define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */ +/* SPM_ADSP_IRQ (0x10006000+0x6C4) */ +#define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */ +#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ +/* SPM_MD32_IRQ (0x10006000+0x6C8) */ +#define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */ +#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */ +/* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */ +#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */ +#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */ +#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */ +#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */ +#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */ +#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */ +#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ +/* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */ +#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ +/* UFS_PSRI_SW (0x10006000+0x6EC) */ +#define UFS_PSRI_SW_LSB (1U << 0) /* 1b */ +/* UFS_PSRI_SW_SET (0x10006000+0x6F0) */ +#define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */ +/* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */ +#define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */ +/* SPM_AP_SEMA (0x10006000+0x6F8) */ +#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ +/* SPM_SPM_SEMA (0x10006000+0x6FC) */ +#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ +/* SPM_DVFS_CON (0x10006000+0x700) */ +#define SPM_DVFS_CON_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CON_STA (0x10006000+0x704) */ +#define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */ +/* SPM_PMIC_SPMI_CON (0x10006000+0x708) */ +#define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */ +#define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */ +#define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */ +#define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */ +/* SPM_DVFS_CMD0 (0x10006000+0x710) */ +#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD1 (0x10006000+0x714) */ +#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD2 (0x10006000+0x718) */ +#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD3 (0x10006000+0x71C) */ +#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD4 (0x10006000+0x720) */ +#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD5 (0x10006000+0x724) */ +#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD6 (0x10006000+0x728) */ +#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD7 (0x10006000+0x72C) */ +#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD8 (0x10006000+0x730) */ +#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD9 (0x10006000+0x734) */ +#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD10 (0x10006000+0x738) */ +#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD11 (0x10006000+0x73C) */ +#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD12 (0x10006000+0x740) */ +#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD13 (0x10006000+0x744) */ +#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD14 (0x10006000+0x748) */ +#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD15 (0x10006000+0x74C) */ +#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD16 (0x10006000+0x750) */ +#define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD17 (0x10006000+0x754) */ +#define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD18 (0x10006000+0x758) */ +#define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD19 (0x10006000+0x75C) */ +#define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD20 (0x10006000+0x760) */ +#define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD21 (0x10006000+0x764) */ +#define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD22 (0x10006000+0x768) */ +#define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */ +/* SPM_DVFS_CMD23 (0x10006000+0x76C) */ +#define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_VALUE_L (0x10006000+0x770) */ +#define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_VALUE_H (0x10006000+0x774) */ +#define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_START_L (0x10006000+0x778) */ +#define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_START_H (0x10006000+0x77C) */ +#define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */ +#define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */ +#define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */ +#define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */ +#define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */ +#define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */ +#define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */ +#define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */ +#define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */ +#define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */ +#define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */ +#define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */ +#define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */ +#define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */ +#define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */ +#define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */ +#define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */ +#define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */ +#define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */ +#define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */ +#define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */ +#define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */ +#define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */ +#define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */ +#define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */ +#define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */ +#define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */ +#define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */ +#define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */ +#define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */ +#define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */ +#define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */ +/* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */ +#define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_0 (0x10006000+0x800) */ +#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_1 (0x10006000+0x804) */ +#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_2 (0x10006000+0x808) */ +#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ +#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_4 (0x10006000+0x810) */ +#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_5 (0x10006000+0x814) */ +#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_6 (0x10006000+0x818) */ +#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ +#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_8 (0x10006000+0x820) */ +#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_9 (0x10006000+0x824) */ +#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_10 (0x10006000+0x828) */ +#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */ +#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_12 (0x10006000+0x830) */ +#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_13 (0x10006000+0x834) */ +#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_14 (0x10006000+0x838) */ +#define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */ +#define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_16 (0x10006000+0x840) */ +#define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_17 (0x10006000+0x844) */ +#define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_18 (0x10006000+0x848) */ +#define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */ +#define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */ +#define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */ +#define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */ +#define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */ +#define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */ +#define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */ +#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */ +#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */ +#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */ +#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */ +#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */ +#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */ +#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */ +/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */ +#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */ +#define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */ +/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */ +#define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */ +#define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */ +#define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */ +#define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */ +/* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */ +#define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */ +#define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */ +#define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */ +#define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */ +/* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */ +#define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */ +#define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */ +#define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */ +#define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */ +#define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */ +#define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */ +#define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */ +#define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */ +#define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */ +#define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */ +#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */ +#define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */ +#define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */ +#define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */ +/* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */ +#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */ +#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */ +#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */ +#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */ +#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */ +/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */ +#define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */ +#define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */ +/* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */ +#define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */ +/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */ +#define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */ +/* SPM_COUNTER_0 (0x10006000+0x978) */ +#define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */ +#define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */ +#define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */ +#define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */ +#define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */ +#define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */ +/* SPM_COUNTER_1 (0x10006000+0x97C) */ +#define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */ +#define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */ +#define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */ +#define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */ +#define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */ +#define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */ +/* SPM_COUNTER_2 (0x10006000+0x980) */ +#define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */ +#define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */ +#define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */ +#define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */ +#define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */ +#define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */ +/* SYS_TIMER_CON (0x10006000+0x98C) */ +#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ +#define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */ +#define SYS_TIMER_ID_LSB (1U << 8) /* 8b */ +#define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */ +/* RC_FSM_STA_0 (0x10006000+0xE00) */ +#define RC_FSM_STA_0_LSB (1U << 0) /* 32b */ +/* RC_CMD_STA_0 (0x10006000+0xE04) */ +#define RC_CMD_STA_0_LSB (1U << 0) /* 32b */ +/* RC_CMD_STA_1 (0x10006000+0xE08) */ +#define RC_CMD_STA_1_LSB (1U << 0) /* 32b */ +/* RC_SPI_STA_0 (0x10006000+0xE0C) */ +#define RC_SPI_STA_0_LSB (1U << 0) /* 32b */ +/* RC_PI_PO_STA_0 (0x10006000+0xE10) */ +#define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M00_REQ_STA_0 (0x10006000+0xE14) */ +#define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */ +#define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M02_REQ_STA_0 (0x10006000+0xE20) */ +#define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M03_REQ_STA_0 (0x10006000+0xE24) */ +#define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M04_REQ_STA_0 (0x10006000+0xE28) */ +#define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */ +#define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M06_REQ_STA_0 (0x10006000+0xE30) */ +#define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M07_REQ_STA_0 (0x10006000+0xE34) */ +#define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M08_REQ_STA_0 (0x10006000+0xE38) */ +#define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */ +#define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M10_REQ_STA_0 (0x10006000+0xE40) */ +#define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M11_REQ_STA_0 (0x10006000+0xE44) */ +#define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_M12_REQ_STA_0 (0x10006000+0xE48) */ +#define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_STA_0 (0x10006000+0xE4C) */ +#define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */ +#define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */ +#define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */ +#define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */ +#define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */ +#define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */ +#define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */ +#define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */ +#define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */ +#define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */ +#define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */ +#define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */ +#define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */ +#define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */ +#define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */ +#define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */ +/* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */ +#define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */ +#define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */ +#define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */ +#define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */ +#define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */ +#define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */ +#define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */ +#define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */ +#define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */ +#define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */ +#define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */ +#define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */ +#define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */ +#define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */ +#define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */ +#define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ +/* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */ +#define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_19 (0x10006000+0xED8) */ +#define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */ +#define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */ +#define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */ +#define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */ +#define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */ +/* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */ +#define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */ +/* PMSR_LAST_DAT (0x10006000+0xF00) */ +#define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */ +/* PMSR_LAST_CNT (0x10006000+0xF04) */ +#define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */ +#define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */ +/* PMSR_LAST_ACK (0x10006000+0xF08) */ +#define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */ +/* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */ +#define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */ +#define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */ +#define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */ +#define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */ +#define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */ +#define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */ +#define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */ +#define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */ +#define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */ +#define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */ +#define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */ +#define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */ +#define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */ +#define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */ +#define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */ +/* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */ +#define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */ +#define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */ +#define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */ +#define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */ +#define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */ +#define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */ +#define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */ +#define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */ +#define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */ +#define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */ +#define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */ +#define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */ +#define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */ +#define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */ +#define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */ +#define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */ +#define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */ +#define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */ +#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */ +#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */ +#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */ +#define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */ +#define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */ +#define PMSR_MODE_LSB (1U << 20) /* 2b */ +#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */ +#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */ +#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */ +/* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */ +#define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */ +#define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */ +#define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */ +#define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */ +#define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */ +#define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */ +#define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */ +#define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */ +/* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */ +#define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */ +#define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */ +#define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */ +#define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */ +#define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */ +#define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */ +#define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */ +#define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */ +#define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */ +#define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */ +#define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */ +#define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */ +#define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */ +#define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */ +#define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */ +#define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */ +/* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */ +#define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */ +#define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */ +#define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */ +#define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */ +#define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */ +#define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */ +#define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */ +#define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */ +#define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */ +#define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */ +#define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */ +#define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */ +#define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */ +#define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */ +#define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */ +#define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */ +/* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */ +#define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */ +#define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */ +#define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */ +#define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */ +#define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */ +#define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */ +#define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */ +#define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */ +#define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */ +#define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */ +#define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */ +#define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */ +#define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */ +#define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */ +#define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */ +#define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */ +/* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */ +#define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */ +#define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */ +/* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */ +#define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */ + +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) +#endif /* MT_SPM_REG */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h new file mode 100644 index 0000000..30194eb --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_RESOURCE_REQ_H +#define MT_SPM_RESOURCE_REQ_H + +/* SPM resource request internal bit */ +#define MT_SPM_BIT_XO_FPM 0 +#define MT_SPM_BIT_26M 1 +#define MT_SPM_BIT_INFRA 2 +#define MT_SPM_BIT_SYSPLL 3 +#define MT_SPM_BIT_DRAM_S0 4 +#define MT_SPM_BIT_DRAM_S1 5 + +/* SPM resource request internal bit_mask */ +#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM) +#define MT_SPM_26M BIT(MT_SPM_BIT_26M) +#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA) +#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL) +#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0) +#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1) +#endif /* MT_SPM_RESOURCE_REQ_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c new file mode 100644 index 0000000..3eb73d4 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/mmio.h> +#include <mt_spm.h> +#include <mt_spm_conservation.h> +#include <mt_spm_internal.h> +#include <mt_spm_rc_internal.h> +#include <mt_spm_reg.h> +#include <mt_spm_resource_req.h> +#include <mt_spm_suspend.h> +#include <plat_pm.h> +#include <uart.h> + +#define SPM_SUSPEND_SLEEP_PCM_FLAG \ + (SPM_FLAG_DISABLE_INFRA_PDN | \ + SPM_FLAG_DISABLE_VCORE_DVS | \ + SPM_FLAG_DISABLE_VCORE_DFS | \ + SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \ + SPM_FLAG_USE_SRCCLKENO2 | \ + SPM_FLAG_ENABLE_MD_MUMTAS | \ + SPM_FLAG_SRAM_SLEEP_CTRL) + +#define SPM_SUSPEND_SLEEP_PCM_FLAG1 \ + (SPM_FLAG1_DISABLE_MD26M_CK_OFF) + +#define SPM_SUSPEND_PCM_FLAG \ + (SPM_FLAG_DISABLE_VCORE_DVS | \ + SPM_FLAG_DISABLE_VCORE_DFS | \ + SPM_FLAG_ENABLE_TIA_WORKAROUND | \ + SPM_FLAG_ENABLE_MD_MUMTAS | \ + SPM_FLAG_SRAM_SLEEP_CTRL) + +#define SPM_SUSPEND_PCM_FLAG1 \ + (SPM_FLAG1_DISABLE_MD26M_CK_OFF) + +#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \ + (R12_PCM_TIMER | \ + R12_KP_IRQ_B | \ + R12_APWDT_EVENT_B | \ + R12_APXGPT1_EVENT_B | \ + R12_CONN2AP_SPM_WAKEUP_B | \ + R12_EINT_EVENT_B | \ + R12_CONN_WDT_IRQ_B | \ + R12_CCIF0_EVENT_B | \ + R12_SSPM2SPM_WAKEUP_B | \ + R12_SCP2SPM_WAKEUP_B | \ + R12_ADSP2SPM_WAKEUP_B | \ + R12_USBX_CDSC_B | \ + R12_USBX_POWERDWN_B | \ + R12_SYS_TIMER_EVENT_B | \ + R12_EINT_EVENT_SECURE_B | \ + R12_CCIF1_EVENT_B | \ + R12_SYS_CIRQ_IRQ_B | \ + R12_MD2AP_PEER_EVENT_B | \ + R12_MD1_WDT_B | \ + R12_CLDMA_EVENT_B | \ + R12_REG_CPU_WAKEUP | \ + R12_APUSYS_WAKE_HOST_B | \ + R12_PCIE_BRIDGE_IRQ | \ + R12_PCIE_IRQ) + +#if defined(CFG_MICROTRUST_TEE_SUPPORT) +#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__) +#else +#define WAKE_SRC_FOR_SUSPEND \ + (__WAKE_SRC_FOR_SUSPEND_COMMON__ | \ + R12_SEJ_EVENT_B) +#endif + +static struct pwr_ctrl suspend_ctrl = { + .wake_src = WAKE_SRC_FOR_SUSPEND, + .pcm_flags = SPM_SUSPEND_PCM_FLAG | SPM_FLAG_DISABLE_INFRA_PDN, + .pcm_flags1 = SPM_SUSPEND_PCM_FLAG1, + + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC6_MASK */ + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddr_en_mask_b = 1, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_vrf18_req = 0, + .reg_spm_ddr_en_req = 0, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC_MASK */ + .reg_md_srcclkena_0_mask_b = 1, + .reg_md_srcclkena2infra_req_0_mask_b = 0, + .reg_md_apsrc2infra_req_0_mask_b = 1, + .reg_md_apsrc_req_0_mask_b = 1, + .reg_md_vrf18_req_0_mask_b = 1, + .reg_md_ddr_en_0_mask_b = 1, + .reg_md_srcclkena_1_mask_b = 0, + .reg_md_srcclkena2infra_req_1_mask_b = 0, + .reg_md_apsrc2infra_req_1_mask_b = 0, + .reg_md_apsrc_req_1_mask_b = 0, + .reg_md_vrf18_req_1_mask_b = 0, + .reg_md_ddr_en_1_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddr_en_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni0_srcclkena_mask_b = 1, + .reg_srcclkeni0_infra_req_mask_b = 1, + .reg_srcclkeni1_srcclkena_mask_b = 0, + .reg_srcclkeni1_infra_req_mask_b = 0, + .reg_srcclkeni2_srcclkena_mask_b = 0, + .reg_srcclkeni2_infra_req_mask_b = 0, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddr_en_mask_b = 1, + .reg_md32_srcclkena_mask_b = 1, + .reg_md32_infra_req_mask_b = 1, + .reg_md32_apsrc_req_mask_b = 1, + .reg_md32_vrf18_req_mask_b = 1, + .reg_md32_ddr_en_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddr_en_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddr_en_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddr_en_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddr_en_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddr_en_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddr_en_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_apu_ddr_en_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddr_en_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_int0_mask_b = 0, + .reg_sw2spm_int1_mask_b = 0, + .reg_sw2spm_int2_mask_b = 0, + .reg_sw2spm_int3_mask_b = 0, + .reg_sc_adsp2spm_wakeup_mask_b = 0, + .reg_sc_sspm2spm_wakeup_mask_b = 0, + .reg_sc_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrreq_mask = 1, + .reg_spm_srcclkena_reserved_mask_b = 0, + .reg_spm_infra_req_reserved_mask_b = 0, + .reg_spm_apsrc_req_reserved_mask_b = 0, + .reg_spm_vrf18_req_reserved_mask_b = 0, + .reg_spm_ddr_en_reserved_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddr_en_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddr_en_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddr_en_mask_b = 1, + + /* SPM_SRC4_MASK */ + .ccif_event_mask_b = 0xFFF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddr_en_mask_b = 0, + .reg_dramc0_md32_infra_req_mask_b = 1, + .reg_dramc0_md32_vrf18_req_mask_b = 0, + .reg_dramc1_md32_infra_req_mask_b = 1, + .reg_dramc1_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc0_md32_wakeup_mask = 1, + .reg_dramc1_md32_wakeup_mask = 1, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x11, + .reg_mcusys_merge_ddr_en_mask_b = 0x11, + .reg_msdc2_srcclkena_mask_b = 1, + .reg_msdc2_infra_req_mask_b = 1, + .reg_msdc2_apsrc_req_mask_b = 1, + .reg_msdc2_vrf18_req_mask_b = 1, + .reg_msdc2_ddr_en_mask_b = 1, + .reg_pcie_srcclkena_mask_b = 1, + .reg_pcie_infra_req_mask_b = 1, + .reg_pcie_apsrc_req_mask_b = 1, + .reg_pcie_vrf18_req_mask_b = 1, + .reg_pcie_ddr_en_mask_b = 1, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0x01382202, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* Auto-gen End */ +}; + +struct spm_lp_scen __spm_suspend = { + .pwrctrl = &suspend_ctrl, +}; + +int mt_spm_suspend_mode_set(int mode) +{ + if (mode == MT_SPM_SUSPEND_SLEEP) { + suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG; + suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1; + } else { + suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG; + suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1; + } + + return 0; +} + +int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, + unsigned int resource_req) +{ + /* If FMAudio / ADSP is active, change to sleep suspend mode */ + if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) { + mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP); + } + + /* Notify MCUPM that device is going suspend flow */ + mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN); + + /* Notify UART to sleep */ + mt_uart_save(); + + return spm_conservation(state_id, ext_opand, + &__spm_suspend, resource_req); +} + +void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, + struct wake_status **status) +{ + spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status); + + /* Notify UART to wakeup */ + mt_uart_restore(); + + /* Notify MCUPM that device leave suspend */ + mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0); + + /* If FMAudio / ADSP is active, change back to suspend mode */ + if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) { + mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN); + } +} + +void mt_spm_suspend_init(void) +{ + spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl); +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h new file mode 100644 index 0000000..08bbad2 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_SUSPEND_H +#define MT_SPM_SUSPEND_H + +#include <mt_spm_internal.h> + +#define MCUPM_MBOX_OFFSET_PDN 0x0C55FDA8 +#define MCUPM_POWER_DOWN 0x4D50444E + +enum MT_SPM_SUSPEND_MODE { + MT_SPM_SUSPEND_SYSTEM_PDN, + MT_SPM_SUSPEND_SLEEP, +}; + +extern int mt_spm_suspend_mode_set(int mode); +extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand, + unsigned int reosuce_req); +extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand, + struct wake_status **status); +extern void mt_spm_suspend_init(void); +#endif /* MT_SPM_SUSPEND_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c new file mode 100644 index 0000000..f74ea80 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c @@ -0,0 +1,405 @@ +/* + * Copyright(C)2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stddef.h> +#include <stdio.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <plat/common/platform.h> +#include <lib/utils_def.h> + +#include <mtk_sip_svc.h> +#include <plat_pm.h> +#include <platform_def.h> + +#include "mt_spm.h" +#include "mt_spm_internal.h" +#include "mt_spm_reg.h" +#include "mt_spm_vcorefs.h" +#include "mt_spm_pmic_wrap.h" + +#define VCORE_CT_ENABLE (1U << 5) +#define SW_REQ5_INIT_VAL (6U << 12) +#define V_VMODE_SHIFT 0 +#define VCORE_HV 105 +#define VCORE_LV 95 +#define PMIC_STEP_UV 6250 + +static const struct reg_config dvfsrc_init_configs[] = { + /* Setup opp table */ + { DVFSRC_LEVEL_LABEL_0_1, 0x50436053 }, + { DVFSRC_LEVEL_LABEL_2_3, 0x40335042 }, + { DVFSRC_LEVEL_LABEL_4_5, 0x40314032 }, + { DVFSRC_LEVEL_LABEL_6_7, 0x30223023 }, + { DVFSRC_LEVEL_LABEL_8_9, 0x20133021 }, + { DVFSRC_LEVEL_LABEL_10_11, 0x20112012 }, + { DVFSRC_LEVEL_LABEL_12_13, 0x10032010 }, + { DVFSRC_LEVEL_LABEL_14_15, 0x10011002 }, + { DVFSRC_LEVEL_LABEL_16_17, 0x00131000 }, + { DVFSRC_LEVEL_LABEL_18_19, 0x00110012 }, + { DVFSRC_LEVEL_LABEL_20_21, 0x00000010 }, + + /* Setup hw emi qos policy */ + { DVFSRC_DDR_REQUEST, 0x00004321 }, + { DVFSRC_DDR_REQUEST3, 0x00000065 }, + + /* Setup up for PCIe */ + { DVFSRC_PCIE_VCORE_REQ, 0x0A298001 }, + + /* Setup up HRT QOS policy */ + { DVFSRC_HRT_BW_BASE, 0x00000004 }, + { DVFSRC_HRT_REQ_UNIT, 0x0000001E }, + { DVFSRC_HRT_HIGH_3, 0x18A618A6 }, + { DVFSRC_HRT_HIGH_2, 0x18A61183 }, + { DVFSRC_HRT_HIGH_1, 0x0D690B80 }, + { DVFSRC_HRT_HIGH, 0x070804B0 }, + { DVFSRC_HRT_LOW_3, 0x18A518A5 }, + { DVFSRC_HRT_LOW_2, 0x18A51182 }, + { DVFSRC_HRT_LOW_1, 0x0D680B7F }, + { DVFSRC_HRT_LOW, 0x070704AF }, + { DVFSRC_HRT_REQUEST, 0x66654321 }, + /* Setup up SRT QOS policy */ + { DVFSRC_QOS_EN, 0x0011007C }, + { DVFSRC_DDR_QOS0, 0x00000019 }, + { DVFSRC_DDR_QOS1, 0x00000026 }, + { DVFSRC_DDR_QOS2, 0x00000033 }, + { DVFSRC_DDR_QOS3, 0x0000003B }, + { DVFSRC_DDR_QOS4, 0x0000004C }, + { DVFSRC_DDR_QOS5, 0x00000066 }, + { DVFSRC_DDR_QOS6, 0x00000066 }, + { DVFSRC_DDR_REQUEST5, 0x54321000 }, + { DVFSRC_DDR_REQUEST7, 0x66000000 }, + /* Setup up hifi request policy */ + { DVFSRC_DDR_REQUEST6, 0x66543210 }, + /* Setup up hw request vcore policy */ + { DVFSRC_VCORE_USER_REQ, 0x00010A29 }, + + /* Setup misc*/ + { DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 }, + { DVFSRC_RSRV_5, 0x00000001 }, + { DVFSRC_INT_EN, 0x00000002 }, + /* Init opp and enable dvfsrc*/ + { DVFSRC_CURRENT_FORCE, 0x00000001 }, + { DVFSRC_BASIC_CONTROL, 0x0298444B }, + { DVFSRC_BASIC_CONTROL, 0x0298054B }, + { DVFSRC_CURRENT_FORCE, 0x00000000 }, +}; + +static struct pwr_ctrl vcorefs_ctrl = { + .wake_src = R12_REG_CPU_WAKEUP, + + /* default VCORE DVFS is disabled */ + .pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO | + SPM_FLAG_DISABLE_VCORE_DVS | + SPM_FLAG_DISABLE_VCORE_DFS), + + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_vrf18_req = 0, + .reg_spm_ddr_en_req = 1, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC6_MASK */ + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddr_en_mask_b = 1, + + /* SPM_SRC_MASK */ + .reg_md_srcclkena_0_mask_b = 1, + .reg_md_srcclkena2infra_req_0_mask_b = 0, + .reg_md_apsrc2infra_req_0_mask_b = 1, + .reg_md_apsrc_req_0_mask_b = 1, + .reg_md_vrf18_req_0_mask_b = 1, + .reg_md_ddr_en_0_mask_b = 1, + .reg_md_srcclkena_1_mask_b = 0, + .reg_md_srcclkena2infra_req_1_mask_b = 0, + .reg_md_apsrc2infra_req_1_mask_b = 0, + .reg_md_apsrc_req_1_mask_b = 0, + .reg_md_vrf18_req_1_mask_b = 0, + .reg_md_ddr_en_1_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddr_en_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni0_srcclkena_mask_b = 1, + .reg_srcclkeni0_infra_req_mask_b = 1, + .reg_srcclkeni1_srcclkena_mask_b = 0, + .reg_srcclkeni1_infra_req_mask_b = 0, + .reg_srcclkeni2_srcclkena_mask_b = 0, + .reg_srcclkeni2_infra_req_mask_b = 0, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddr_en_mask_b = 1, + .reg_md32_srcclkena_mask_b = 1, + .reg_md32_infra_req_mask_b = 1, + .reg_md32_apsrc_req_mask_b = 1, + .reg_md32_vrf18_req_mask_b = 1, + .reg_md32_ddr_en_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddr_en_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddr_en_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddr_en_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddr_en_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddr_en_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddr_en_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_apu_ddr_en_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddr_en_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_int0_mask_b = 0, + .reg_sw2spm_int1_mask_b = 0, + .reg_sw2spm_int2_mask_b = 0, + .reg_sw2spm_int3_mask_b = 0, + .reg_sc_adsp2spm_wakeup_mask_b = 0, + .reg_sc_sspm2spm_wakeup_mask_b = 0, + .reg_sc_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrreq_mask = 1, + .reg_spm_srcclkena_reserved_mask_b = 0, + .reg_spm_infra_req_reserved_mask_b = 0, + .reg_spm_apsrc_req_reserved_mask_b = 0, + .reg_spm_vrf18_req_reserved_mask_b = 0, + .reg_spm_ddr_en_reserved_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddr_en_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddr_en_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddr_en_mask_b = 1, + + /* SPM_SRC4_MASK */ + .ccif_event_mask_b = 0xFFF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddr_en_mask_b = 0, + .reg_dramc0_md32_infra_req_mask_b = 1, + .reg_dramc0_md32_vrf18_req_mask_b = 0, + .reg_dramc1_md32_infra_req_mask_b = 1, + .reg_dramc1_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc0_md32_wakeup_mask = 1, + .reg_dramc1_md32_wakeup_mask = 1, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x11, + .reg_mcusys_merge_ddr_en_mask_b = 0x11, + .reg_msdc2_srcclkena_mask_b = 1, + .reg_msdc2_infra_req_mask_b = 1, + .reg_msdc2_apsrc_req_mask_b = 1, + .reg_msdc2_vrf18_req_mask_b = 1, + .reg_msdc2_ddr_en_mask_b = 1, + .reg_pcie_srcclkena_mask_b = 1, + .reg_pcie_infra_req_mask_b = 1, + .reg_pcie_apsrc_req_mask_b = 1, + .reg_pcie_vrf18_req_mask_b = 1, + .reg_pcie_ddr_en_mask_b = 1, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFFF, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* Auto-gen End */ +}; + +struct spm_lp_scen __spm_vcorefs = { + .pwrctrl = &vcorefs_ctrl, +}; + +static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val) +{ + if (cmd < NR_IDX_ALL) { + mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val); + } else { + INFO("cmd out of range!\n"); + } +} + +void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue) +{ + mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB, + SPM_DVFSRC_ENABLE_LSB); + + mmio_write_32(SPM_DVFS_LEVEL, 0x00000001); + mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001); +} + +void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl, + const struct pwr_ctrl *src_pwr_ctrl) +{ + uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS | + SPM_FLAG_DISABLE_VCORE_DFS | + SPM_FLAG_ENABLE_VOLTAGE_BIN; + + dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) | + (src_pwr_ctrl->pcm_flags & dvfs_mask); + + if (dest_pwr_ctrl->pcm_flags_cust > 0U) { + dest_pwr_ctrl->pcm_flags_cust = + (dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) | + (src_pwr_ctrl->pcm_flags & dvfs_mask); + } +} + +static void spm_go_to_vcorefs(void) +{ + __spm_set_power_control(__spm_vcorefs.pwrctrl); + __spm_set_wakeup_event(__spm_vcorefs.pwrctrl); + __spm_set_pcm_flags(__spm_vcorefs.pwrctrl); + __spm_send_cpu_wakeup_event(); +} + +static void dvfsrc_init(void) +{ + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) { + mmio_write_32(dvfsrc_init_configs[i].offset, + dvfsrc_init_configs[i].val); + } +} + +static uint32_t spm_vcorefs_get_efuse_data(void) +{ + return mmio_read_32(VCORE_VB_EFUSE); +} + +static uint32_t is_rising_need(void) +{ + return ((spm_vcorefs_get_efuse_data() & 0xF) == 11U) ? 1U : 0U; +} + +static void spm_vcorefs_vcore_setting(uint64_t flag) +{ + uint32_t dvfs_v_mode, dvfsrc_rsrv, i; + uint32_t opp_uv[] = {725000U, 650000U, 600000U, 575000U}; + + dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4); + + dvfs_v_mode = (dvfsrc_rsrv >> V_VMODE_SHIFT) & 0x3; + + if (is_rising_need() != 0U) { + opp_uv[2] = 625000U; + opp_uv[3] = 600000U; + } + + for (i = 0; i < ARRAY_SIZE(opp_uv); i++) { + if (dvfs_v_mode == 3U) { + /* LV */ + opp_uv[i] = round_down((opp_uv[i] * VCORE_LV) / 100U, + PMIC_STEP_UV); + } else if (dvfs_v_mode == 1U) { + /* HV */ + opp_uv[i] = round_up((opp_uv[i] * VCORE_HV) / 100U, + PMIC_STEP_UV); + } + spm_vcorefs_pwarp_cmd(i, __vcore_uv_to_pmic(opp_uv[i])); + } +} + +uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4) +{ + uint64_t cmd = x1; + uint64_t spm_flags; + + switch (cmd) { + case VCOREFS_SMC_CMD_INIT: + /* vcore_dvfs init + kick */ + mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL); + spm_dvfsfw_init(0ULL, 0ULL); + spm_vcorefs_vcore_setting(x3 & 0xF); + spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO; + if ((x2 & 0x1) > 0U) { + spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS; + } + + if ((x2 & 0x2) > 0U) { + spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS; + } + + if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) { + spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN; + } + + set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags); + spm_go_to_vcorefs(); + dvfsrc_init(); + + *x4 = 0U; + mmio_write_32(DVFSRC_SW_REQ5, 0U); + break; + case VCOREFS_SMC_CMD_KICK: + mmio_write_32(DVFSRC_SW_REQ5, 0U); + break; + default: + break; + } + + return 0ULL; +} diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h new file mode 100644 index 0000000..f4e0c48 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h @@ -0,0 +1,135 @@ +/* + * Copyright(C)2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_VCOREFS_H +#define MT_SPM_VCOREFS_H + +uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4); + +enum vcorefs_smc_cmd { + VCOREFS_SMC_CMD_0, + VCOREFS_SMC_CMD_1, + VCOREFS_SMC_CMD_2, + VCOREFS_SMC_CMD_3, + VCOREFS_SMC_CMD_4, + /* check spmfw status */ + VCOREFS_SMC_CMD_5, + + /* get spmfw type */ + VCOREFS_SMC_CMD_6, + + /* get spm reg status */ + VCOREFS_SMC_CMD_7, + + NUM_VCOREFS_SMC_CMD, +}; + +enum vcorefs_smc_cmd_new { + VCOREFS_SMC_CMD_INIT = 0, + VCOREFS_SMC_CMD_KICK = 1, +}; + +#define _VCORE_BASE_UV 400000 +#define _VCORE_STEP_UV 6250 + +/* PMIC */ +#define __vcore_pmic_to_uv(pmic) \ + (((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV) + +#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \ + ((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV) + +struct reg_config { + uint32_t offset; + uint32_t val; +}; + +#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0) +#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) +#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8) +#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC) +#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0) +#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4) +#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8) +#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100) +#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104) +#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108) +#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C) +#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110) +#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114) +#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118) +#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C) +#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280) +#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294) +#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) +#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614) +#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00) +#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04) +#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08) +#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C) +#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10) +#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14) +#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18) +#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34) +#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) +#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C) +#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40) +#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44) +#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60) +#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4) +#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8) +#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC) +#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0) +#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4) +#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8) +#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC) +#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0) +#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4) +#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8) +#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC) +#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0) +#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4) +#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) +#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC) +#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00) +#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) +#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08) +#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C) +#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0) +#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4) +#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8) +#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC) +#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00) +#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04) +#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08) +#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C) +#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0) +#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4) +#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8) +#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC) +#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00) +#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04) +#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08) +#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C) +#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10) +#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14) +#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) +#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C) +#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38) +#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C) +#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C) +#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50) +#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54) +#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58) +#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C) +#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60) +#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64) +#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68) +#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C) + +#define VCORE_VB_EFUSE (0x11C105E8) + +#endif /* MT_SPM_VCOREFS_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h new file mode 100644 index 0000000..66be7ee --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_SSPM_NOTIFIER_H +#define MT_SPM_SSPM_NOTIFIER_H + +enum MT_SPM_SSPM_NOTIFY_ID { + MT_SPM_NOTIFY_LP_ENTER, + MT_SPM_NOTIFY_LP_LEAVE, +}; + +int mt_spm_sspm_notify(int type, unsigned int lp_mode); + +static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode) +{ + return mt_spm_sspm_notify(type, lp_mode); +} +#endif /* MT_SPM_SSPM_NOTIFIER_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h new file mode 100644 index 0000000..452ae90 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SPM_SSPM_INTC_H +#define MT_SPM_SSPM_INTC_H + +#include <mt_spm_reg.h> + +#define MT_SPM_SSPM_INTC_SEL_0 0x10 +#define MT_SPM_SSPM_INTC_SEL_1 0x20 +#define MT_SPM_SSPM_INTC_SEL_2 0x40 +#define MT_SPM_SSPM_INTC_SEL_3 0x80 + +#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \ + (((0x10 << id) | (sg << id)) & 0xff) + +#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1) +#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0) +#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1) +#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0) +#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1) +#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0) +#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1) +#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0) + +#define DO_SPM_SSPM_LP_SUSPEND() \ + mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH) +#define DO_SPM_SSPM_LP_RESUME() \ + mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW) +#endif /* MT_SPM_SSPM_INTC_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c new file mode 100644 index 0000000..e0ba037 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stddef.h> + +#include <lib/mmio.h> + +#include <mt_spm_notifier.h> +#include <mt_spm_sspm_intc.h> + +#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x) +#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL)) + +#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0) +#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1) +#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2) +#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3) + +#define MCUPM_MBOX_OFFSET_LP 0x0C55FDA4 +#define MCUPM_MBOX_ENTER_LP 0x454e0000 +#define MCUPM_MBOX_LEAVE_LP 0x4c450000 +#define MCUPM_MBOX_SLEEP_MASK 0x0000FFFF + +int mt_spm_sspm_notify(int type, unsigned int lp_mode) +{ + switch (type) { + case MT_SPM_NOTIFY_LP_ENTER: + mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode); + mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_ENTER_LP | + (lp_mode & MCUPM_MBOX_SLEEP_MASK)); + DO_SPM_SSPM_LP_SUSPEND(); + break; + case MT_SPM_NOTIFY_LP_LEAVE: + mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode); + mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_LEAVE_LP | + (lp_mode & MCUPM_MBOX_SLEEP_MASK)); + DO_SPM_SSPM_LP_RESUME(); + break; + default: + break; + } + + return 0; +} diff --git a/plat/mediatek/mt8192/drivers/spm/pcm_def.h b/plat/mediatek/mt8192/drivers/spm/pcm_def.h new file mode 100644 index 0000000..ab46b86 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/pcm_def.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PCM_DEF_H +#define PCM_DEF_H + +/* + * Auto generated by DE, please DO NOT modify this file directly. + */ + +/* --- R0 Define --- */ +#define R0_SC_26M_CK_OFF (1U << 0) +#define R0_SC_TX_TRACK_RETRY_EN (1U << 1) +#define R0_SC_MEM_CK_OFF (1U << 2) +#define R0_SC_AXI_CK_OFF (1U << 3) +#define R0_SC_DR_SRAM_LOAD (1U << 4) +#define R0_SC_MD26M_CK_OFF (1U << 5) +#define R0_SC_DPY_MODE_SW (1U << 6) +#define R0_SC_DMSUS_OFF (1U << 7) +#define R0_SC_DPY_2ND_DLL_EN (1U << 8) +#define R0_SC_DR_SRAM_RESTORE (1U << 9) +#define R0_SC_MPLLOUT_OFF (1U << 10) +#define R0_SC_TX_TRACKING_DIS (1U << 11) +#define R0_SC_DPY_DLL_EN (1U << 12) +#define R0_SC_DPY_DLL_CK_EN (1U << 13) +#define R0_SC_DPY_VREF_EN (1U << 14) +#define R0_SC_PHYPLL_EN (1U << 15) +#define R0_SC_DDRPHY_FB_CK_EN (1U << 16) +#define R0_SC_DPY_BCLK_ENABLE (1U << 17) +#define R0_SC_MPLL_OFF (1U << 18) +#define R0_SC_SHU_RESTORE (1U << 19) +#define R0_SC_CKSQ0_OFF (1U << 20) +#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21) +#define R0_SC_DR_SHU_EN (1U << 22) +#define R0_SC_DPHY_PRECAL_UP (1U << 23) +#define R0_SC_MPLL_S_OFF (1U << 24) +#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25) +#define R0_SC_PHYPLL_SHU_EN (1U << 26) +#define R0_SC_PHYPLL2_SHU_EN (1U << 27) +#define R0_SC_PHYPLL_MODE_SW (1U << 28) +#define R0_SC_PHYPLL2_MODE_SW (1U << 29) +#define R0_SC_DR_SHU_LEVEL0 (1U << 30) +#define R0_SC_DR_SHU_LEVEL1 (1U << 31) +/* --- R7 Define --- */ +#define R7_PWRAP_SLEEP_REQ (1U << 0) +#define R7_EMI_CLK_OFF_REQ (1U << 1) +#define R7_PCM_BUS_PROTECT_REQ (1U << 2) +#define R7_SPM_CK_UPDATE (1U << 3) +#define R7_SPM_CK_SEL0 (1U << 4) +#define R7_SPM_CK_SEL1 (1U << 5) +#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6) +#define R7_SC_FHC_PAUSE_MPLL (1U << 7) +#define R7_SC_26M_CK_SEL (1U << 8) +#define R7_PCM_TIMER_SET (1U << 9) +#define R7_PCM_TIMER_CLR (1U << 10) +#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11) +#define R7_CSYSPWRUPACK (1U << 12) +#define R7_PCM_IM_SLP_EN (1U << 13) +#define R7_SRCCLKENO0 (1U << 14) +#define R7_FORCE_DDR_EN_WAKE (1U << 15) +#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16) +#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17) +#define R7_SC_AXI_DCM_DIS (1U << 18) +#define R7_SC_FHC_PAUSE_MEM (1U << 19) +#define R7_SC_FHC_PAUSE_MAIN (1U << 20) +#define R7_SRCCLKENO1 (1U << 21) +#define R7_PCM_WDT_KICK_P (1U << 22) +#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23) +#define R7_SC_DDR_PST_REQ_PCM (1U << 24) +#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25) +#define R7_PMIC_IRQ_REQ_EN (1U << 26) +#define R7_FORCE_F26M_WAKE (1U << 27) +#define R7_FORCE_APSRC_WAKE (1U << 28) +#define R7_FORCE_INFRA_WAKE (1U << 29) +#define R7_FORCE_VRF18_WAKE (1U << 30) +#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31) +/* --- R12 Define --- */ +#define R12_PCM_TIMER (1U << 0) +#define R12_TWAM_IRQ_B (1U << 1) +#define R12_KP_IRQ_B (1U << 2) +#define R12_APWDT_EVENT_B (1U << 3) +#define R12_APXGPT1_EVENT_B (1U << 4) +#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5) +#define R12_EINT_EVENT_B (1U << 6) +#define R12_CONN_WDT_IRQ_B (1U << 7) +#define R12_CCIF0_EVENT_B (1U << 8) +#define R12_LOWBATTERY_IRQ_B (1U << 9) +#define R12_SSPM2SPM_WAKEUP_B (1U << 10) +#define R12_SCP2SPM_WAKEUP_B (1U << 11) +#define R12_ADSP2SPM_WAKEUP_B (1U << 12) +#define R12_PCM_WDT_WAKEUP_B (1U << 13) +#define R12_USBX_CDSC_B (1U << 14) +#define R12_USBX_POWERDWN_B (1U << 15) +#define R12_SYS_TIMER_EVENT_B (1U << 16) +#define R12_EINT_EVENT_SECURE_B (1U << 17) +#define R12_CCIF1_EVENT_B (1U << 18) +#define R12_UART0_IRQ_B (1U << 19) +#define R12_AFE_IRQ_MCU_B (1U << 20) +#define R12_THERM_CTRL_EVENT_B (1U << 21) +#define R12_SYS_CIRQ_IRQ_B (1U << 22) +#define R12_MD2AP_PEER_EVENT_B (1U << 23) +#define R12_CSYSPWREQ_B (1U << 24) +#define R12_MD1_WDT_B (1U << 25) +#define R12_CLDMA_EVENT_B (1U << 26) +#define R12_SEJ_EVENT_B (1U << 27) +#define R12_REG_CPU_WAKEUP (1U << 28) +#define R12_APUSYS_WAKE_HOST_B (1U << 29) +#define R12_PCIE_BRIDGE_IRQ (1U << 30) +#define R12_PCIE_IRQ (1U << 31) +/* --- R12ext Define --- */ +#define R12EXT_26M_WAKE (1U << 0) +#define R12EXT_26M_SLEEP (1U << 1) +#define R12EXT_INFRA_WAKE (1U << 2) +#define R12EXT_INFRA_SLEEP (1U << 3) +#define R12EXT_APSRC_WAKE (1U << 4) +#define R12EXT_APSRC_SLEEP (1U << 5) +#define R12EXT_VRF18_WAKE (1U << 6) +#define R12EXT_VRF18_SLEEP (1U << 7) +#define R12EXT_DVFS_WAKE (1U << 8) +#define R12EXT_DDREN_WAKE (1U << 9) +#define R12EXT_DDREN_SLEEP (1U << 10) +#define R12EXT_MCU_PM_WFI (1U << 11) +#define R12EXT_SSPM_IDLE (1U << 12) +#define R12EXT_CONN_SRCCLKENB (1U << 13) +#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14) +#define R12EXT_SW_MAILBOX_WAKE (1U << 15) +#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16) +#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17) +#define R12EXT_SCP_MAILBOX_WAKE (1U << 18) +#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19) +#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20) +#define R12EXT_VS1_TRIGGER (1U << 21) +#define R12EXT_VS2_TRIGGER (1U << 22) +#define R12EXT_COROSS_REQ_APU (1U << 23) +#define R12EXT_CROSS_REQ_L3 (1U << 24) +#define R12EXT_DDR_PST_ACK (1U << 25) +#define R12EXT_BIT26 (1U << 26) +#define R12EXT_BIT27 (1U << 27) +#define R12EXT_BIT28 (1U << 28) +#define R12EXT_BIT29 (1U << 29) +#define R12EXT_BIT30 (1U << 30) +#define R12EXT_BIT31 (1U << 31) +/* --- R13 Define --- */ +#define R13_SRCCLKENI0 (1U << 0) +#define R13_SRCCLKENI1 (1U << 1) +#define R13_MD_SRCCLKENA_0 (1U << 2) +#define R13_MD_APSRC_REQ_0 (1U << 3) +#define R13_CONN_DDR_EN (1U << 4) +#define R13_MD_SRCCLKENA_1 (1U << 5) +#define R13_SSPM_SRCCLKENA (1U << 6) +#define R13_SSPM_APSRC_REQ (1U << 7) +#define R13_MD1_STATE (1U << 8) +#define R13_BIT9 (1U << 9) +#define R13_MM_STATE (1U << 10) +#define R13_SSPM_STATE (1U << 11) +#define R13_MD_DDR_EN_0 (1U << 12) +#define R13_CONN_STATE (1U << 13) +#define R13_CONN_SRCCLKENA (1U << 14) +#define R13_CONN_APSRC_REQ (1U << 15) +#define R13_SC_DDR_PST_ACK_ALL (1U << 16) +#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17) +#define R13_SCP_STATE (1U << 18) +#define R13_CSYSPWRUPREQ (1U << 19) +#define R13_PWRAP_SLEEP_ACK (1U << 20) +#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21) +#define R13_AUDIO_DSP_STATE (1U << 22) +#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23) +#define R13_CONN_SRCCLKENB (1U << 24) +#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25) +#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26) +#define R13_DVFS_STATE (1U << 27) +#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28) +#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29) +#define R13_MD_VRF18_REQ_0 (1U << 30) +#define R13_DDR_EN_STATE (1U << 31) +#endif /* PCM_DEF_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/sleep_def.h b/plat/mediatek/mt8192/drivers/spm/sleep_def.h new file mode 100644 index 0000000..6c5cbed --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spm/sleep_def.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SLEEP_DEF_H +#define SLEEP_DEF_H + +/* + * Auto generated by DE, please DO NOT modify this file directly. + */ + +/* --- SPM Flag Define --- */ +#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0) +#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1) +#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2) +#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3) +#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4) +#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5) +#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6) +#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7) +#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8) +#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9) +#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) +#define SPM_FLAG_RESERVED_BIT11 (1U << 11) +#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12) +#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13) +#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14) +#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15) +#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16) +#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17) +#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18) +#define SPM_FLAG_ENABLE_MD_MUMTAS (1U << 19) +#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20) +#define SPM_FLAG_RESERVED_BIT21 (1U << 21) +#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22) +#define SPM_FLAG_DISABLE_SRAM_EVENT (1U << 23) +#define SPM_FLAG_RESERVED_BIT24 (1U << 24) +#define SPM_FLAG_RESERVED_BIT25 (1U << 25) +#define SPM_FLAG_RESERVED_BIT26 (1U << 26) +#define SPM_FLAG_VTCXO_STATE (1U << 27) +#define SPM_FLAG_INFRA_STATE (1U << 28) +#define SPM_FLAG_APSRC_STATE (1U << 29) +#define SPM_FLAG_VRF18_STATE (1U << 30) +#define SPM_FLAG_DDREN_STATE (1U << 31) +/* --- SPM Flag1 Define --- */ +#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0) +#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1) +#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2) +#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3) +#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4) +#define SPM_FLAG1_RESERVED_BIT5 (1U << 5) +#define SPM_FLAG1_ENABLE_REKICK (1U << 6) +#define SPM_FLAG1_DISABLE_MD26M_CK_OFF (1U << 7) +#define SPM_FLAG1_RESERVED_BIT8 (1U << 8) +#define SPM_FLAG1_RESERVED_BIT9 (1U << 9) +#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10) +#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11) +#define SPM_FLAG1_RESERVED_BIT12 (1U << 12) +#define SPM_FLAG1_RESERVED_BIT13 (1U << 13) +#define SPM_FLAG1_RESERVED_BIT14 (1U << 14) +#define SPM_FLAG1_RESERVED_BIT15 (1U << 15) +#define SPM_FLAG1_RESERVED_BIT16 (1U << 16) +#define SPM_FLAG1_RESERVED_BIT17 (1U << 17) +#define SPM_FLAG1_RESERVED_BIT18 (1U << 18) +#define SPM_FLAG1_RESERVED_BIT19 (1U << 19) +#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20) +#define SPM_FLAG1_RESERVED_BIT21 (1U << 21) +#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22) +#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23) +#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24) +#define SPM_FLAG1_RESERVED_BIT25 (1U << 25) +#define SPM_FLAG1_RESERVED_BIT26 (1U << 26) +#define SPM_FLAG1_RESERVED_BIT27 (1U << 27) +#define SPM_FLAG1_RESERVED_BIT28 (1U << 28) +#define SPM_FLAG1_RESERVED_BIT29 (1U << 29) +#define SPM_FLAG1_RESERVED_BIT30 (1U << 30) +#define SPM_FLAG1_DISABLE_CPUEB_OFF (1U << 31) +/* --- SPM DEBUG Define --- */ +#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) +#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) +#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) +#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) +#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) +#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) +#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) +#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) +#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) +#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) +#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10) +#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11) +#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12) +#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13) +#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14) +#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15) +#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16) +#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17) +#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18) +#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19) +#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20) +#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21) +#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22) +#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23) +#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24) +#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25) +#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26) +#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27) +#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28) +#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29) +#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30) +#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31) +/* --- SPM DEBUG1 Define --- */ +#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0) +#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1) +#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2) +#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3) +#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4) +#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5) +#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6) +#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7) +#define SPM_DBG1_RESERVED_BIT8 (1U << 8) +#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9) +#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10) +#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11) +#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12) +#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13) +#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14) +#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15) +#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16) +#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17) +#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18) +#define SPM_DBG1_RESERVED_BIT19 (1U << 19) +#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20) +#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21) +#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22) +#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23) +#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24) +#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25) +#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26) +#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27) +#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28) +#define SPM_DBG1_RESERVED_BIT29 (1U << 29) +#define SPM_DBG1_RESERVED_BIT30 (1U << 30) +#define SPM_DBG1_DEBUG_DISABLE_CPUEB_OFF (1U << 31) + + /* Macro and Inline */ +#define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U) +#define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U) +#define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U) +#endif /* SLEEP_DEF_H */ diff --git a/plat/mediatek/mt8192/drivers/spmc/mtspmc.c b/plat/mediatek/mt8192/drivers/spmc/mtspmc.c new file mode 100644 index 0000000..7ccebd6 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spmc/mtspmc.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> + +#include <mcucfg.h> +#include <mtspmc.h> +#include <mtspmc_private.h> + + +void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu) +{ + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); +} + +void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu) +{ + mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); +} + +void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr) +{ + assert(cluster == 0U); + + mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); +} + +uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu) +{ + assert(cluster == 0U); + + return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR)); +} + +void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64) +{ + uint32_t reg; + + assert(cluster == 0U); + + reg = per_cluster(cluster, MCUCFG_INITARCH); + + if (arm64) { + mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); + } else { + mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); + } +} + +/** + * Return subsystem's power state. + * + * @mask: mask to SPM_CPU_PWR_STATUS to query the power state + * of one subsystem. + * RETURNS: + * 0 (the subsys was powered off) + * 1 (the subsys was powered on) + */ +bool spm_get_powerstate(uint32_t mask) +{ + return (mmio_read_32(SPM_CPU_PWR_STATUS) & mask) != 0U; +} + +bool spm_get_cluster_powerstate(uint32_t cluster) +{ + assert(cluster == 0U); + + return spm_get_powerstate(MP0_CPUTOP); +} + +bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu) +{ + uint32_t mask = BIT(cpu); + + assert(cluster == 0U); + + return spm_get_powerstate(mask); +} + +int spmc_init(void) +{ + INFO("SPM: enable CPC mode\n"); + + mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN); + + mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); + mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); + mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); + mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); + mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); + mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); + mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); + + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(1)); + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(2)); + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(3)); + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(4)); + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(5)); + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(6)); + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(7)); + + mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); + mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); + mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); + + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); + + return 0; +} + +/** + * Power on a core with specified cluster and core index + * + * @cluster: the cluster ID of the CPU which to be powered on + * @cpu: the CPU ID of the CPU which to be powered on + */ +void spm_poweron_cpu(uint32_t cluster, uint32_t cpu) +{ + /* set to 0 after BIG VPROC bulk on & before B-core power on seq. */ + if (cpu >= 4U) { + mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U); + } + + mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN); + mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); + + while (!spm_get_cpu_powerstate(cluster, cpu)) { + } + + mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN); + + /* Enable Big CPU Last PC */ + if (cpu >= 4U) { + mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3)); + } +} + +/** + * Power off a core with specified cluster and core index + * + * @cluster: the cluster ID of the CPU which to be powered off + * @cpu: the CPU ID of the CPU which to be powered off + */ +void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu) +{ + /* Set mp0_spmc_pwr_on_cpuX = 0 */ + mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); +} + +/** + * Power off a cluster with specified index + * + * @cluster: the cluster index which to be powered off + */ +void spm_poweroff_cluster(uint32_t cluster) +{ + /* No need to power on/off cluster on single cluster platform */ + assert(false); +} + +/** + * Power on a cluster with specified index + * + * @cluster: the cluster index which to be powered on + */ +void spm_poweron_cluster(uint32_t cluster) +{ + /* No need to power on/off cluster on single cluster platform */ + assert(false); +} diff --git a/plat/mediatek/mt8192/drivers/spmc/mtspmc.h b/plat/mediatek/mt8192/drivers/spmc/mtspmc.h new file mode 100644 index 0000000..7ed2e62 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spmc/mtspmc.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTSPMC_H +#define MTSPMC_H + +#include <stdint.h> + +int spmc_init(void); + +void spm_poweron_cpu(uint32_t cluster, uint32_t cpu); +void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu); + +void spm_poweroff_cluster(uint32_t cluster); +void spm_poweron_cluster(uint32_t cluster); + +bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu); +bool spm_get_cluster_powerstate(uint32_t cluster); +bool spm_get_powerstate(uint32_t mask); + +void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64); +void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr); +uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu); + +void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu); +void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu); + +#endif /* MTSPMC_H */ diff --git a/plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h new file mode 100644 index 0000000..ad78295 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTSPMC_PRIVATE_H +#define MTSPMC_PRIVATE_H + +#include <lib/utils_def.h> +#include <platform_def.h> + +unsigned long read_cpuectlr(void); +void write_cpuectlr(unsigned long cpuectlr); + +unsigned long read_cpupwrctlr_el1(void); +void write_cpupwrctlr_el1(unsigned long cpuectlr); + +/* + * per_cpu/cluster helper + */ +struct per_cpu_reg { + unsigned int cluster_addr; + unsigned int cpu_stride; +}; + +#define per_cpu(cluster, cpu, reg) \ + (reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride)) + +#define per_cluster(cluster, reg) (reg[cluster].cluster_addr) + +#define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs)) +#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs)) +#define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs)) + +/* === SPMC related registers */ +#define SPM_POWERON_CONFIG_EN SPM_REG(0x000) +/* bit-fields of SPM_POWERON_CONFIG_EN */ +#define PROJECT_CODE (U(0xb16) << 16) +#define BCLK_CG_EN BIT(0) + +#define SPM_PWR_STATUS SPM_REG(0x16c) +#define SPM_PWR_STATUS_2ND SPM_REG(0x170) +#define SPM_CPU_PWR_STATUS SPM_REG(0x174) + +/* bit-fields of SPM_PWR_STATUS */ +#define MD BIT(0) +#define CONN BIT(1) +#define DDRPHY BIT(2) +#define DISP BIT(3) +#define MFG BIT(4) +#define ISP BIT(5) +#define INFRA BIT(6) +#define VDEC BIT(7) +#define MP0_CPUTOP BIT(8) +#define MP0_CPU0 BIT(9) +#define MP0_CPU1 BIT(10) +#define MP0_CPU2 BIT(11) +#define MP0_CPU3 BIT(12) +#define MCUSYS BIT(14) +#define MP0_CPU4 BIT(15) +#define MP0_CPU5 BIT(16) +#define MP0_CPU6 BIT(17) +#define MP0_CPU7 BIT(18) +#define VEN BIT(21) + +/* === SPMC related registers */ +#define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200) +#define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204) +#define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208) +#define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c) +#define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210) +#define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214) +#define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218) +#define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c) +#define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220) +#define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224) + +/* bit fields of SPM_*_PWR_CON */ +#define PWR_ON_ACK BIT(31) +#define VPROC_EXT_OFF BIT(7) +#define DORMANT_EN BIT(6) +#define RESETPWRON_CONFIG BIT(5) +#define PWR_CLK_DIS BIT(4) +#define PWR_ON BIT(2) +#define PWR_RST_B BIT(0) + +/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */ +static const struct per_cpu_reg SPM_CPU_PWR[] = { + { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U } +}; + +/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */ +static const struct per_cpu_reg SPM_CLUSTER_PWR[] = { + { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U } +}; + +/* === MCUCFG related registers */ +/* aa64naa32 */ +#define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4) +/* reset vectors */ +#define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900) +#define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908) +#define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910) +#define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918) +#define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920) +#define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928) +#define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930) +#define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938) + +/* MCUSYS DREQ BIG VPROC ISO control */ +#define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c) + +/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */ +static const struct per_cpu_reg MCUCFG_BOOTADDR[] = { + { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U } +}; + +/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */ +static const struct per_cpu_reg MCUCFG_INITARCH[] = { + { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U } +}; + +#define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu) +#define LAST_PC_REG(cpu) (MCUCFG_REG(0x308) + (cpu * 0x800)) + +/* === CPC control */ +#define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814) +#define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840) + +/* bit fields of CPC_FLOW_CTRL_CFG */ +#define CPC_CTRL_ENABLE BIT(16) +#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */ +#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu) + +/* bit fields of CPC_SPMC_PWR_STATUS */ +#define CORE_SPMC_PWR_ON_ACK GENMASK(15, 0) + +/* === APB Module infracfg_ao */ +#define INFRA_TOPAXI_PROTECTEN INFRACFG_AO_REG(0x0220) +#define INFRA_TOPAXI_PROTECTEN_STA0 INFRACFG_AO_REG(0x0224) +#define INFRA_TOPAXI_PROTECTEN_STA1 INFRACFG_AO_REG(0x0228) +#define INFRA_TOPAXI_PROTECTEN_SET INFRACFG_AO_REG(0x02a0) +#define INFRA_TOPAXI_PROTECTEN_CLR INFRACFG_AO_REG(0x02a4) +#define INFRA_TOPAXI_PROTECTEN_1 INFRACFG_AO_REG(0x0250) +#define INFRA_TOPAXI_PROTECTEN_STA0_1 INFRACFG_AO_REG(0x0254) +#define INFRA_TOPAXI_PROTECTEN_STA1_1 INFRACFG_AO_REG(0x0258) +#define INFRA_TOPAXI_PROTECTEN_1_SET INFRACFG_AO_REG(0x02a8) +#define INFRA_TOPAXI_PROTECTEN_1_CLR INFRACFG_AO_REG(0x02ac) + +/* bit fields of INFRA_TOPAXI_PROTECTEN */ +#define MP0_SPMC_PROT_STEP1_0_MASK BIT(12) +#define MP0_SPMC_PROT_STEP1_1_MASK (BIT(26) | BIT(12)) + +/* === SPARK */ +#define VOLTAGE_04 U(0x40) +#define VOLTAGE_05 U(0x60) + +#define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200) +#define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334) +#define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340) + +/* bit fields of CPU0_ILDO_CONTROL5 */ +#define ILDO_RET_VOSEL GENMASK(7, 0) + +/* bit fields of PTP3_CPU_SPMC_SW_CFG */ +#define SW_SPARK_EN BIT(0) + +/* bit fields of CPU0_ILDO_CONTROL8 */ +#define ILDO_BYPASS_B BIT(0) + +static const struct per_cpu_reg MCUCFG_SPARK[] = { + { .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U } +}; + +static const struct per_cpu_reg ILDO_CONTROL5[] = { + { .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U } +}; + +static const struct per_cpu_reg ILDO_CONTROL8[] = { + { .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U } +}; + +#endif /* MTSPMC_PRIVATE_H */ diff --git a/plat/mediatek/mt8192/include/mcucfg.h b/plat/mediatek/mt8192/include/mcucfg.h new file mode 100644 index 0000000..046cf73 --- /dev/null +++ b/plat/mediatek/mt8192/include/mcucfg.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCUCFG_H +#define MCUCFG_H + +#ifndef __ASSEMBLER__ +#include <stdint.h> +#endif /* __ASSEMBLER__ */ + +#include <platform_def.h> + +#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs)) + +#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8)) +#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8)) + +#define MP2_CPUCFG MCUCFG_REG(0x2208) + +#define MP2_CPU0_STANDBYWFE BIT(4) +#define MP2_CPU1_STANDBYWFE BIT(5) + +#define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788) +#define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C) +#define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790) + +#define sw_spark_en BIT(0) +#define sw_no_wait_for_q_channel BIT(1) +#define sw_fsm_override BIT(2) +#define sw_logic_pre1_pdb BIT(3) +#define sw_logic_pre2_pdb BIT(4) +#define sw_logic_pdb BIT(5) +#define sw_iso BIT(6) +#define sw_sram_sleepb (U(0x3F) << 7) +#define sw_sram_isointb BIT(13) +#define sw_clk_dis BIT(14) +#define sw_ckiso BIT(15) +#define sw_pd (U(0x3F) << 16) +#define sw_hot_plug_reset BIT(22) +#define sw_pwr_on_override_en BIT(23) +#define sw_pwr_on BIT(24) +#define sw_coq_dis BIT(25) +#define logic_pdbo_all_off_ack BIT(26) +#define logic_pdbo_all_on_ack BIT(27) +#define logic_pre2_pdbo_all_on_ack BIT(28) +#define logic_pre1_pdbo_all_on_ack BIT(29) + + +#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \ + (MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4) + +#define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30) +#define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34) +#define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38) +#define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C) + +#define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30) +#define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34) +#define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38) +#define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C) + +#define cpu_sw_spark_en BIT(0) +#define cpu_sw_no_wait_for_q_channel BIT(1) +#define cpu_sw_fsm_override BIT(2) +#define cpu_sw_logic_pre1_pdb BIT(3) +#define cpu_sw_logic_pre2_pdb BIT(4) +#define cpu_sw_logic_pdb BIT(5) +#define cpu_sw_iso BIT(6) +#define cpu_sw_sram_sleepb BIT(7) +#define cpu_sw_sram_isointb BIT(8) +#define cpu_sw_clk_dis BIT(9) +#define cpu_sw_ckiso BIT(10) +#define cpu_sw_pd (U(0x1F) << 11) +#define cpu_sw_hot_plug_reset BIT(16) +#define cpu_sw_powr_on_override_en BIT(17) +#define cpu_sw_pwr_on BIT(18) +#define cpu_spark2ldo_allswoff BIT(19) +#define cpu_pdbo_all_on_ack BIT(20) +#define cpu_pre2_pdbo_allon_ack BIT(21) +#define cpu_pre1_pdbo_allon_ack BIT(22) + +/* CPC related registers */ +#define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714) +#define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804) +#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814) +#define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818) +#define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c) +#define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824) +#define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828) +#define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8) +#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac) +#define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00) +#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04) +#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08) +#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c) +#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10) +#define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14) +#define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20) +#define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70) +#define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74) + +#define SPARK2LDO MCUCFG_REG(0x2700) +/* APB Module mcucfg */ +#define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000) +#define MP0_AXI_CONFIG MCUCFG_REG(0x02C) +#define MP0_MISC_CONFIG0 MCUCFG_REG(0x030) +#define MP0_MISC_CONFIG1 MCUCFG_REG(0x034) +#define MP0_MISC_CONFIG2 MCUCFG_REG(0x038) +#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8)) +#define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C) +#define MP0_MISC_CONFIG9 MCUCFG_REG(0x054) +#define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064) + +#define MP0_RW_RSVD0 MCUCFG_REG(0x06C) + + +#define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200) +#define MP1_AXI_CONFIG MCUCFG_REG(0x22C) +#define MP1_MISC_CONFIG0 MCUCFG_REG(0x230) +#define MP1_MISC_CONFIG1 MCUCFG_REG(0x234) +#define MP1_MISC_CONFIG2 MCUCFG_REG(0x238) +#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8)) +#define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C) +#define MP1_MISC_CONFIG9 MCUCFG_REG(0x254) +#define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264) + +#define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740) +#define SYNC_DCM_CONFIG MCUCFG_REG(0x744) + +#define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0) + +#define MP0_SPMC MCUCFG_REG(0x788) +#define MP1_SPMC MCUCFG_REG(0x78C) +#define MP2_AXI_CONFIG MCUCFG_REG(0x220C) +#define MP2_AXI_CONFIG_ACINACTM BIT(0) +#define MP2_AXI_CONFIG_AINACTS BIT(4) + +#define MPx_AXI_CONFIG_ACINACTM BIT(4) +#define MPx_AXI_CONFIG_AINACTS BIT(5) + +#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28) + +#define MP0_CPU0_STANDBYWFE BIT(20) +#define MP0_CPU1_STANDBYWFE BIT(21) +#define MP0_CPU2_STANDBYWFE BIT(22) +#define MP0_CPU3_STANDBYWFE BIT(23) + +#define MP1_CPU0_STANDBYWFE BIT(20) +#define MP1_CPU1_STANDBYWFE BIT(21) +#define MP1_CPU2_STANDBYWFE BIT(22) +#define MP1_CPU3_STANDBYWFE BIT(23) + +#define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00) +#define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04) +#define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08) +#define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00) +#define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04) +#define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08) + +#define MP2_PWR_RST_CTL MCUCFG_REG(0x2008) +#define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0) +#define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4) + +#define MP2_COQ MCUCFG_REG(0x22BC) +#define MP2_COQ_SW_DIS BIT(0) + +#define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400) +#define MP2_CA15M_MON_L MCUCFG_REG(0x2404) + +#define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430) +#define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438) +#define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434) +#define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C) + +#define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068) +#define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268) +#define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C) + +#define MP2_SW_RST_B BIT(0) +#define MP2_TOPAON_APB_MASK BIT(1) + +#define B_SW_HOT_PLUG_RESET BIT(30) + +#define B_SW_PD_OFFSET 18U +#define B_SW_PD (U(0x3f) << B_SW_PD_OFFSET) + +#define B_SW_SRAM_SLEEPB_OFFSET 12U +#define B_SW_SRAM_SLEEPB (U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET) + +#define B_SW_SRAM_ISOINTB BIT(9) +#define B_SW_ISO BIT(8) +#define B_SW_LOGIC_PDB BIT(7) +#define B_SW_LOGIC_PRE2_PDB BIT(6) +#define B_SW_LOGIC_PRE1_PDB BIT(5) +#define B_SW_FSM_OVERRIDE BIT(4) +#define B_SW_PWR_ON BIT(3) +#define B_SW_PWR_ON_OVERRIDE_EN BIT(2) + +#define B_FSM_STATE_OUT_OFFSET (6U) +#define B_FSM_STATE_OUT_MASK (U(0x1f) << B_FSM_STATE_OUT_OFFSET) +#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5) +#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4) +#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3) +#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2) + +#define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET) +#define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET) +#define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET) + +#ifndef __ASSEMBLER__ +/* cpu boot mode */ +enum { + MP0_CPUCFG_64BIT_SHIFT = 12U, + MP1_CPUCFG_64BIT_SHIFT = 28U, + MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT, + MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT +}; + +enum { + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U, + + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = + U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = + U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = + U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = + U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = + U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT +}; + +enum { + MP1_AINACTS_SHIFT = 4U, + MP1_AINACTS = 1U << MP1_AINACTS_SHIFT +}; + +enum { + MP1_SW_CG_GEN_SHIFT = 12U, + MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT +}; + +enum { + MP1_L2RSTDISABLE_SHIFT = 14U, + MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT +}; +#endif /* __ASSEMBLER__ */ + +#endif /* MCUCFG_H */ diff --git a/plat/mediatek/mt8192/include/plat_helpers.h b/plat/mediatek/mt8192/include/plat_helpers.h new file mode 100644 index 0000000..9b550ee --- /dev/null +++ b/plat/mediatek/mt8192/include/plat_helpers.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLAT_HELPERS_H__ +#define __PLAT_HELPERS_H__ + +unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); + +#endif /* __PLAT_HELPERS_H__ */ diff --git a/plat/mediatek/mt8192/include/plat_macros.S b/plat/mediatek/mt8192/include/plat_macros.S new file mode 100644 index 0000000..7d17e36 --- /dev/null +++ b/plat/mediatek/mt8192/include/plat_macros.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <platform_def.h> + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception + * is taken in BL31. + * Clobbers: x0 - x10, x26, x27, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* To-do: GIC owner */ + /* To-do: CCI owner */ + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/mediatek/mt8192/include/plat_mtk_lpm.h b/plat/mediatek/mt8192/include/plat_mtk_lpm.h new file mode 100644 index 0000000..deaac97 --- /dev/null +++ b/plat/mediatek/mt8192/include/plat_mtk_lpm.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MTK_LPM_H +#define PLAT_MTK_LPM_H + +#include <lib/psci/psci.h> +#include <lib/utils_def.h> + +#define MT_IRQ_REMAIN_MAX U(32) +#define MT_IRQ_REMAIN_CAT_LOG BIT(31) + +struct mt_irqremain { + unsigned int count; + unsigned int irqs[MT_IRQ_REMAIN_MAX]; + unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX]; + unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX]; +}; + +#define PLAT_RC_STATUS_READY BIT(0) +#define PLAT_RC_STATUS_FEATURE_EN BIT(1) +#define PLAT_RC_STATUS_UART_NONSLEEP BIT(31) + +struct mt_lpm_tz { + int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state); + int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state); + + int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state); + int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state); + + int (*pwr_cluster_on)(unsigned int cpu, + const psci_power_state_t *state); + int (*pwr_cluster_dwn)(unsigned int cpu, + const psci_power_state_t *state); + + int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state); + int (*pwr_mcusys_on_finished)(unsigned int cpu, + const psci_power_state_t *state); + int (*pwr_mcusys_dwn)(unsigned int cpu, + const psci_power_state_t *state); +}; + +const struct mt_lpm_tz *mt_plat_cpu_pm_init(void); + +#endif /* PLAT_MTK_LPM_H */ diff --git a/plat/mediatek/mt8192/include/plat_pm.h b/plat/mediatek/mt8192/include/plat_pm.h new file mode 100644 index 0000000..a2881ce --- /dev/null +++ b/plat/mediatek/mt8192/include/plat_pm.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PM_H +#define PLAT_PM_H + +#include <lib/utils_def.h> + +#define MT_PLAT_PWR_STATE_CPU U(1) +#define MT_PLAT_PWR_STATE_CLUSTER U(2) +#define MT_PLAT_PWR_STATE_MCUSYS U(3) +#define MT_PLAT_PWR_STATE_SUSPEND2IDLE U(8) +#define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND U(9) + +#define MTK_LOCAL_STATE_RUN U(0) +#define MTK_LOCAL_STATE_RET U(1) +#define MTK_LOCAL_STATE_OFF U(2) + +#define MTK_AFFLVL_CPU U(0) +#define MTK_AFFLVL_CLUSTER U(1) +#define MTK_AFFLVL_MCUSYS U(2) +#define MTK_AFFLVL_SYSTEM U(3) + +#define IS_CLUSTER_OFF_STATE(s) \ + is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER]) +#define IS_MCUSYS_OFF_STATE(s) \ + is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS]) +#define IS_SYSTEM_SUSPEND_STATE(s) \ + is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM]) + +#define IS_PLAT_SUSPEND_ID(stateid)\ + ((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) \ + || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND)) + +#endif /* PLAT_PM_H */ diff --git a/plat/mediatek/mt8192/include/plat_private.h b/plat/mediatek/mt8192/include/plat_private.h new file mode 100644 index 0000000..42ca415 --- /dev/null +++ b/plat/mediatek/mt8192/include/plat_private.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_configure_mmu_el3(uintptr_t total_base, + uintptr_t total_size, + uintptr_t ro_start, + uintptr_t ro_limit); + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/mediatek/mt8192/include/plat_sip_calls.h b/plat/mediatek/mt8192/include/plat_sip_calls.h new file mode 100644 index 0000000..fdc7bea --- /dev/null +++ b/plat/mediatek/mt8192/include/plat_sip_calls.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SIP_CALLS_H +#define PLAT_SIP_CALLS_H + +/******************************************************************************* + * Plat SiP function constants + ******************************************************************************/ +#define MTK_PLAT_SIP_NUM_CALLS (4) + +#endif /* PLAT_SIP_CALLS_H */ diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h new file mode 100644 index 0000000..ec377b5 --- /dev/null +++ b/plat/mediatek/mt8192/include/platform_def.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + + +#define PLAT_PRIMARY_CPU 0x0 + +#define MT_GIC_BASE 0x0c000000 +#define PLAT_MT_CCI_BASE 0x0c500000 +#define MCUCFG_BASE 0x0c530000 + +#define IO_PHYS 0x10000000 + +/* Aggregate of all devices for MMU mapping */ +#define MTK_DEV_RNG0_BASE IO_PHYS +#define MTK_DEV_RNG0_SIZE 0x10000000 +#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) +#define MTK_DEV_RNG1_SIZE 0x10000000 +#define MTK_DEV_RNG2_BASE 0x0c000000 +#define MTK_DEV_RNG2_SIZE 0x600000 +#define MTK_MCDI_SRAM_BASE 0x11B000 +#define MTK_MCDI_SRAM_MAP_SIZE 0x1000 + +#define APUSYS_BASE 0x19000000 +#define APUSYS_SCTRL_REVISER_BASE 0x19021000 +#define APUSYS_SCTRL_REVISER_SIZE 0x1000 +#define APUSYS_APU_S_S_4_BASE 0x190F2000 +#define APUSYS_APU_S_S_4_SIZE 0x1000 +#define APUSYS_APC_AO_WRAPPER_BASE 0x190F8000 +#define APUSYS_APC_AO_WRAPPER_SIZE 0x1000 +#define APUSYS_NOC_DAPC_AO_BASE 0x190FC000 +#define APUSYS_NOC_DAPC_AO_SIZE 0x1000 + +#define TOPCKGEN_BASE (IO_PHYS + 0x00000000) +#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) +#define GPIO_BASE (IO_PHYS + 0x00005000) +#define SPM_BASE (IO_PHYS + 0x00006000) +#define APMIXEDSYS (IO_PHYS + 0x0000C000) +#define DVFSRC_BASE (IO_PHYS + 0x00012000) +#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000) +#define DEVAPC_INFRA_AO_BASE (IO_PHYS + 0x00030000) +#define DEVAPC_PERI_AO_BASE (IO_PHYS + 0x00034000) +#define DEVAPC_PERI_AO2_BASE (IO_PHYS + 0x00038000) +#define DEVAPC_PERI_PAR_AO_BASE (IO_PHYS + 0x0003C000) +#define EMI_BASE (IO_PHYS + 0x00219000) +#define EMI_MPU_BASE (IO_PHYS + 0x00226000) +#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) +#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000) +#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) +#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) +#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) +#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) +#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000) +#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) +#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000) +#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000) +#define MMSYS_BASE (IO_PHYS + 0x04000000) +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define UART0_BASE (IO_PHYS + 0x01002000) +#define UART1_BASE (IO_PHYS + 0x01003000) + +#define UART_BAUDRATE 115200 + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_TICKS 13000000 +#define SYS_COUNTER_FREQ_IN_MHZ 13 + +/******************************************************************************* + * GIC-600 & interrupt handling related constants + ******************************************************************************/ + +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE MT_GIC_BASE +#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) + +#define SYS_CIRQ_BASE (IO_PHYS + 0x204000) +#define CIRQ_REG_NUM 14 +#define CIRQ_IRQ_NUM 439 +#define CIRQ_SPI_START 64 +#define MD_WDT_IRQ_BIT_ID 110 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLATFORM_STACK_SIZE 0x800 + +#define PLAT_MAX_PWR_LVL U(3) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(9) + +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_MCUSYS_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(8) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) + +#define SOC_CHIP_ID U(0x8192) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define TZRAM_BASE 0x54600000 +#define TZRAM_SIZE 0x00030000 + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES 16 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) +#endif /* PLATFORM_DEF_H */ diff --git a/plat/mediatek/mt8192/include/rtc.h b/plat/mediatek/mt8192/include/rtc.h new file mode 100644 index 0000000..a9c7bc8 --- /dev/null +++ b/plat/mediatek/mt8192/include/rtc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RTC_H +#define RTC_H + +#include <rtc_mt6359p.h> + +#endif /* RTC_H */ diff --git a/plat/mediatek/mt8192/plat_pm.c b/plat/mediatek/mt8192/plat_pm.c new file mode 100644 index 0000000..018e418 --- /dev/null +++ b/plat/mediatek/mt8192/plat_pm.c @@ -0,0 +1,398 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* common headers */ +#include <assert.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/gpio.h> +#include <lib/psci/psci.h> + +/* platform specific headers */ +#include <mt_gic_v3.h> +#include <mtk_ptp3_common.h> +#include <mtspmc.h> +#include <plat/common/platform.h> +#include <plat_dfd.h> +#include <plat_mtk_lpm.h> +#include <plat_params.h> +#include <plat_pm.h> +#include <pmic.h> +#include <rtc.h> + +/* + * Cluster state request: + * [0] : The CPU requires cluster power down + * [1] : The CPU requires cluster power on + */ +#define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff) +#define coordinate_cluster_pwron() coordinate_cluster(1) +#define coordinate_cluster_pwroff() coordinate_cluster(0) + +/* platform secure entry point */ +static uintptr_t secure_entrypoint; +/* per-CPU power state */ +static unsigned int plat_power_state[PLATFORM_CORE_COUNT]; + +/* platform CPU power domain - ops */ +static const struct mt_lpm_tz *plat_mt_pm; + +#define plat_mt_pm_invoke(_name, _cpu, _state) ({ \ + int ret = -1; \ + if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ + ret = plat_mt_pm->_name(_cpu, _state); \ + } \ + ret; }) + +#define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \ + if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ + (void) plat_mt_pm->_name(_cpu, _state); \ + } \ + }) + +/* + * Common MTK_platform operations to power on/off a + * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. + */ + +static void plat_cpu_pwrdwn_common(unsigned int cpu, + const psci_power_state_t *state, unsigned int req_pstate) +{ + assert(cpu == plat_my_core_pos()); + + plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); + + if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) || + (req_pstate == 0U)) { /* hotplug off */ + coordinate_cluster_pwroff(); + } + + /* Prevent interrupts from spuriously waking up this CPU */ + mt_gic_rdistif_save(); + gicv3_cpuif_disable(cpu); + gicv3_rdistif_off(cpu); + /* PTP3 config */ + ptp3_deinit(cpu); +} + +static void plat_cpu_pwron_common(unsigned int cpu, + const psci_power_state_t *state, unsigned int req_pstate) +{ + assert(cpu == plat_my_core_pos()); + + plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); + + coordinate_cluster_pwron(); + + /* + * If mcusys does power down before then restore + * all CPUs' GIC Redistributors + */ + if (IS_MCUSYS_OFF_STATE(state)) { + mt_gic_rdistif_restore_all(); + } else { + gicv3_rdistif_on(cpu); + gicv3_cpuif_enable(cpu); + mt_gic_rdistif_init(); + mt_gic_rdistif_restore(); + } + + /* PTP3 config */ + ptp3_init(cpu); +} + +/* + * Common MTK_platform operations to power on/off a + * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. + */ + +static void plat_cluster_pwrdwn_common(unsigned int cpu, + const psci_power_state_t *state, unsigned int req_pstate) +{ + assert(cpu == plat_my_core_pos()); + + if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) { + coordinate_cluster_pwron(); + + /* TODO: return on fail. + * Add a 'return' here before adding any code following + * the if-block. + */ + } +} + +static void plat_cluster_pwron_common(unsigned int cpu, + const psci_power_state_t *state, unsigned int req_pstate) +{ + assert(cpu == plat_my_core_pos()); + + if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) { + /* TODO: return on fail. + * Add a 'return' here before adding any code following + * the if-block. + */ + } +} + +/* + * Common MTK_platform operations to power on/off a + * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. + */ + +static void plat_mcusys_pwrdwn_common(unsigned int cpu, + const psci_power_state_t *state, unsigned int req_pstate) +{ + assert(cpu == plat_my_core_pos()); + + if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) { + return; /* return on fail */ + } + + mt_gic_distif_save(); + gic_sgi_save_all(); +} + +static void plat_mcusys_pwron_common(unsigned int cpu, + const psci_power_state_t *state, unsigned int req_pstate) +{ + assert(cpu == plat_my_core_pos()); + + if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) { + return; /* return on fail */ + } + + mt_gic_init(); + mt_gic_distif_restore(); + gic_sgi_restore_all(); + + dfd_resume(); + + plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state); +} + +/* + * plat_psci_ops implementation + */ + +static void plat_cpu_standby(plat_local_state_t cpu_state) +{ + uint64_t scr; + + scr = read_scr_el3(); + write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); + + isb(); + dsb(); + wfi(); + + write_scr_el3(scr); +} + +static int plat_power_domain_on(u_register_t mpidr) +{ + unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); + unsigned int cluster = 0U; + + if (cpu >= PLATFORM_CORE_COUNT) { + return PSCI_E_INVALID_PARAMS; + } + + if (!spm_get_cluster_powerstate(cluster)) { + spm_poweron_cluster(cluster); + } + + /* init CPU reset arch as AARCH64 */ + mcucfg_init_archstate(cluster, cpu, true); + mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); + spm_poweron_cpu(cluster, cpu); + + return PSCI_E_SUCCESS; +} + +static void plat_power_domain_on_finish(const psci_power_state_t *state) +{ + unsigned long mpidr = read_mpidr_el1(); + unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); + + assert(cpu < PLATFORM_CORE_COUNT); + + /* Allow IRQs to wakeup this core in IDLE flow */ + mcucfg_enable_gic_wakeup(0U, cpu); + + if (IS_CLUSTER_OFF_STATE(state)) { + plat_cluster_pwron_common(cpu, state, 0U); + } + + plat_cpu_pwron_common(cpu, state, 0U); +} + +static void plat_power_domain_off(const psci_power_state_t *state) +{ + unsigned long mpidr = read_mpidr_el1(); + unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); + + assert(cpu < PLATFORM_CORE_COUNT); + + plat_cpu_pwrdwn_common(cpu, state, 0U); + spm_poweroff_cpu(0U, cpu); + + /* prevent unintended IRQs from waking up the hot-unplugged core */ + mcucfg_disable_gic_wakeup(0U, cpu); + + if (IS_CLUSTER_OFF_STATE(state)) { + plat_cluster_pwrdwn_common(cpu, state, 0U); + } +} + +static void plat_power_domain_suspend(const psci_power_state_t *state) +{ + unsigned int cpu = plat_my_core_pos(); + + assert(cpu < PLATFORM_CORE_COUNT); + + plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state); + + /* Perform the common CPU specific operations */ + plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]); + + if (IS_CLUSTER_OFF_STATE(state)) { + /* Perform the common cluster specific operations */ + plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]); + } + + if (IS_MCUSYS_OFF_STATE(state)) { + /* Perform the common mcusys specific operations */ + plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]); + } +} + +static void plat_power_domain_suspend_finish(const psci_power_state_t *state) +{ + unsigned int cpu = plat_my_core_pos(); + + assert(cpu < PLATFORM_CORE_COUNT); + + if (IS_MCUSYS_OFF_STATE(state)) { + /* Perform the common mcusys specific operations */ + plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]); + } + + if (IS_CLUSTER_OFF_STATE(state)) { + /* Perform the common cluster specific operations */ + plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]); + } + + /* Perform the common CPU specific operations */ + plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]); + + plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state); +} + +static int plat_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int pstate = psci_get_pstate_type(power_state); + unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state); + unsigned int cpu = plat_my_core_pos(); + + if (pstate == PSTATE_TYPE_STANDBY) { + req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; + } else { + unsigned int i; + unsigned int pstate_id = psci_get_pstate_id(power_state); + plat_local_state_t s = MTK_LOCAL_STATE_OFF; + + /* Use pstate_id to be power domain state */ + if (pstate_id > s) { + s = (plat_local_state_t)pstate_id; + } + + for (i = 0U; i <= aff_lvl; i++) { + req_state->pwr_domain_state[i] = s; + } + } + + plat_power_state[cpu] = power_state; + return PSCI_E_SUCCESS; +} + +static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + unsigned int lv; + unsigned int cpu = plat_my_core_pos(); + + for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { + req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE; + } + + plat_power_state[cpu] = + psci_make_powerstate( + MT_PLAT_PWR_STATE_SYSTEM_SUSPEND, + PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL); + + flush_dcache_range((uintptr_t) + &plat_power_state[cpu], + sizeof(plat_power_state[cpu])); +} + +static void __dead2 plat_mtk_system_off(void) +{ + INFO("MTK System Off\n"); + + rtc_power_off_sequence(); + pmic_power_off(); + + wfi(); + ERROR("MTK System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 plat_mtk_system_reset(void) +{ + struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset(); + + INFO("MTK System Reset\n"); + + gpio_set_value(gpio_reset->index, gpio_reset->polarity); + + wfi(); + ERROR("MTK System Reset: operation not handled.\n"); + panic(); +} + +static const plat_psci_ops_t plat_psci_ops = { + .system_reset = plat_mtk_system_reset, + .cpu_standby = plat_cpu_standby, + .pwr_domain_on = plat_power_domain_on, + .pwr_domain_on_finish = plat_power_domain_on_finish, + .pwr_domain_off = plat_power_domain_off, + .pwr_domain_suspend = plat_power_domain_suspend, + .pwr_domain_suspend_finish = plat_power_domain_suspend_finish, + .system_off = plat_mtk_system_off, + .validate_power_state = plat_validate_power_state, + .get_sys_suspend_power_state = plat_get_sys_suspend_power_state +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &plat_psci_ops; + secure_entrypoint = sec_entrypoint; + + /* + * init the warm reset config for boot CPU + * reset arch as AARCH64 + * reset addr as function bl31_warm_entrypoint() + */ + mcucfg_init_archstate(0U, 0U, true); + mcucfg_set_bootaddr(0U, 0U, secure_entrypoint); + + spmc_init(); + plat_mt_pm = mt_plat_cpu_pm_init(); + + return 0; +} diff --git a/plat/mediatek/mt8192/plat_sip_calls.c b/plat/mediatek/mt8192/plat_sip_calls.c new file mode 100644 index 0000000..0fffed5 --- /dev/null +++ b/plat/mediatek/mt8192/plat_sip_calls.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <mtk_apusys.h> +#include <mtk_sip_svc.h> +#include <mt_spm_vcorefs.h> +#include <plat_dfd.h> +#include "plat_sip_calls.h" + +uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uint64_t ret; + uint32_t rnd_val0 = 0U; + + switch (smc_fid) { + case MTK_SIP_VCORE_CONTROL_AARCH32: + case MTK_SIP_VCORE_CONTROL_AARCH64: + ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); + SMC_RET2(handle, ret, x4); + break; + case MTK_SIP_APUSYS_CONTROL_AARCH32: + case MTK_SIP_APUSYS_CONTROL_AARCH64: + ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); + SMC_RET2(handle, ret, rnd_val0); + break; + case MTK_SIP_KERNEL_DFD_AARCH32: + case MTK_SIP_KERNEL_DFD_AARCH64: + ret = dfd_smc_dispatcher(x1, x2, x3, x4); + SMC_RET1(handle, ret); + break; + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} diff --git a/plat/mediatek/mt8192/plat_topology.c b/plat/mediatek/mt8192/plat_topology.c new file mode 100644 index 0000000..8c1231a --- /dev/null +++ b/plat/mediatek/mt8192/plat_topology.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Project Includes */ +#include <arch.h> +#include <arch_helpers.h> +#include <lib/psci/psci.h> + +/* Platform Includes */ +#include <plat_helpers.h> +#include <platform_def.h> + +const unsigned char mtk_power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* Number of children for the root node */ + PLATFORM_MCUSYS_COUNT, + /* Number of children for the mcusys node */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the MT8192 default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return mtk_power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + if (read_mpidr() & MPIDR_MT_MASK) { + /* ARMv8.2 arch */ + if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { + return -1; + } + return plat_mediatek_calc_core_pos(mpidr); + } + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { + return -1; + } + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -1; + } + + /* + * Validate cpu_id by checking whether it represents a CPU in + * one of the two clusters present on the platform. + */ + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { + return -1; + } + + return (cpu_id + (cluster_id * 8)); +} diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk new file mode 100644 index 0000000..a19fc45 --- /dev/null +++ b/plat/mediatek/mt8192/platform.mk @@ -0,0 +1,103 @@ +# +# Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +MTK_PLAT := plat/mediatek +MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} + +PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ + -I${MTK_PLAT}/common/lpm/ \ + -I${MTK_PLAT}/drivers/cirq/ \ + -I${MTK_PLAT}/drivers/gic600/ \ + -I${MTK_PLAT}/drivers/gpio/ \ + -I${MTK_PLAT}/drivers/pmic/ \ + -I${MTK_PLAT}/drivers/pmic_wrap/ \ + -I${MTK_PLAT}/drivers/rtc/ \ + -I${MTK_PLAT}/drivers/timer/ \ + -I${MTK_PLAT}/drivers/uart/ \ + -I${MTK_PLAT}/include/ \ + -I${MTK_PLAT_SOC}/include/ \ + -I${MTK_PLAT_SOC}/drivers/ \ + -I${MTK_PLAT_SOC}/drivers/apusys/ \ + -I${MTK_PLAT_SOC}/drivers/dcm \ + -I${MTK_PLAT_SOC}/drivers/devapc \ + -I${MTK_PLAT_SOC}/drivers/dfd \ + -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ + -I${MTK_PLAT_SOC}/drivers/gpio/ \ + -I${MTK_PLAT_SOC}/drivers/mcdi/ \ + -I${MTK_PLAT_SOC}/drivers/pmic/ \ + -I${MTK_PLAT_SOC}/drivers/ptp3/ \ + -I${MTK_PLAT_SOC}/drivers/spmc/ + +GICV3_SUPPORT_GIC600 := 1 +include drivers/arm/gic/v3/gicv3.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} \ + plat/common/aarch64/crash_console_helpers.S \ + plat/common/plat_psci_common.c + +BL31_SOURCES += common/desc_image_load.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/ti/uart/aarch64/16550_console.S \ + drivers/gpio/gpio.c \ + lib/bl_aux_params/bl_aux_params.c \ + lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a76.S \ + plat/common/plat_gicv3.c \ + ${MTK_PLAT}/common/mtk_plat_common.c \ + ${MTK_PLAT}/common/mtk_sip_svc.c \ + ${MTK_PLAT}/common/params_setup.c \ + ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ + ${MTK_PLAT}/drivers/cirq/mt_cirq.c \ + ${MTK_PLAT}/drivers/gic600/mt_gic_v3.c \ + ${MTK_PLAT}/drivers/gpio/mtgpio_common.c \ + ${MTK_PLAT}/drivers/pmic/pmic.c \ + ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init_v2.c \ + ${MTK_PLAT}/drivers/rtc/rtc_common.c \ + ${MTK_PLAT}/drivers/rtc/rtc_mt6359p.c \ + ${MTK_PLAT}/drivers/timer/mt_timer.c \ + ${MTK_PLAT}/drivers/uart/uart.c \ + ${MTK_PLAT_SOC}/aarch64/platform_common.c \ + ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ + ${MTK_PLAT_SOC}/bl31_plat_setup.c \ + ${MTK_PLAT_SOC}/plat_pm.c \ + ${MTK_PLAT_SOC}/plat_topology.c \ + ${MTK_PLAT_SOC}/plat_sip_calls.c \ + ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \ + ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys_apc.c \ + ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \ + ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \ + ${MTK_PLAT_SOC}/drivers/devapc/devapc.c \ + ${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \ + ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \ + ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ + ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \ + ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \ + ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \ + ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \ + ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \ + ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c + +# Build SPM drivers +include ${MTK_PLAT_SOC}/drivers/spm/build.mk + +# Configs for A76 and A55 +HW_ASSISTED_COHERENCY := 1 +USE_COHERENT_MEM := 0 +CTX_INCLUDE_AARCH32_REGS := 0 + +# indicate the reset vector address can be programmed +PROGRAMMABLE_RESET_ADDRESS := 1 + +COLD_BOOT_SINGLE_CPU := 1 + +MACH_MT8192 := 1 +$(eval $(call add_define,MACH_MT8192)) + +include lib/coreboot/coreboot.mk + |