diff options
Diffstat (limited to 'plat/nxp/soc-ls1046a/ls1046aqds')
| -rw-r--r-- | plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c | 91 | ||||
| -rw-r--r-- | plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h | 79 | ||||
| -rw-r--r-- | plat/nxp/soc-ls1046a/ls1046aqds/platform.c | 28 | ||||
| -rw-r--r-- | plat/nxp/soc-ls1046a/ls1046aqds/platform.mk | 39 | ||||
| -rw-r--r-- | plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h | 13 | ||||
| -rw-r--r-- | plat/nxp/soc-ls1046a/ls1046aqds/policy.h | 16 |
6 files changed, 266 insertions, 0 deletions
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c new file mode 100644 index 0000000..89c9c0a --- /dev/null +++ b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c @@ -0,0 +1,91 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> + +#include <common/debug.h> +#include <ddr.h> +#include <lib/utils.h> + +#include <errata.h> +#include "platform_def.h" + +static const struct rc_timing rce[] = { + {U(1600), U(8), U(7)}, + {U(1867), U(8), U(7)}, + {U(2134), U(8), U(9)}, + {} +}; + +static const struct board_timing udimm[] = { + {U(0x04), rce, U(0x01020304), U(0x06070805)}, +}; + +int ddr_board_options(struct ddr_info *priv) +{ + int ret; + struct memctl_opt *popts = &priv->opt; + + if (popts->rdimm) { + debug("RDIMM parameters not set.\n"); + return -EINVAL; + } + + ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm)); + if (ret != 0) { + return ret; + } + + popts->wrlvl_override = U(1); + popts->wrlvl_sample = U(0x0); /* 32 clocks */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_TRAIN_EN | + DDR_CDR2_VREF_RANGE_2; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = U(0x70); + + return 0; +} + +long long init_ddr(void) +{ + int spd_addr[] = { NXP_SPD_EEPROM0 }; + struct ddr_info info; + struct sysinfo sys; + long long dram_size; + + zeromem(&sys, sizeof(sys)); + if (get_clocks(&sys)) { + ERROR("System clocks are not set\n"); + assert(0); + } + debug("platform clock %lu\n", sys.freq_platform); + debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); + debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); + + zeromem(&info, sizeof(struct ddr_info)); + info.num_ctlrs = 1; + info.dimm_on_ctlr = 1; + info.clk = get_ddr_freq(&sys, 0); + info.spd_addr = spd_addr; + info.ddr[0] = (void *)NXP_DDR_ADDR; + + dram_size = dram_init(&info); + + if (dram_size < 0) { + ERROR("DDR init failed.\n"); + } + +#ifdef ERRATA_SOC_A008850 + erratum_a008850_post(); +#endif + + return dram_size; +} diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h b/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h new file mode 100644 index 0000000..aa69a66 --- /dev/null +++ b/plat/nxp/soc-ls1046a/ls1046aqds/plat_def.h @@ -0,0 +1,79 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DEF_H +#define PLAT_DEF_H + +#include <arch.h> +/* Required without TBBR. + * To include the defines for DDR PHY + * Images. + */ +#include <tbbr_img_def.h> + +#include <policy.h> +#include <soc.h> + +#define NXP_SPD_EEPROM0 0x51 + +#define NXP_SYSCLK_FREQ 100000000 +#define NXP_DDRCLK_FREQ 100000000 + +/* UART related definition */ +#define NXP_CONSOLE_ADDR NXP_UART_ADDR +#define NXP_CONSOLE_BAUDRATE 115200 + +/* Size of cacheable stacks */ +#if defined(IMAGE_BL2) +#if defined(TRUSTED_BOARD_BOOT) +#define PLATFORM_STACK_SIZE 0x2000 +#else +#define PLATFORM_STACK_SIZE 0x1000 +#endif +#elif defined(IMAGE_BL31) +#define PLATFORM_STACK_SIZE 0x1000 +#endif + +/* SD block buffer */ +#define NXP_SD_BLOCK_BUF_SIZE (0x00100000) +#define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000) + +#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) + +/* IO defines as needed by IO driver framework */ +#define MAX_IO_DEVICES U(3) +#define MAX_IO_BLOCK_DEVICES U(1) +#define MAX_IO_HANDLES U(4) + +/* + * FIP image defines - Offset at which FIP Image would be present + * Image would include Bl31 , Bl33 and Bl32 (optional) + */ +#ifdef POLICY_FUSE_PROVISION +#define MAX_FIP_DEVICES U(2) +#endif + +#ifndef MAX_FIP_DEVICES +#define MAX_FIP_DEVICES U(1) +#endif + +/* + * ID of the secure physical generic timer interrupt used by the BL32. + */ +#define BL32_IRQ_SEC_PHY_TIMER 29 + +/* + * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_LS_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_LS_G0_IRQ_PROPS(grp) + +#endif diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/platform.c b/plat/nxp/soc-ls1046a/ls1046aqds/platform.c new file mode 100644 index 0000000..cef920f --- /dev/null +++ b/plat/nxp/soc-ls1046a/ls1046aqds/platform.c @@ -0,0 +1,28 @@ +/* + * Copyright 2020-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat_common.h> + +#pragma weak board_enable_povdd +#pragma weak board_disable_povdd + +bool board_enable_povdd(void) +{ +#ifdef CONFIG_POVDD_ENABLE + return true; +#else + return false; +#endif +} + +bool board_disable_povdd(void) +{ +#ifdef CONFIG_POVDD_ENABLE + return true; +#else + return false; +#endif +} diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/platform.mk b/plat/nxp/soc-ls1046a/ls1046aqds/platform.mk new file mode 100644 index 0000000..9600b93 --- /dev/null +++ b/plat/nxp/soc-ls1046a/ls1046aqds/platform.mk @@ -0,0 +1,39 @@ +# +# Copyright 2018-2022 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# board-specific build parameters +BOOT_MODE ?= qspi +BOARD := ls1046aqds +POVDD_ENABLE := no + + # DDR Compilation Configs +NUM_OF_DDRC := 1 +DDRC_NUM_DIMM := 1 +DDRC_NUM_CS := 4 +DDR_ECC_EN := yes +CONFIG_STATIC_DDR := 0 + +# On-Board Flash Details +QSPI_FLASH_SZ := 0x20000000 +NOR_FLASH_SZ := 0x20000000 + +# Platform specific features. +WARM_BOOT := no + +# Adding Platform files build files +BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ + ${BOARD_PATH}/platform.c + +SUPPORTED_BOOT_MODE := qspi \ + sd \ + nor \ + nand + +# Adding platform board build info +include plat/nxp/common/plat_make_helper/plat_common_def.mk + +# Adding SoC build info +include plat/nxp/soc-ls1046a/soc.mk diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h b/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h new file mode 100644 index 0000000..7f98bb1 --- /dev/null +++ b/plat/nxp/soc-ls1046a/ls1046aqds/platform_def.h @@ -0,0 +1,13 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <plat_def.h> +#include <plat_default_def.h> + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/policy.h b/plat/nxp/soc-ls1046a/ls1046aqds/policy.h new file mode 100644 index 0000000..c6c325f --- /dev/null +++ b/plat/nxp/soc-ls1046a/ls1046aqds/policy.h @@ -0,0 +1,16 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef POLICY_H +#define POLICY_H + +/* Set this to 0x0 to leave the default SMMU page size in sACR + * Set this to 0x1 to change the SMMU page size to 64K + */ +#define POLICY_SMMU_PAGESZ_64K 0x1 + +#endif /* POLICY_H */ |