diff options
Diffstat (limited to '')
| -rw-r--r-- | plat/xilinx/versal_net/aarch64/versal_net_common.c | 127 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/aarch64/versal_net_helpers.S | 110 |
2 files changed, 237 insertions, 0 deletions
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c new file mode 100644 index 0000000..c78b5d0 --- /dev/null +++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <drivers/generic_delay_timer.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> +#include <plat_ipi.h> + +#include <plat_private.h> +#include <versal_net_def.h> + +uint32_t platform_id, platform_version; + +/* + * Table of regions to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * configure_mmu_elx() will give the available subset of that, + */ +const mmap_region_t plat_versal_net_mmap[] = { + MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; + +const mmap_region_t *plat_versal_net_get_mmap(void) +{ + return plat_versal_net_mmap; +} + +/* For saving cpu clock for certain platform */ +uint32_t cpu_clock; + +char *board_name_decode(void) +{ + switch (platform_id) { + case VERSAL_NET_SPP: + return "IPP"; + case VERSAL_NET_EMU: + return "EMU"; + case VERSAL_NET_SILICON: + return "Silicon"; + case VERSAL_NET_QEMU: + return "QEMU"; + default: + return "Unknown"; + } +} + +void board_detection(void) +{ + uint32_t version; + + version = mmio_read_32(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + if (platform_id == VERSAL_NET_QEMU_COSIM) { + platform_id = VERSAL_NET_QEMU; + } + + if ((platform_id == VERSAL_NET_SPP) || + (platform_id == VERSAL_NET_EMU) || + (platform_id == VERSAL_NET_QEMU)) { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9U; + } + + /* Make sure that console is setup to see this message */ + VERBOSE("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10U, platform_version % 10U); +} + +void versal_net_config_setup(void) +{ + uint32_t val; + uintptr_t crl_base, iou_scntrs_base, psx_base; + + crl_base = VERSAL_NET_CRL; + iou_scntrs_base = VERSAL_NET_IOU_SCNTRS; + psx_base = PSX_CRF; + + /* Reset for system timestamp generator in FPX */ + mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); + + /* Global timer init - Program time stamp reference clk */ + val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET); + val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val); + + /* Clear reset of timestamp reg */ + mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0); + + /* Program freq register in System counter and enable system counter. */ + mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET, + cpu_clock); + mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, + VERSAL_NET_IOU_SCNTRS_CONTROL_EN); + + generic_delay_timer_init(); + +#if (TFA_NO_PM == 0) + /* Configure IPI data for versal_net */ + versal_net_ipi_config_table_init(); +#endif +} + +uint32_t plat_get_syscnt_freq2(void) +{ + return cpu_clock; +} diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S new file mode 100644 index 0000000..48082a6 --- /dev/null +++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <drivers/arm/gicv3.h> +#include <platform_def.h> + + .globl plat_secondary_cold_boot_setup + .globl plat_is_my_cpu_primary + .globl platform_mem_init + .globl plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * TODO: Should we read the PSYS register to make sure + * that the request has gone through. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + mrs x0, mpidr_el1 + + /* + * There is no sane reason to come out of this wfi. This + * cpu will be powered on and reset by the cpu_on pm api + */ + dsb sy + bl plat_panic_handler +endfunc plat_secondary_cold_boot_setup + +func plat_is_my_cpu_primary + mov x9, x30 + bl plat_my_core_pos + cmp x0, #VERSAL_NET_PRIMARY_CPU + cset x0, eq + ret x9 +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_core_pos_by_mpidr() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_core_pos_by_mpidr +endfunc plat_my_core_pos + + /* --------------------------------------------------------------------- + * We don't need to carry out any memory initialization on Versal NET + * platform. The Secure RAM is accessible straight away. + * --------------------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init +/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE + mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ + mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE + b console_pl011_core_init */ +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE + b console_pl011_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * void plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : void. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE + b console_pl011_core_flush +endfunc plat_crash_console_flush |