diff options
Diffstat (limited to '')
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_ipi.h | 58 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_macros.S | 118 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_pm_common.h | 25 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_private.h | 49 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/platform_def.h | 114 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/versal_net_def.h | 171 |
6 files changed, 535 insertions, 0 deletions
diff --git a/plat/xilinx/versal_net/include/plat_ipi.h b/plat/xilinx/versal_net/include/plat_ipi.h new file mode 100644 index 0000000..5255f8f --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_ipi.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Versal IPI management enums and defines */ + +#ifndef PLAT_IPI_H +#define PLAT_IPI_H + +#include <stdint.h> + +#include <ipi.h> + +/********************************************************************* + * IPI agent IDs macros + ********************************************************************/ +#define IPI_ID_PMC 1U +#define IPI_ID_APU 2U +#define IPI_ID_RPU0 3U +#define IPI_ID_RPU1 4U +#define IPI_ID_3 5U +#define IPI_ID_4 6U +#define IPI_ID_5 7U +#define IPI_ID_MAX 8U + +/********************************************************************* + * IPI message buffers + ********************************************************************/ +#define IPI_BUFFER_BASEADDR (0xEB3F0000U) + +#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U) + +#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U +#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U + +#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE +#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE + +#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET +#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET + +#define IPI_BUFFER_MAX_WORDS 8 + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +/********************************************************************* + * Platform specific IPI API declarations + ********************************************************************/ + +/* Configure IPI table for versal_net */ +void versal_net_ipi_config_table_init(void); + +#endif /* PLAT_IPI_H */ diff --git a/plat/xilinx/versal_net/include/plat_macros.S b/plat/xilinx/versal_net/include/plat_macros.S new file mode 100644 index 0000000..fb108b6 --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_macros.S @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv2.h> +#include <drivers/arm/gicv3.h> + +#include "../include/platform_def.h" + +.section .rodata.gic_reg_name, "aS" +/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" + +/* Applicable only to GICv3 with SRE enabled */ +icc_regs: + .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" + +/* Registers common to both GICv2 and GICv3 */ +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31 on Versal NET platform. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro versal_net_print_gic_regs + /* Check for GICv3 system register access */ + mrs x7, id_aa64pfr0_el1 + ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x7, #1 + b.ne print_gicv2 + + /* Check for SRE enable */ + mrs x8, ICC_SRE_EL3 + tst x8, #ICC_SRE_SRE_BIT + b.eq print_gicv2 + + /* Load the icc reg list to x6 */ + adr x6, icc_regs + /* Load the icc regs to gp regs used by str_in_crash_buf_print */ + mrs x8, ICC_HPPIR0_EL1 + mrs x9, ICC_HPPIR1_EL1 + mrs x10, ICC_CTLR_EL3 + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + b print_gic_common + +print_gicv2: + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + +print_gic_common: + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* + * Empty for now to handle more platforms variant. + * Uncomment it when versions are stable + */ + /* + mov_imm x17, PLAT_VERSAL_NET_GICD_BASE + mov_imm x16, PLAT_VERSAL_NET_GICR_BASE + versal_net_print_gic_regs + */ + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/xilinx/versal_net/include/plat_pm_common.h b/plat/xilinx/versal_net/include/plat_pm_common.h new file mode 100644 index 0000000..ad7b40f --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_pm_common.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains platform specific definitions of commonly used macros data types + * for PU Power Management. This file should be common for all PU's. + */ + +#ifndef PLAT_PM_COMMON_H +#define PLAT_PM_COMMON_H + +#include <stdint.h> + +#include <common/debug.h> + +#include "pm_defs.h" + +#define NON_SECURE_FLAG 1U +#define SECURE_FLAG 0U + +#endif /* PLAT_PM_COMMON_H */ diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h new file mode 100644 index 0000000..6a3bc19 --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_private.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +#include <bl31/interrupt_mgmt.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +typedef struct versal_intr_info_type_el3 { + uint32_t id; + interrupt_type_handler_t handler; +} versal_intr_info_type_el3_t; + +void versal_net_config_setup(void); + +const mmap_region_t *plat_versal_net_get_mmap(void); + +void plat_versal_net_gic_driver_init(void); +void plat_versal_net_gic_init(void); +void plat_versal_net_gic_cpuif_enable(void); +void plat_versal_net_gic_cpuif_disable(void); +void plat_versal_net_gic_pcpu_init(void); +void plat_versal_net_gic_save(void); +void plat_versal_net_gic_resume(void); +void plat_versal_net_gic_redistif_on(void); +void plat_versal_net_gic_redistif_off(void); + +extern uint32_t cpu_clock, platform_id, platform_version; +void board_detection(void); +char *board_name_decode(void); +uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, uint64_t flags); +int32_t sip_svc_setup_init(void); +/* + * Register handler to specific GIC entrance + * for INTR_TYPE_EL3 type of interrupt + */ +int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); + +#define PM_GET_CHIPID (24U) +#define IOCTL_OSPI_MUX_SELECT (21U) + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h new file mode 100644 index 0000000..696771f --- /dev/null +++ b/plat/xilinx/versal_net/include/platform_def.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include "versal_net_def.h" + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE U(0x440) + +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ + +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) + +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#ifndef VERSAL_NET_ATF_MEM_BASE +# define BL31_BASE U(0xBBF00000) +# define BL31_LIMIT U(0xBBFFFFFF) +#else +# define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE) +# define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE - 1) +# ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE +# define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \ + VERSAL_NET_ATF_MEM_PROGBITS_SIZE - 1) +# endif +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef VERSAL_NET_BL32_MEM_BASE +# define BL32_BASE U(0x60000000) +# define BL32_LIMIT U(0x7FFFFFFF) +#else +# define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE) +# define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE - 1) +#endif + +/******************************************************************************* + * BL33 specific defines. + ******************************************************************************/ +#ifndef PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) +#else +# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) +#endif + +/******************************************************************************* + * TSP specific defines. + ******************************************************************************/ +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1U) + +/* ID of the secure physical generic timer interrupt used by the TSP */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_DDR_LOWMEM_MAX U(0x80000000) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) +#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#define MAX_MMAP_REGIONS U(10) +#else +#define MAX_MMAP_REGIONS U(9) +#endif + +#define MAX_XLAT_TABLES U(8) + +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define PLAT_VERSAL_NET_GICD_BASE U(0xE2000000) +#define PLAT_VERSAL_NET_GICR_BASE U(0xE2060000) + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_VERSAL_IPI_IRQ 62 + +#define PLAT_VERSAL_NET_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h new file mode 100644 index 0000000..8cb5bf3 --- /dev/null +++ b/plat/xilinx/versal_net/include/versal_net_def.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VERSAL_NET_DEF_H +#define VERSAL_NET_DEF_H + +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +#define MAX_INTR_EL3 2 +/* This part is taken from U-Boot project under GPL that's why dual license above */ +#define __bf_shf(x) (__builtin_ffsll(x) - 1U) +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +/* List all consoles */ +#define VERSAL_NET_CONSOLE_ID_pl011 U(1) +#define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) +#define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) + +#define VERSAL_NET_CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) + +/* List all platforms */ +#define VERSAL_NET_SILICON U(0) +#define VERSAL_NET_SPP U(1) +#define VERSAL_NET_EMU U(2) +#define VERSAL_NET_QEMU U(3) +#define VERSAL_NET_QEMU_COSIM U(7) + +/* For platform detection */ +#define PMC_TAP U(0xF11A0000) +#define PMC_TAP_VERSION (PMC_TAP + 0x4U) +# define PLATFORM_MASK GENMASK(27U, 24U) +# define PLATFORM_VERSION_MASK GENMASK(31U, 28U) + +/* Global timer reset */ +#define PSX_CRF U(0xEC200000) +#define ACPU0_CLK_CTRL U(0x10C) +#define ACPU_CLK_CTRL_CLKACT BIT(25) + +#define RST_APU0_OFFSET U(0x300) +#define RST_APU_COLD_RESET BIT(0) +#define RST_APU_WARN_RESET BIT(4) +#define RST_APU_CLUSTER_COLD_RESET BIT(8) +#define RST_APU_CLUSTER_WARM_RESET BIT(9) + +#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) + +#define APU_PCLI U(0xECB10000) +#define APU_PCLI_CPU_STEP U(0x30) +#define APU_PCLI_CLUSTER_CPU_STEP (4U * APU_PCLI_CPU_STEP) +#define APU_PCLI_CLUSTER_OFFSET U(0x8000) +#define APU_PCLI_CLUSTER_STEP U(0x1000) +#define PCLI_PREQ_OFFSET U(0x4) +#define PREQ_CHANGE_REQUEST BIT(0) +#define PCLI_PSTATE_OFFSET U(0x8) +#define PCLI_PSTATE_VAL_SET U(0x48) +#define PCLI_PSTATE_VAL_CLEAR U(0x38) + +/* Firmware Image Package */ +#define VERSAL_NET_PRIMARY_CPU U(0) + +#define CORE_0_IEN_POWER_OFFSET (0x00000018U) +#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ + (0x30 * cpu_id))) +#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) +#define CORE_0_IDS_POWER_OFFSET (0x0000001CU) +#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ + (0x30 * cpu_id))) +#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) +#define CORE_PWRDN_EN_BIT_MASK (0x1U) + +/******************************************************************************* + * memory map related constants + ******************************************************************************/ +/* IPP 1.2/SPP 0.9 mapping */ +#define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ +#define DEVICE0_SIZE U(0x08000000) +#define DEVICE1_BASE U(0xE2000000) /* gic */ +#define DEVICE1_SIZE U(0x00800000) +#define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ +#define DEVICE2_SIZE U(0x01000000) +#define CRF_BASE U(0xFD1A0000) +#define CRF_SIZE U(0x00600000) +#define IPI_BASE U(0xEB300000) +#define IPI_SIZE U(0x00100000) + +/* CRL */ +#define VERSAL_NET_CRL U(0xEB5E0000) +#define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) +#define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) + +#define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) + +/* IOU SCNTRS */ +#define VERSAL_NET_IOU_SCNTRS U(0xEC920000) +#define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) +#define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) + +#define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1) + +#define APU_CLUSTER0 U(0xECC00000) +#define APU_RVBAR_L_0 U(0x40) +#define APU_RVBAR_H_0 U(0x44) +#define APU_CLUSTER_STEP U(0x100000) + +#define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) + +/******************************************************************************* + * IRQ constants + ******************************************************************************/ +#define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define VERSAL_NET_UART0_BASE U(0xF1920000) +#define VERSAL_NET_UART_BAUDRATE 115200 + +#define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE + +#define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE +#define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK +#define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE + +/******************************************************************************* + * IPI registers and bitfields + ******************************************************************************/ +#define IPI0_REG_BASE (0xEB330000U) +#define IPI0_TRIG_BIT (1 << 2) +#define PMC_IPI_TRIG_BIT (1 << 1) +#define IPI1_REG_BASE (0xEB340000U) +#define IPI1_TRIG_BIT (1 << 3) +#define IPI2_REG_BASE (0xEB350000U) +#define IPI2_TRIG_BIT (1 << 4) +#define IPI3_REG_BASE (0xEB360000U) +#define IPI3_TRIG_BIT (1 << 5) +#define IPI4_REG_BASE (0xEB370000U) +#define IPI4_TRIG_BIT (1 << 6) +#define IPI5_REG_BASE (0xEB380000U) +#define IPI5_TRIG_BIT (1 << 7) + +/* Processor core device IDs */ +#define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) +#define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) +#define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) +#define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) + +#define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) +#define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) +#define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) +#define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) + +#define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) +#define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) +#define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) +#define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) + +#define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) +#define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) +#define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) +#define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) + +#endif /* VERSAL_NET_DEF_H */ |