diff options
Diffstat (limited to 'plat/xilinx/versal_net')
| -rw-r--r-- | plat/xilinx/versal_net/aarch64/versal_net_common.c | 127 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/aarch64/versal_net_helpers.S | 110 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/bl31_versal_net_setup.c | 223 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_ipi.h | 58 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_macros.S | 118 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_pm_common.h | 25 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/plat_private.h | 49 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/platform_def.h | 114 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/include/versal_net_def.h | 171 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/plat_psci.c | 220 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/plat_psci_pm.c | 264 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/plat_topology.c | 63 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/platform.mk | 102 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/pm_service/pm_client.c | 240 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/sip_svc_setup.c | 101 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/versal_net_gicv3.c | 222 | ||||
| -rw-r--r-- | plat/xilinx/versal_net/versal_net_ipi.c | 85 |
17 files changed, 2292 insertions, 0 deletions
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c new file mode 100644 index 0000000..c78b5d0 --- /dev/null +++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <drivers/generic_delay_timer.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> +#include <plat_ipi.h> + +#include <plat_private.h> +#include <versal_net_def.h> + +uint32_t platform_id, platform_version; + +/* + * Table of regions to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * configure_mmu_elx() will give the available subset of that, + */ +const mmap_region_t plat_versal_net_mmap[] = { + MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; + +const mmap_region_t *plat_versal_net_get_mmap(void) +{ + return plat_versal_net_mmap; +} + +/* For saving cpu clock for certain platform */ +uint32_t cpu_clock; + +char *board_name_decode(void) +{ + switch (platform_id) { + case VERSAL_NET_SPP: + return "IPP"; + case VERSAL_NET_EMU: + return "EMU"; + case VERSAL_NET_SILICON: + return "Silicon"; + case VERSAL_NET_QEMU: + return "QEMU"; + default: + return "Unknown"; + } +} + +void board_detection(void) +{ + uint32_t version; + + version = mmio_read_32(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + if (platform_id == VERSAL_NET_QEMU_COSIM) { + platform_id = VERSAL_NET_QEMU; + } + + if ((platform_id == VERSAL_NET_SPP) || + (platform_id == VERSAL_NET_EMU) || + (platform_id == VERSAL_NET_QEMU)) { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9U; + } + + /* Make sure that console is setup to see this message */ + VERBOSE("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10U, platform_version % 10U); +} + +void versal_net_config_setup(void) +{ + uint32_t val; + uintptr_t crl_base, iou_scntrs_base, psx_base; + + crl_base = VERSAL_NET_CRL; + iou_scntrs_base = VERSAL_NET_IOU_SCNTRS; + psx_base = PSX_CRF; + + /* Reset for system timestamp generator in FPX */ + mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); + + /* Global timer init - Program time stamp reference clk */ + val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET); + val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val); + + /* Clear reset of timestamp reg */ + mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0); + + /* Program freq register in System counter and enable system counter. */ + mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET, + cpu_clock); + mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, + VERSAL_NET_IOU_SCNTRS_CONTROL_EN); + + generic_delay_timer_init(); + +#if (TFA_NO_PM == 0) + /* Configure IPI data for versal_net */ + versal_net_ipi_config_table_init(); +#endif +} + +uint32_t plat_get_syscnt_freq2(void) +{ + return cpu_clock; +} diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S new file mode 100644 index 0000000..48082a6 --- /dev/null +++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <drivers/arm/gicv3.h> +#include <platform_def.h> + + .globl plat_secondary_cold_boot_setup + .globl plat_is_my_cpu_primary + .globl platform_mem_init + .globl plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * TODO: Should we read the PSYS register to make sure + * that the request has gone through. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + mrs x0, mpidr_el1 + + /* + * There is no sane reason to come out of this wfi. This + * cpu will be powered on and reset by the cpu_on pm api + */ + dsb sy + bl plat_panic_handler +endfunc plat_secondary_cold_boot_setup + +func plat_is_my_cpu_primary + mov x9, x30 + bl plat_my_core_pos + cmp x0, #VERSAL_NET_PRIMARY_CPU + cset x0, eq + ret x9 +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_core_pos_by_mpidr() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_core_pos_by_mpidr +endfunc plat_my_core_pos + + /* --------------------------------------------------------------------- + * We don't need to carry out any memory initialization on Versal NET + * platform. The Secure RAM is accessible straight away. + * --------------------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init +/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE + mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ + mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE + b console_pl011_core_init */ +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE + b console_pl011_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * void plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : void. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE + b console_pl011_core_flush +endfunc plat_crash_console_flush diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c new file mode 100644 index 0000000..c9942d6 --- /dev/null +++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> + +#include <bl31/bl31.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/fdt_fixup.h> +#include <common/fdt_wrappers.h> +#include <drivers/arm/pl011.h> +#include <drivers/console.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <libfdt.h> +#include <plat/common/platform.h> +#include <plat_arm.h> + +#include <plat_private.h> +#include <plat_startup.h> +#include <versal_net_def.h> + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; +static console_t versal_net_runtime_console; + +/* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + */ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + assert(sec_state_is_valid(type)); + + if (type == NON_SECURE) { + return &bl33_image_ep_info; + } + + return &bl32_image_ep_info; +} + +/* + * Set the build time defaults,if we can't find any config data. + */ +static inline void bl31_set_default_config(void) +{ + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + +/* + * Perform any BL31 specific platform actions. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + */ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + uint32_t uart_clock; + int32_t rc; + + board_detection(); + + switch (platform_id) { + case VERSAL_NET_SPP: + cpu_clock = 1000000; + uart_clock = 1000000; + break; + case VERSAL_NET_EMU: + cpu_clock = 3660000; + uart_clock = 25000000; + break; + case VERSAL_NET_QEMU: + /* Random values now */ + cpu_clock = 100000000; + uart_clock = 25000000; + break; + case VERSAL_NET_SILICON: + cpu_clock = 100000000; + uart_clock = 100000000; + break; + default: + panic(); + } + + /* Initialize the console to provide early debug support */ + rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock, + VERSAL_NET_UART_BAUDRATE, + &versal_net_runtime_console); + if (rc == 0) { + panic(); + } + + console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME); + + NOTICE("TF-A running on Xilinx %s %d.%d\n", board_name_decode(), + platform_version / 10U, platform_version % 10U); + + /* Initialize the platform config for future decision making */ + versal_net_config_setup(); + /* There are no parameters from BL2 if BL31 is a reset vector */ + assert(arg0 == 0U); + assert(arg1 == 0U); + + /* + * Do initial security configuration to allow DRAM/device access. On + * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but + * other platforms might have more programmable security devices + * present. + */ + + /* Populate common information for BL32 and BL33 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + + bl31_set_default_config(); + + NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); + NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); +} + +static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; + +int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) +{ + static uint32_t index; + uint32_t i; + + /* Validate 'handler' and 'id' parameters */ + if (handler == NULL || index >= MAX_INTR_EL3) { + return -EINVAL; + } + + /* Check if a handler has already been registered */ + for (i = 0; i < index; i++) { + if (id == type_el3_interrupt_table[i].id) { + return -EALREADY; + } + } + + type_el3_interrupt_table[index].id = id; + type_el3_interrupt_table[index].handler = handler; + + index++; + + return 0; +} + +static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, + void *handle, void *cookie) +{ + uint32_t intr_id; + uint32_t i; + interrupt_type_handler_t handler = NULL; + + intr_id = plat_ic_get_pending_interrupt_id(); + + for (i = 0; i < MAX_INTR_EL3; i++) { + if (intr_id == type_el3_interrupt_table[i].id) { + handler = type_el3_interrupt_table[i].handler; + } + } + + if (handler != NULL) { + handler(intr_id, flags, handle, cookie); + } + + return 0; +} + +void bl31_platform_setup(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + plat_versal_net_gic_driver_init(); + plat_versal_net_gic_init(); +} + +void bl31_plat_runtime_setup(void) +{ + uint64_t flags = 0; + int32_t rc; + + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_EL3, + rdo_el3_interrupt_handler, flags); + if (rc != 0) { + panic(); + } +} + +/* + * Perform the very early platform specific architectural setup here. + */ +void bl31_plat_arch_setup(void) +{ + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, + MT_RO_DATA | MT_SECURE), + {0} + }; + + setup_page_tables(bl_regions, plat_versal_net_get_mmap()); + enable_mmu(0); +} diff --git a/plat/xilinx/versal_net/include/plat_ipi.h b/plat/xilinx/versal_net/include/plat_ipi.h new file mode 100644 index 0000000..5255f8f --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_ipi.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Versal IPI management enums and defines */ + +#ifndef PLAT_IPI_H +#define PLAT_IPI_H + +#include <stdint.h> + +#include <ipi.h> + +/********************************************************************* + * IPI agent IDs macros + ********************************************************************/ +#define IPI_ID_PMC 1U +#define IPI_ID_APU 2U +#define IPI_ID_RPU0 3U +#define IPI_ID_RPU1 4U +#define IPI_ID_3 5U +#define IPI_ID_4 6U +#define IPI_ID_5 7U +#define IPI_ID_MAX 8U + +/********************************************************************* + * IPI message buffers + ********************************************************************/ +#define IPI_BUFFER_BASEADDR (0xEB3F0000U) + +#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U) + +#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U +#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U + +#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE +#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE + +#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET +#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET + +#define IPI_BUFFER_MAX_WORDS 8 + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +/********************************************************************* + * Platform specific IPI API declarations + ********************************************************************/ + +/* Configure IPI table for versal_net */ +void versal_net_ipi_config_table_init(void); + +#endif /* PLAT_IPI_H */ diff --git a/plat/xilinx/versal_net/include/plat_macros.S b/plat/xilinx/versal_net/include/plat_macros.S new file mode 100644 index 0000000..fb108b6 --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_macros.S @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv2.h> +#include <drivers/arm/gicv3.h> + +#include "../include/platform_def.h" + +.section .rodata.gic_reg_name, "aS" +/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" + +/* Applicable only to GICv3 with SRE enabled */ +icc_regs: + .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" + +/* Registers common to both GICv2 and GICv3 */ +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31 on Versal NET platform. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro versal_net_print_gic_regs + /* Check for GICv3 system register access */ + mrs x7, id_aa64pfr0_el1 + ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x7, #1 + b.ne print_gicv2 + + /* Check for SRE enable */ + mrs x8, ICC_SRE_EL3 + tst x8, #ICC_SRE_SRE_BIT + b.eq print_gicv2 + + /* Load the icc reg list to x6 */ + adr x6, icc_regs + /* Load the icc regs to gp regs used by str_in_crash_buf_print */ + mrs x8, ICC_HPPIR0_EL1 + mrs x9, ICC_HPPIR1_EL1 + mrs x10, ICC_CTLR_EL3 + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + b print_gic_common + +print_gicv2: + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + +print_gic_common: + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* + * Empty for now to handle more platforms variant. + * Uncomment it when versions are stable + */ + /* + mov_imm x17, PLAT_VERSAL_NET_GICD_BASE + mov_imm x16, PLAT_VERSAL_NET_GICR_BASE + versal_net_print_gic_regs + */ + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/xilinx/versal_net/include/plat_pm_common.h b/plat/xilinx/versal_net/include/plat_pm_common.h new file mode 100644 index 0000000..ad7b40f --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_pm_common.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains platform specific definitions of commonly used macros data types + * for PU Power Management. This file should be common for all PU's. + */ + +#ifndef PLAT_PM_COMMON_H +#define PLAT_PM_COMMON_H + +#include <stdint.h> + +#include <common/debug.h> + +#include "pm_defs.h" + +#define NON_SECURE_FLAG 1U +#define SECURE_FLAG 0U + +#endif /* PLAT_PM_COMMON_H */ diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h new file mode 100644 index 0000000..6a3bc19 --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_private.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +#include <bl31/interrupt_mgmt.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +typedef struct versal_intr_info_type_el3 { + uint32_t id; + interrupt_type_handler_t handler; +} versal_intr_info_type_el3_t; + +void versal_net_config_setup(void); + +const mmap_region_t *plat_versal_net_get_mmap(void); + +void plat_versal_net_gic_driver_init(void); +void plat_versal_net_gic_init(void); +void plat_versal_net_gic_cpuif_enable(void); +void plat_versal_net_gic_cpuif_disable(void); +void plat_versal_net_gic_pcpu_init(void); +void plat_versal_net_gic_save(void); +void plat_versal_net_gic_resume(void); +void plat_versal_net_gic_redistif_on(void); +void plat_versal_net_gic_redistif_off(void); + +extern uint32_t cpu_clock, platform_id, platform_version; +void board_detection(void); +char *board_name_decode(void); +uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, uint64_t flags); +int32_t sip_svc_setup_init(void); +/* + * Register handler to specific GIC entrance + * for INTR_TYPE_EL3 type of interrupt + */ +int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); + +#define PM_GET_CHIPID (24U) +#define IOCTL_OSPI_MUX_SELECT (21U) + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h new file mode 100644 index 0000000..696771f --- /dev/null +++ b/plat/xilinx/versal_net/include/platform_def.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include "versal_net_def.h" + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE U(0x440) + +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ + +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) + +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#ifndef VERSAL_NET_ATF_MEM_BASE +# define BL31_BASE U(0xBBF00000) +# define BL31_LIMIT U(0xBBFFFFFF) +#else +# define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE) +# define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE - 1) +# ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE +# define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \ + VERSAL_NET_ATF_MEM_PROGBITS_SIZE - 1) +# endif +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef VERSAL_NET_BL32_MEM_BASE +# define BL32_BASE U(0x60000000) +# define BL32_LIMIT U(0x7FFFFFFF) +#else +# define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE) +# define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE - 1) +#endif + +/******************************************************************************* + * BL33 specific defines. + ******************************************************************************/ +#ifndef PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) +#else +# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) +#endif + +/******************************************************************************* + * TSP specific defines. + ******************************************************************************/ +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1U) + +/* ID of the secure physical generic timer interrupt used by the TSP */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_DDR_LOWMEM_MAX U(0x80000000) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) +#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#define MAX_MMAP_REGIONS U(10) +#else +#define MAX_MMAP_REGIONS U(9) +#endif + +#define MAX_XLAT_TABLES U(8) + +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define PLAT_VERSAL_NET_GICD_BASE U(0xE2000000) +#define PLAT_VERSAL_NET_GICR_BASE U(0xE2060000) + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_VERSAL_IPI_IRQ 62 + +#define PLAT_VERSAL_NET_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h new file mode 100644 index 0000000..8cb5bf3 --- /dev/null +++ b/plat/xilinx/versal_net/include/versal_net_def.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VERSAL_NET_DEF_H +#define VERSAL_NET_DEF_H + +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +#define MAX_INTR_EL3 2 +/* This part is taken from U-Boot project under GPL that's why dual license above */ +#define __bf_shf(x) (__builtin_ffsll(x) - 1U) +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +/* List all consoles */ +#define VERSAL_NET_CONSOLE_ID_pl011 U(1) +#define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) +#define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) + +#define VERSAL_NET_CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) + +/* List all platforms */ +#define VERSAL_NET_SILICON U(0) +#define VERSAL_NET_SPP U(1) +#define VERSAL_NET_EMU U(2) +#define VERSAL_NET_QEMU U(3) +#define VERSAL_NET_QEMU_COSIM U(7) + +/* For platform detection */ +#define PMC_TAP U(0xF11A0000) +#define PMC_TAP_VERSION (PMC_TAP + 0x4U) +# define PLATFORM_MASK GENMASK(27U, 24U) +# define PLATFORM_VERSION_MASK GENMASK(31U, 28U) + +/* Global timer reset */ +#define PSX_CRF U(0xEC200000) +#define ACPU0_CLK_CTRL U(0x10C) +#define ACPU_CLK_CTRL_CLKACT BIT(25) + +#define RST_APU0_OFFSET U(0x300) +#define RST_APU_COLD_RESET BIT(0) +#define RST_APU_WARN_RESET BIT(4) +#define RST_APU_CLUSTER_COLD_RESET BIT(8) +#define RST_APU_CLUSTER_WARM_RESET BIT(9) + +#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) + +#define APU_PCLI U(0xECB10000) +#define APU_PCLI_CPU_STEP U(0x30) +#define APU_PCLI_CLUSTER_CPU_STEP (4U * APU_PCLI_CPU_STEP) +#define APU_PCLI_CLUSTER_OFFSET U(0x8000) +#define APU_PCLI_CLUSTER_STEP U(0x1000) +#define PCLI_PREQ_OFFSET U(0x4) +#define PREQ_CHANGE_REQUEST BIT(0) +#define PCLI_PSTATE_OFFSET U(0x8) +#define PCLI_PSTATE_VAL_SET U(0x48) +#define PCLI_PSTATE_VAL_CLEAR U(0x38) + +/* Firmware Image Package */ +#define VERSAL_NET_PRIMARY_CPU U(0) + +#define CORE_0_IEN_POWER_OFFSET (0x00000018U) +#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ + (0x30 * cpu_id))) +#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) +#define CORE_0_IDS_POWER_OFFSET (0x0000001CU) +#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ + (0x30 * cpu_id))) +#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) +#define CORE_PWRDN_EN_BIT_MASK (0x1U) + +/******************************************************************************* + * memory map related constants + ******************************************************************************/ +/* IPP 1.2/SPP 0.9 mapping */ +#define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ +#define DEVICE0_SIZE U(0x08000000) +#define DEVICE1_BASE U(0xE2000000) /* gic */ +#define DEVICE1_SIZE U(0x00800000) +#define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ +#define DEVICE2_SIZE U(0x01000000) +#define CRF_BASE U(0xFD1A0000) +#define CRF_SIZE U(0x00600000) +#define IPI_BASE U(0xEB300000) +#define IPI_SIZE U(0x00100000) + +/* CRL */ +#define VERSAL_NET_CRL U(0xEB5E0000) +#define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) +#define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) + +#define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) + +/* IOU SCNTRS */ +#define VERSAL_NET_IOU_SCNTRS U(0xEC920000) +#define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) +#define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) + +#define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1) + +#define APU_CLUSTER0 U(0xECC00000) +#define APU_RVBAR_L_0 U(0x40) +#define APU_RVBAR_H_0 U(0x44) +#define APU_CLUSTER_STEP U(0x100000) + +#define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) + +/******************************************************************************* + * IRQ constants + ******************************************************************************/ +#define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define VERSAL_NET_UART0_BASE U(0xF1920000) +#define VERSAL_NET_UART_BAUDRATE 115200 + +#define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE + +#define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE +#define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK +#define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE + +/******************************************************************************* + * IPI registers and bitfields + ******************************************************************************/ +#define IPI0_REG_BASE (0xEB330000U) +#define IPI0_TRIG_BIT (1 << 2) +#define PMC_IPI_TRIG_BIT (1 << 1) +#define IPI1_REG_BASE (0xEB340000U) +#define IPI1_TRIG_BIT (1 << 3) +#define IPI2_REG_BASE (0xEB350000U) +#define IPI2_TRIG_BIT (1 << 4) +#define IPI3_REG_BASE (0xEB360000U) +#define IPI3_TRIG_BIT (1 << 5) +#define IPI4_REG_BASE (0xEB370000U) +#define IPI4_TRIG_BIT (1 << 6) +#define IPI5_REG_BASE (0xEB380000U) +#define IPI5_TRIG_BIT (1 << 7) + +/* Processor core device IDs */ +#define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) +#define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) +#define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) +#define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) + +#define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) +#define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) +#define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) +#define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) + +#define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) +#define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) +#define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) +#define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) + +#define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) +#define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) +#define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) +#define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) + +#endif /* VERSAL_NET_DEF_H */ diff --git a/plat/xilinx/versal_net/plat_psci.c b/plat/xilinx/versal_net/plat_psci.c new file mode 100644 index 0000000..c5833a9 --- /dev/null +++ b/plat/xilinx/versal_net/plat_psci.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> +#include <plat_arm.h> + +#include <plat_private.h> + +#define PM_RET_ERROR_NOFEATURE U(19) + +#define PM_IOCTL 34U + +static uintptr_t versal_net_sec_entry; + +static void zynqmp_cpu_standby(plat_local_state_t cpu_state) +{ + dsb(); + wfi(); +} + +static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) +{ + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); + uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER; + uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER; + uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0; + uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + (cluster * 0x4); + + VERBOSE("%s: mpidr: 0x%lx, cpuid: %x, cpu: %x, cluster: %x\n", + __func__, mpidr, cpu_id, cpu, cluster); + + if (cpu_id == -1) { + return PSCI_E_INTERN_FAIL; + } + + if (platform_id == VERSAL_NET_SPP && cluster > 1) { + panic(); + } + + if (cluster > 3) { + panic(); + } + + apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + (cluster * APU_PCLI_CLUSTER_STEP); + apu_cluster_base = APU_CLUSTER0 + (cluster * APU_CLUSTER_STEP); + + /* Enable clock */ + mmio_setbits_32(PSX_CRF + ACPU0_CLK_CTRL + (cluster * 0x4), ACPU_CLK_CTRL_CLKACT); + + /* Enable cluster states */ + mmio_setbits_32(apu_pcli_cluster + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_SET); + mmio_setbits_32(apu_pcli_cluster + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); + + /* assert core reset */ + mmio_setbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); + + /* program RVBAR */ + mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3), + (uint32_t)versal_net_sec_entry); + mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3), + versal_net_sec_entry >> 32); + + /* de-assert core reset */ + mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); + + /* clear cluster resets */ + mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_WARM_RESET); + mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_COLD_RESET); + + apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) + + (APU_PCLI_CLUSTER_CPU_STEP * cluster); + + mmio_write_32(apu_pcli_base + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_CLEAR); + mmio_write_32(apu_pcli_base + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); + + return PSCI_E_SUCCESS; +} + +static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state) +{ +} + +static void __dead2 zynqmp_nopmu_system_reset(void) +{ + while (1) + wfi(); +} + +static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint) +{ + return PSCI_E_SUCCESS; +} + +static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) +{ +} + +static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + plat_versal_net_gic_pcpu_init(); + plat_versal_net_gic_cpuif_enable(); +} + +static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ +} + +static void __dead2 zynqmp_system_off(void) +{ + while (1) + wfi(); +} + +static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) +{ + return PSCI_E_SUCCESS; +} + +static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; +} + +static const struct plat_psci_ops versal_net_nopmc_psci_ops = { + .cpu_standby = zynqmp_cpu_standby, + .pwr_domain_on = zynqmp_nopmu_pwr_domain_on, + .pwr_domain_off = zynqmp_nopmu_pwr_domain_off, + .system_reset = zynqmp_nopmu_system_reset, + .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, + .pwr_domain_suspend = zynqmp_pwr_domain_suspend, + .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, + .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, + .system_off = zynqmp_system_off, + .validate_power_state = zynqmp_validate_power_state, + .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops. + ******************************************************************************/ +int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **psci_ops) +{ + versal_net_sec_entry = sec_entrypoint; + + VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); + + *psci_ops = &versal_net_nopmc_psci_ops; + + return 0; +} + +int sip_svc_setup_init(void) +{ + return 0; +} + +static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id, + uint32_t arg1, uint32_t arg2) +{ + VERBOSE("%s: ioctl_id: %x, arg1: %x\n", __func__, ioctl_id, arg1); + if (ioctl_id == IOCTL_OSPI_MUX_SELECT) { + mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1); + return 0; + } + return PM_RET_ERROR_NOFEATURE; +} + +static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, uint64_t flags) +{ + int32_t ret; + uint32_t arg[4], api_id; + + arg[0] = (uint32_t)x1; + arg[1] = (uint32_t)(x1 >> 32); + arg[2] = (uint32_t)x2; + arg[3] = (uint32_t)(x2 >> 32); + + api_id = smc_fid & FUNCID_NUM_MASK; + VERBOSE("%s: smc_fid: %x, api_id=0x%x\n", __func__, smc_fid, api_id); + + switch (api_id) { + case PM_IOCTL: + { + ret = no_pm_ioctl(arg[0], arg[1], arg[2], arg[3]); + SMC_RET1(handle, (uint64_t)ret); + } + case PM_GET_CHIPID: + { + uint32_t idcode, version; + + idcode = mmio_read_32(PMC_TAP); + version = mmio_read_32(PMC_TAP_VERSION); + SMC_RET2(handle, ((uint64_t)idcode << 32), version); + } + default: + WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + void *cookie, void *handle, uint64_t flags) +{ + return no_pm_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); +} diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c new file mode 100644 index 0000000..8beaa9a --- /dev/null +++ b/plat/xilinx/versal_net/plat_psci_pm.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <common/debug.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> +#include <plat_arm.h> + +#include <plat_private.h> +#include "pm_api_sys.h" +#include "pm_client.h" +#include <pm_common.h> +#include "pm_svc_main.h" +#include "versal_net_def.h" + +static uintptr_t versal_net_sec_entry; + +static int32_t versal_net_pwr_domain_on(u_register_t mpidr) +{ + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); + const struct pm_proc *proc; + + VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n", + __func__, mpidr, cpu_id); + + if (cpu_id == -1) { + return PSCI_E_INTERN_FAIL; + } + + proc = pm_get_proc(cpu_id); + if (!proc) { + return PSCI_E_INTERN_FAIL; + } + + pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U, + versal_net_sec_entry >> 32, 0, 0); + + /* Clear power down request */ + pm_client_wakeup(proc); + + return PSCI_E_SUCCESS; +} + +/** + * versal_net_pwr_domain_off() - This function performs actions to turn off core + * + * @param target_state Targeted state + */ +static void versal_net_pwr_domain_off(const psci_power_state_t *target_state) +{ + uint32_t cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + } + + /* Prevent interrupts from spuriously waking up this cpu */ + plat_versal_net_gic_cpuif_disable(); + + /* + * Send request to PMC to power down the appropriate APU CPU + * core. + * According to PSCI specification, CPU_off function does not + * have resume address and CPU core can only be woken up + * invoking CPU_on function, during which resume address will + * be set. + */ + pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, + SECURE_FLAG); +} + +/** + * versal_net_system_reset() - This function sends the reset request + * to firmware for the system to reset. This function does not return. + */ +static void __dead2 versal_net_system_reset(void) +{ + /* Send the system reset request to the PMC */ + pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, + pm_get_shutdown_scope(), SECURE_FLAG); + + while (1) { + wfi(); + } +} + +/** + * versal_net_pwr_domain_suspend() - This function sends request to PMC to suspend + * core. + * + * @param target_state Targeted state + */ +static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + uint32_t state; + uint32_t cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + } + + plat_versal_net_gic_cpuif_disable(); + + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + plat_versal_net_gic_save(); + } + + state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? + PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; + + /* Send request to PMC to suspend this core */ + pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry, + SECURE_FLAG); + + /* TODO: disable coherency */ +} + +static void versal_net_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + (void)target_state; + + /* Enable the gic cpu interface */ + plat_versal_net_gic_pcpu_init(); + + /* Program the gic per-cpu distributor or re-distributor interface */ + plat_versal_net_gic_cpuif_enable(); +} + +/** + * versal_net_pwr_domain_suspend_finish() - This function performs actions to finish + * suspend procedure. + * + * @param target_state Targeted state + */ +static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + uint32_t cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Clear the APU power control register for this cpu */ + pm_client_wakeup(proc); + + /* TODO: enable coherency */ + + /* APU was turned off, so restore GIC context */ + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + plat_versal_net_gic_resume(); + } + + plat_versal_net_gic_cpuif_enable(); +} + +/** + * versal_net_system_off() - This function sends the system off request + * to firmware. This function does not return. + */ +static void __dead2 versal_net_system_off(void) +{ + /* Send the power down request to the PMC */ + pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, + pm_get_shutdown_scope(), SECURE_FLAG); + + while (1) { + wfi(); + } +} + +/** + * versal_net_validate_power_state() - This function ensures that the power state + * parameter in request is valid. + * + * @param power_state Power state of core + * @param req_state Requested state + * + * @return Returns status, either PSCI_E_SUCCESS or reason + */ +static int32_t versal_net_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); + + int32_t pstate = psci_get_pstate_type(power_state); + + assert(req_state); + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; + } else { + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; + } + + /* We expect the 'state id' to be zero */ + if (psci_get_pstate_id(power_state)) { + return PSCI_E_INVALID_PARAMS; + } + + return PSCI_E_SUCCESS; +} + +/** + * versal_net_get_sys_suspend_power_state() - Get power state for system suspend + * + * @param req_state Requested state + */ +static void versal_net_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; +} + +static const struct plat_psci_ops versal_net_nopmc_psci_ops = { + .pwr_domain_on = versal_net_pwr_domain_on, + .pwr_domain_off = versal_net_pwr_domain_off, + .pwr_domain_on_finish = versal_net_pwr_domain_on_finish, + .pwr_domain_suspend = versal_net_pwr_domain_suspend, + .pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish, + .system_off = versal_net_system_off, + .system_reset = versal_net_system_reset, + .validate_power_state = versal_net_validate_power_state, + .get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops. + ******************************************************************************/ +int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **psci_ops) +{ + versal_net_sec_entry = sec_entrypoint; + + VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); + + *psci_ops = &versal_net_nopmc_psci_ops; + + return 0; +} + +int32_t sip_svc_setup_init(void) +{ + return pm_setup(); +} + +uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + void *cookie, void *handle, uint64_t flags) +{ + return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); +} diff --git a/plat/xilinx/versal_net/plat_topology.c b/plat/xilinx/versal_net/plat_topology.c new file mode 100644 index 0000000..7f985b0 --- /dev/null +++ b/plat/xilinx/versal_net/plat_topology.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <plat/common/platform.h> + +#include <plat_private.h> +#include <platform_def.h> + +static const uint8_t plat_power_domain_tree_desc[] = { + /* Number of root nodes */ + 1, + /* Number of clusters */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + /* Number of children for the second cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + /* Number of children for the third cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + /* Number of children for the fourth cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, +}; + +const uint8_t *plat_get_power_domain_tree_desc(void) +{ + return plat_power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int32_t plat_core_pos_by_mpidr(u_register_t mpidr) +{ + uint32_t cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + cluster_id = MPIDR_AFFLVL2_VAL(mpidr); + cpu_id = MPIDR_AFFLVL1_VAL(mpidr); + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -3; + } + + /* + * Validate cpu_id by checking whether it represents a CPU in + * one of the two clusters present on the platform. + */ + if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { + return -1; + } + + return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER)); +} diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk new file mode 100644 index 0000000..b3d56bc --- /dev/null +++ b/plat/xilinx/versal_net/platform.mk @@ -0,0 +1,102 @@ +# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. +# Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +PLAT_PATH := plat/xilinx/versal_net + +# A78 Erratum for SoC +ERRATA_A78_AE_1941500 := 1 +ERRATA_A78_AE_1951502 := 1 +ERRATA_A78_AE_2376748 := 1 +ERRATA_A78_AE_2395408 := 1 + +override PROGRAMMABLE_RESET_ADDRESS := 1 +PSCI_EXTENDED_STATE_ID := 1 +SEPARATE_CODE_AND_RODATA := 1 +override RESET_TO_BL31 := 1 +PL011_GENERIC_UART := 1 +GIC_ENABLE_V4_EXTN := 0 +GICV3_SUPPORT_GIC600 := 1 +TFA_NO_PM := 0 + +override CTX_INCLUDE_AARCH32_REGS := 0 + +ifdef TFA_NO_PM + $(eval $(call add_define,TFA_NO_PM)) +endif + +ifdef VERSAL_NET_ATF_MEM_BASE + $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE)) + + ifndef VERSAL_NET_ATF_MEM_SIZE + $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE") + endif + $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE)) + + ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE + $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE)) + endif +endif + +ifdef VERSAL_NET_BL32_MEM_BASE + $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE)) + + ifndef VERSAL_NET_BL32_MEM_SIZE + $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE") + endif + $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE)) +endif + +USE_COHERENT_MEM := 0 +HW_ASSISTED_COHERENCY := 1 + +VERSAL_NET_CONSOLE ?= pl011 +$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE})) + +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -Iplat/xilinx/common/include/ \ + -Iplat/xilinx/common/ipi_mailbox_service/ \ + -I${PLAT_PATH}/include/ \ + -Iplat/xilinx/versal/pm_service/ + +# Include GICv3 driver files +include drivers/arm/gic/v3/gicv3.mk +include lib/xlat_tables_v2/xlat_tables.mk +include lib/libfdt/libfdt.mk + +PLAT_BL_COMMON_SOURCES := \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + ${GICV3_SOURCES} \ + drivers/arm/pl011/aarch64/pl011_console.S \ + plat/arm/common/arm_common.c \ + plat/common/plat_gicv3.c \ + ${PLAT_PATH}/aarch64/versal_net_helpers.S \ + ${PLAT_PATH}/aarch64/versal_net_common.c + +BL31_SOURCES += drivers/arm/cci/cci.c \ + lib/cpus/aarch64/cortex_a78_ae.S \ + lib/cpus/aarch64/cortex_a78.S \ + plat/common/plat_psci_common.c +ifeq ($(TFA_NO_PM), 0) +BL31_SOURCES += plat/xilinx/versal/pm_service/pm_api_sys.c \ + plat/xilinx/common/pm_service/pm_ipi.c \ + ${PLAT_PATH}/plat_psci_pm.c \ + plat/xilinx/versal/pm_service/pm_svc_main.c \ + ${PLAT_PATH}/pm_service/pm_client.c \ + ${PLAT_PATH}/versal_net_ipi.c +else +BL31_SOURCES += ${PLAT_PATH}/plat_psci.c +endif +BL31_SOURCES += plat/xilinx/common/plat_startup.c \ + plat/xilinx/common/ipi.c \ + plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ + ${PLAT_PATH}/bl31_versal_net_setup.c \ + ${PLAT_PATH}/plat_topology.c \ + common/fdt_fixup.c \ + ${LIBFDT_SRCS} \ + ${PLAT_PATH}/sip_svc_setup.c \ + ${PLAT_PATH}/versal_net_gicv3.c \ + ${XLAT_TABLES_LIB_SRCS} diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c new file mode 100644 index 0000000..6487324 --- /dev/null +++ b/plat/xilinx/versal_net/pm_service/pm_client.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * APU specific definition of processors in the subsystem as well as functions + * for getting information about and changing state of the APU. + */ + +#include <assert.h> + +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv3.h> +#include <lib/bakery_lock.h> +#include <lib/mmio.h> +#include <lib/mmio.h> +#include <lib/utils.h> +#include <plat/common/platform.h> + +#include <plat_ipi.h> +#include <platform_def.h> +#include "pm_api_sys.h" +#include "pm_client.h" +#include <versal_net_def.h> + +#define UNDEFINED_CPUID (~0) + +DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7) +DEFINE_BAKERY_LOCK(pm_client_secure_lock); + +static const struct pm_ipi apu_ipi = { + .local_ipi_id = IPI_ID_APU, + .remote_ipi_id = IPI_ID_PMC, + .buffer_base = IPI_BUFFER_APU_BASE, +}; + +/* Order in pm_procs_all array must match cpu ids */ +static const struct pm_proc pm_procs_all[] = { + { + .node_id = PM_DEV_CLUSTER0_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER0_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER0_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER0_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + } +}; + +const struct pm_proc *primary_proc = &pm_procs_all[0]; + +/** + * pm_get_proc() - returns pointer to the proc structure + * @param cpuid id of the cpu whose proc struct pointer should be returned + * + * @return pointer to a proc structure if proc is found, otherwise NULL + */ +const struct pm_proc *pm_get_proc(uint32_t cpuid) +{ + if (cpuid < ARRAY_SIZE(pm_procs_all)) { + return &pm_procs_all[cpuid]; + } + + NOTICE("ERROR: cpuid: %d proc NULL\n", cpuid); + return NULL; +} + +/** + * pm_client_suspend() - Client-specific suspend actions + * + * This function should contain any PU-specific actions + * required prior to sending suspend request to PMU + * Actions taken depend on the state system is suspending to. + * + * @param proc processor which need to suspend + * @param state desired suspend state + */ +void pm_client_suspend(const struct pm_proc *proc, uint32_t state) +{ + uint32_t cpu_id = plat_my_core_pos(); + uintptr_t val; + + bakery_lock_get(&pm_client_secure_lock); + + /* TODO: Set wakeup source */ + + val = read_cpu_pwrctrl_val(); + val |= CORE_PWRDN_EN_BIT_MASK; + write_cpu_pwrctrl_val(val); + + isb(); + + mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id), + APU_PCIL_CORE_X_IEN_POWER_MASK); + + bakery_lock_release(&pm_client_secure_lock); +} + +/** + * pm_get_cpuid() - get the local cpu ID for a global node ID + * @param nid node id of the processor + * + * @return the cpu ID (starting from 0) for the subsystem + */ +static uint32_t pm_get_cpuid(uint32_t nid) +{ + for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) { + if (pm_procs_all[i].node_id == nid) { + return i; + } + } + return UNDEFINED_CPUID; +} + +/** + * pm_client_wakeup() - Client-specific wakeup actions + * + * This function should contain any PU-specific actions + * required for waking up another APU core + * + * @param proc Processor which need to wakeup + */ +void pm_client_wakeup(const struct pm_proc *proc) +{ + uint32_t cpuid = pm_get_cpuid(proc->node_id); + + if (cpuid == UNDEFINED_CPUID) { + return; + } + + bakery_lock_get(&pm_client_secure_lock); + + /* TODO: clear powerdown bit for affected cpu */ + + bakery_lock_release(&pm_client_secure_lock); +} + +/** + * pm_client_abort_suspend() - Client-specific abort-suspend actions + * + * This function should contain any PU-specific actions + * required for aborting a prior suspend request + */ +void pm_client_abort_suspend(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + uintptr_t val; + + /* Enable interrupts at processor level (for current cpu) */ + gicv3_cpuif_enable(plat_my_core_pos()); + + bakery_lock_get(&pm_client_secure_lock); + + /* Clear powerdown request */ + val = read_cpu_pwrctrl_val(); + val &= ~CORE_PWRDN_EN_BIT_MASK; + write_cpu_pwrctrl_val(val); + + isb(); + + /* Disabled power down interrupt */ + mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id), + APU_PCIL_CORE_X_IDS_POWER_MASK); + + bakery_lock_release(&pm_client_secure_lock); +} diff --git a/plat/xilinx/versal_net/sip_svc_setup.c b/plat/xilinx/versal_net/sip_svc_setup.c new file mode 100644 index 0000000..0e3940f --- /dev/null +++ b/plat/xilinx/versal_net/sip_svc_setup.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Top level SMC handler for SiP calls. Dispatch PM calls to PM SMC handler. */ + +#include <errno.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <tools_share/uuid.h> + +#include "ipi_mailbox_svc.h" +#include "plat_private.h" +#include "pm_svc_main.h" + +/* SMC function IDs for SiP Service queries */ +#define VERSAL_NET_SIP_SVC_CALL_COUNT (0x8200ff00U) +#define VERSAL_NET_SIP_SVC_UID (0x8200ff01U) +#define VERSAL_NET_SIP_SVC_VERSION (0x8200ff03U) + +/* SiP Service Calls version numbers */ +#define SIP_SVC_VERSION_MAJOR (0U) +#define SIP_SVC_VERSION_MINOR (1U) + +/* These macros are used to identify PM calls from the SMC function ID */ +#define PM_FID_MASK 0xf000u +#define PM_FID_VALUE 0u +#define IPI_FID_VALUE 0x1000u +#define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE) +#define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE) + +/* SiP Service UUID */ +DEFINE_SVC_UUID2(versal_net_sip_uuid, + 0x80d4c25a, 0xebaf, 0x11eb, 0x94, 0x68, + 0x0b, 0x4e, 0x3b, 0x8f, 0xc3, 0x60); + +/** + * sip_svc_setup() - Setup SiP Service + */ +static int32_t sip_svc_setup(void) +{ + return sip_svc_setup_init(); +} + +/* + * sip_svc_smc_handler() - Top-level SiP Service SMC handler + * + * Handler for all SiP SMC calls. Handles standard SIP requests + * and calls PM SMC handler if the call is for a PM-API function. + */ +static uintptr_t sip_svc_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + /* Let PM SMC handler deal with PM-related requests */ + if (is_pm_fid(smc_fid)) { + return smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); + } + + /* Let IPI SMC handler deal with IPI-related requests if platform */ + if (is_ipi_fid(smc_fid)) { + return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); + } + + /* Let PM SMC handler deal with PM-related requests */ + switch (smc_fid) { + case VERSAL_NET_SIP_SVC_CALL_COUNT: + /* PM functions + default functions */ + SMC_RET1(handle, 2); + + case VERSAL_NET_SIP_SVC_UID: + SMC_UUID_RET(handle, versal_net_sip_uuid); + + case VERSAL_NET_SIP_SVC_VERSION: + SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR); + + default: + WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +/* Register PM Service Calls as runtime service */ +DECLARE_RT_SVC( + sip_svc, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + sip_svc_setup, + sip_svc_smc_handler); diff --git a/plat/xilinx/versal_net/versal_net_gicv3.c b/plat/xilinx/versal_net/versal_net_gicv3.c new file mode 100644 index 0000000..b7ac6ab --- /dev/null +++ b/plat/xilinx/versal_net/versal_net_gicv3.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <common/interrupt_props.h> +#include <drivers/arm/gicv3.h> +#include <lib/utils.h> +#include <plat/common/platform.h> + +#include <plat_private.h> +#include <platform_def.h> + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv3 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_versal_net_gic_driver_init +#pragma weak plat_versal_net_gic_init +#pragma weak plat_versal_net_gic_cpuif_enable +#pragma weak plat_versal_net_gic_cpuif_disable +#pragma weak plat_versal_net_gic_pcpu_init +#pragma weak plat_versal_net_gic_redistif_on +#pragma weak plat_versal_net_gic_redistif_off + +/* The GICv3 driver only needs to be initialized in EL3 */ +static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static const uintptr_t gicr_base_addrs[2] = { + PLAT_VERSAL_NET_GICR_BASE, /* GICR Base address of the primary CPU */ + 0U /* Zero Termination */ +}; + +/* List of zero terminated GICR frame addresses which CPUs will probe */ +static const uintptr_t *gicr_frames; + +static const interrupt_prop_t versal_net_interrupt_props[] = { + PLAT_VERSAL_NET_G1S_IRQ_PROPS(INTR_GROUP1S), + PLAT_VERSAL_NET_G0_IRQ_PROPS(INTR_GROUP0) +}; + +/* + * We save and restore the GICv3 context on system suspend. Allocate the + * data in the designated EL3 Secure carve-out memory. + */ +static gicv3_redist_ctx_t rdist_ctx __section("versal_net_el3_tzc_dram"); +static gicv3_dist_ctx_t dist_ctx __section("versal_net_el3_tzc_dram"); + +/* + * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register + * to core position. + * + * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity + * values read from GICR_TYPER don't have an MT field. To reuse the same + * translation used for CPUs, we insert MT bit read from the PE's MPIDR into + * that read from GICR_TYPER. + * + * Assumptions: + * + * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; + * - No CPUs implemented in the system use affinity level 3. + */ +static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr) +{ + mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); + return plat_core_pos_by_mpidr(mpidr); +} + +static const gicv3_driver_data_t versal_net_gic_data __unused = { + .gicd_base = PLAT_VERSAL_NET_GICD_BASE, + .gicr_base = 0U, + .interrupt_props = versal_net_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = versal_net_gicv3_mpidr_hash +}; + +void __init plat_versal_net_gic_driver_init(void) +{ + /* + * The GICv3 driver is initialized in EL3 and does not need + * to be initialized again in SEL1. This is because the S-EL1 + * can use GIC system registers to manage interrupts and does + * not need GIC interface base addresses to be configured. + */ +#if IMAGE_BL31 + gicv3_driver_init(&versal_net_gic_data); + gicr_frames = gicr_base_addrs; + + if (gicv3_rdistif_probe(gicr_frames[0]) == -1) { + ERROR("No GICR base frame found for Primary CPU\n"); + panic(); + } +#endif +} + +/****************************************************************************** + * Versal NET common helper to initialize the GIC. Only invoked by BL31 + *****************************************************************************/ +void __init plat_versal_net_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to enable the GIC CPU interface + *****************************************************************************/ +void plat_versal_net_gic_cpuif_enable(void) +{ + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to disable the GIC CPU interface + *****************************************************************************/ +void plat_versal_net_gic_cpuif_disable(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to initialize the per-cpu redistributor interface in + * GICv3 + *****************************************************************************/ +void plat_versal_net_gic_pcpu_init(void) +{ + int32_t result; + const uintptr_t *plat_gicr_frames = gicr_frames; + + do { + result = gicv3_rdistif_probe(*plat_gicr_frames); + + /* If the probe is successful, no need to proceed further */ + if (result == 0) { + break; + } + + plat_gicr_frames++; + } while (*plat_gicr_frames != 0U); + + if (result == -1) { + ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); + panic(); + } + + gicv3_rdistif_init(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helpers to power GIC redistributor interface + *****************************************************************************/ +void plat_versal_net_gic_redistif_on(void) +{ + gicv3_rdistif_on(plat_my_core_pos()); +} + +void plat_versal_net_gic_redistif_off(void) +{ + gicv3_rdistif_off(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to save & restore the GICv3 on resume from system + * suspend + *****************************************************************************/ +void plat_versal_net_gic_save(void) +{ + /* + * If an ITS is available, save its context before + * the Redistributor using: + * gicv3_its_save_disable(gits_base, &its_ctx[i]) + * Additionnaly, an implementation-defined sequence may + * be required to save the whole ITS state. + */ + + /* + * Save the GIC Redistributors and ITS contexts before the + * Distributor context. As we only handle SYSTEM SUSPEND API, + * we only need to save the context of the CPU that is issuing + * the SYSTEM SUSPEND call, i.e. the current CPU. + */ + gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); + + /* Save the GIC Distributor context */ + gicv3_distif_save(&dist_ctx); + + /* + * From here, all the components of the GIC can be safely powered down + * as long as there is an alternate way to handle wakeup interrupt + * sources. + */ +} + +void plat_versal_net_gic_resume(void) +{ + /* Restore the GIC Distributor context */ + gicv3_distif_init_restore(&dist_ctx); + + /* + * Restore the GIC Redistributor and ITS contexts after the + * Distributor context. As we only handle SYSTEM SUSPEND API, + * we only need to restore the context of the CPU that issued + * the SYSTEM SUSPEND call. + */ + gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); + + /* + * If an ITS is available, restore its context after + * the Redistributor using: + * gicv3_its_restore(gits_base, &its_ctx[i]) + * An implementation-defined sequence may be required to + * restore the whole ITS state. The ITS must also be + * re-enabled after this sequence has been executed. + */ +} diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c new file mode 100644 index 0000000..26ded89 --- /dev/null +++ b/plat/xilinx/versal_net/versal_net_ipi.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Versal NET IPI agent registers access management + */ + +#include <errno.h> +#include <string.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <lib/bakery_lock.h> +#include <lib/mmio.h> + +#include <ipi.h> +#include <plat_ipi.h> +#include <plat_private.h> + +/* versal_net ipi configuration table */ +static const struct ipi_config versal_net_ipi_table[IPI_ID_MAX] = { + /* A72 IPI */ + [IPI_ID_APU] = { + .ipi_bit_mask = IPI0_TRIG_BIT, + .ipi_reg_base = IPI0_REG_BASE, + .secure_only = 0, + }, + + /* PMC IPI */ + [IPI_ID_PMC] = { + .ipi_bit_mask = PMC_IPI_TRIG_BIT, + .ipi_reg_base = IPI0_REG_BASE, + .secure_only = 0, + }, + + /* RPU0 IPI */ + [IPI_ID_RPU0] = { + .ipi_bit_mask = IPI1_TRIG_BIT, + .ipi_reg_base = IPI1_REG_BASE, + .secure_only = 0, + }, + + /* RPU1 IPI */ + [IPI_ID_RPU1] = { + .ipi_bit_mask = IPI2_TRIG_BIT, + .ipi_reg_base = IPI2_REG_BASE, + .secure_only = 0, + }, + + /* IPI3 IPI */ + [IPI_ID_3] = { + .ipi_bit_mask = IPI3_TRIG_BIT, + .ipi_reg_base = IPI3_REG_BASE, + .secure_only = 0, + }, + + /* IPI4 IPI */ + [IPI_ID_4] = { + .ipi_bit_mask = IPI4_TRIG_BIT, + .ipi_reg_base = IPI4_REG_BASE, + .secure_only = 0, + }, + + /* IPI5 IPI */ + [IPI_ID_5] = { + .ipi_bit_mask = IPI5_TRIG_BIT, + .ipi_reg_base = IPI5_REG_BASE, + .secure_only = 0, + }, +}; + +/* versal_net_ipi_config_table_init() - Initialize versal_net IPI configuration data + * + * @ipi_config_table - IPI configuration table + * @ipi_total - Total number of IPI available + * + */ +void versal_net_ipi_config_table_init(void) +{ + ipi_config_table_init(versal_net_ipi_table, ARRAY_SIZE(versal_net_ipi_table)); +} |