From 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 28 Apr 2024 11:13:47 +0200 Subject: Adding upstream version 2.8.0+dfsg. Signed-off-by: Daniel Baumann --- drivers/arm/sbsa/sbsa.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 drivers/arm/sbsa/sbsa.c (limited to 'drivers/arm/sbsa/sbsa.c') diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c new file mode 100644 index 0000000..79c6f26 --- /dev/null +++ b/drivers/arm/sbsa/sbsa.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) +{ + assert((value >> SBSA_WDOG_WOR_WIDTH) == 0); + mmio_write_32(base + SBSA_WDOG_WOR_LOW_OFFSET, + ((uint32_t)value & UINT32_MAX)); + mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); +} + +/* + * Start the watchdog timer at base address "base" for a + * period of "ms" milliseconds.The watchdog has to be + * refreshed within this time period. + */ +void sbsa_wdog_start(uintptr_t base, uint64_t ms) +{ + uint64_t counter_freq; + uint64_t offset_reg_value; + + counter_freq = (uint64_t)plat_get_syscnt_freq2(); + offset_reg_value = ms * counter_freq / 1000; + + sbsa_watchdog_offset_reg_write(base, offset_reg_value); + mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, SBSA_WDOG_WCS_EN); +} + +/* Stop the watchdog */ +void sbsa_wdog_stop(uintptr_t base) +{ + mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); +} -- cgit v1.2.3