From 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 28 Apr 2024 11:13:47 +0200 Subject: Adding upstream version 2.8.0+dfsg. Signed-off-by: Daniel Baumann --- plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c | 35 +++ plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S | 93 +++++++ plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S | 120 +++++++++ plat/arm/board/fvp_r/fvp_r_bl1_main.c | 268 ++++++++++++++++++++ plat/arm/board/fvp_r/fvp_r_bl1_setup.c | 248 +++++++++++++++++++ plat/arm/board/fvp_r/fvp_r_common.c | 289 ++++++++++++++++++++++ plat/arm/board/fvp_r/fvp_r_context_mgmt.c | 53 ++++ plat/arm/board/fvp_r/fvp_r_debug.S | 47 ++++ plat/arm/board/fvp_r/fvp_r_def.h | 103 ++++++++ plat/arm/board/fvp_r/fvp_r_err.c | 48 ++++ plat/arm/board/fvp_r/fvp_r_helpers.S | 128 ++++++++++ plat/arm/board/fvp_r/fvp_r_io_storage.c | 105 ++++++++ plat/arm/board/fvp_r/fvp_r_misc_helpers.S | 32 +++ plat/arm/board/fvp_r/fvp_r_private.h | 23 ++ plat/arm/board/fvp_r/fvp_r_stack_protector.c | 24 ++ plat/arm/board/fvp_r/fvp_r_trusted_boot.c | 73 ++++++ plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h | 28 +++ plat/arm/board/fvp_r/include/platform_def.h | 268 ++++++++++++++++++++ plat/arm/board/fvp_r/platform.mk | 99 ++++++++ 19 files changed, 2084 insertions(+) create mode 100644 plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c create mode 100644 plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S create mode 100644 plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S create mode 100644 plat/arm/board/fvp_r/fvp_r_bl1_main.c create mode 100644 plat/arm/board/fvp_r/fvp_r_bl1_setup.c create mode 100644 plat/arm/board/fvp_r/fvp_r_common.c create mode 100644 plat/arm/board/fvp_r/fvp_r_context_mgmt.c create mode 100644 plat/arm/board/fvp_r/fvp_r_debug.S create mode 100644 plat/arm/board/fvp_r/fvp_r_def.h create mode 100644 plat/arm/board/fvp_r/fvp_r_err.c create mode 100644 plat/arm/board/fvp_r/fvp_r_helpers.S create mode 100644 plat/arm/board/fvp_r/fvp_r_io_storage.c create mode 100644 plat/arm/board/fvp_r/fvp_r_misc_helpers.S create mode 100644 plat/arm/board/fvp_r/fvp_r_private.h create mode 100644 plat/arm/board/fvp_r/fvp_r_stack_protector.c create mode 100644 plat/arm/board/fvp_r/fvp_r_trusted_boot.c create mode 100644 plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h create mode 100644 plat/arm/board/fvp_r/include/platform_def.h create mode 100644 plat/arm/board/fvp_r/platform.mk (limited to 'plat/arm/board/fvp_r') diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c new file mode 100644 index 0000000..ae6af6c --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "../../../../bl1/bl1_private.h" +#include + +#include + +/******************************************************************************* + * Function that does the first bit of architectural setup that affects + * execution in the non-secure address space. + ******************************************************************************/ +void bl1_arch_setup(void) +{ + /* v8-R64 does not include SCRs. */ +} + +/******************************************************************************* + * Set the Secure EL1 required architectural state + ******************************************************************************/ +void bl1_arch_next_el_setup(void) +{ + u_register_t next_sctlr; + + /* Use the same endianness than the current BL */ + next_sctlr = (read_sctlr_el2() & SCTLR_EE_BIT); + + /* Set SCTLR Secure EL1 */ + next_sctlr |= SCTLR_EL1_RES1; + + write_sctlr_el1(next_sctlr); +} diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S b/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S new file mode 100644 index 0000000..15f4c43 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + + .globl bl1_entrypoint + .globl bl1_run_next_image + + + /* ----------------------------------------------------- + * bl1_entrypoint() is the entry point into the trusted + * firmware code when a cpu is released from warm or + * cold reset. + * ----------------------------------------------------- + */ + +func bl1_entrypoint + /* --------------------------------------------------------------------- + * If the reset address is programmable then bl1_entrypoint() is + * executed only on the cold boot path. Therefore, we can skip the warm + * boot mailbox mechanism. + * --------------------------------------------------------------------- + */ + el2_entrypoint_common \ + _init_sctlr=1 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=bl1_exceptions \ + _pie_fixup_size=0 + + /* -------------------------------------------------------------------- + * Perform BL1 setup + * -------------------------------------------------------------------- + */ + bl bl1_setup + + /* -------------------------------------------------------------------- + * Initialize platform and jump to our c-entry point + * for this type of reset. + * -------------------------------------------------------------------- + */ + bl bl1_main + + /* --------------------------------------------- + * Should never reach this point. + * --------------------------------------------- + */ + no_ret plat_panic_handler +endfunc bl1_entrypoint + +func bl1_run_next_image + mov x20,x0 + + /* --------------------------------------------- + * MPU needs to be disabled because both BL1 and BL33 execute + * in EL2, and therefore share the same address space. + * BL33 will initialize the address space according to its + * own requirement. + * --------------------------------------------- + */ + bl disable_mpu_icache_el2 + + /* --------------------------------------------- + * Wipe clean and disable all MPU regions. This function expects + * that the MPU has already been turned off, and caching concerns + * addressed, but it also explicitly turns off the MPU. + * --------------------------------------------- + */ + bl clear_all_mpu_regions + + /* -------------------------------------------------- + * Do the transition to next boot image. + * -------------------------------------------------- + */ + ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] + msr elr_el2, x0 + msr spsr_el2, x1 + + ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] + ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] + ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] + ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] + exception_return +endfunc bl1_run_next_image diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S b/plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S new file mode 100644 index 0000000..43c2e01 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +/* ----------------------------------------------------------------------------- + * File contains an EL2 equivalent of the EL3 vector table from: + * .../bl1/aarch64/bl1_exceptions.S + * ----------------------------------------------------------------------------- + */ + +/* ----------------------------------------------------------------------------- + * Very simple stackless exception handlers used by BL1. + * ----------------------------------------------------------------------------- + */ + .globl bl1_exceptions + +vector_base bl1_exceptions + + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSP0 + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry SynchronousExceptionSP0 + +vector_entry IrqSP0 + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry IrqSP0 + +vector_entry FiqSP0 + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry FiqSP0 + +vector_entry SErrorSP0 + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSPx + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry SynchronousExceptionSPx + +vector_entry IrqSPx + mov x0, #IRQ_SP_ELX + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry IrqSPx + +vector_entry FiqSPx + mov x0, #FIQ_SP_ELX + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry FiqSPx + +vector_entry SErrorSPx + mov x0, #SERROR_SP_ELX + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionA64 + /* The current v8-R64 implementation does not support conduit calls */ + b el2_panic +end_vector_entry SynchronousExceptionA64 + +vector_entry IrqA64 + mov x0, #IRQ_AARCH64 + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry IrqA64 + +vector_entry FiqA64 + mov x0, #FIQ_AARCH64 + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry FiqA64 + +vector_entry SErrorA64 + mov x0, #SERROR_AARCH64 + bl plat_report_exception + no_ret plat_panic_handler +end_vector_entry SErrorA64 + + +unexpected_sync_exception: + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + no_ret plat_panic_handler + + /* ----------------------------------------------------- + * Save Secure/Normal world context and jump to + * BL1 SMC handler. + * ----------------------------------------------------- + */ diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_main.c b/plat/arm/board/fvp_r/fvp_r_bl1_main.c new file mode 100644 index 0000000..841a176 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_bl1_main.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "../../../../bl1/bl1_private.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + + +void cm_prepare_el2_exit(void); + +void bl1_run_next_image(const struct entry_point_info *bl_ep_info); + +/******************************************************************************* + * Function to perform late architectural and platform specific initialization. + * It also queries the platform to load and run next BL image. Only called + * by the primary cpu after a cold boot. + ******************************************************************************/ +void bl1_transfer_bl33(void) +{ + unsigned int image_id; + + /* Get the image id of next image to load and run. */ + image_id = bl1_plat_get_next_image_id(); + +#if !ARM_DISABLE_TRUSTED_WDOG + /* Disable watchdog before leaving BL1 */ + plat_arm_secure_wdt_stop(); +#endif + + bl1_run_next_image(&bl1_plat_get_image_desc(image_id)->ep_info); +} + +/******************************************************************************* + * This function locates and loads the BL33 raw binary image in the trusted SRAM. + * Called by the primary cpu after a cold boot. + * TODO: Add support for alternative image load mechanism e.g using virtio/elf + * loader etc. + ******************************************************************************/ +void bl1_load_bl33(void) +{ + image_desc_t *desc; + image_info_t *info; + int err; + + /* Get the image descriptor */ + desc = bl1_plat_get_image_desc(BL33_IMAGE_ID); + assert(desc != NULL); + + /* Get the image info */ + info = &desc->image_info; + INFO("BL1: Loading BL33\n"); + + err = bl1_plat_handle_pre_image_load(BL33_IMAGE_ID); + if (err != 0) { + ERROR("Failure in pre image load handling of BL33 (%d)\n", err); + plat_error_handler(err); + } + + err = load_auth_image(BL33_IMAGE_ID, info); + if (err != 0) { + ERROR("Failed to load BL33 firmware.\n"); + plat_error_handler(err); + } + + /* Allow platform to handle image information. */ + err = bl1_plat_handle_post_image_load(BL33_IMAGE_ID); + if (err != 0) { + ERROR("Failure in post image load handling of BL33 (%d)\n", err); + plat_error_handler(err); + } + + NOTICE("BL1: Booting BL33\n"); +} + +/******************************************************************************* + * Helper utility to calculate the BL2 memory layout taking into consideration + * the BL1 RW data assuming that it is at the top of the memory layout. + ******************************************************************************/ +void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout) +{ + assert(bl1_mem_layout != NULL); + assert(bl2_mem_layout != NULL); + + /* + * Remove BL1 RW data from the scope of memory visible to BL2. + * This is assuming BL1 RW data is at the top of bl1_mem_layout. + */ + assert(bl1_mem_layout->total_base < BL1_RW_BASE); + bl2_mem_layout->total_base = bl1_mem_layout->total_base; + bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; + + flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); +} + +/******************************************************************************* + * This function prepares for entry to BL33 + ******************************************************************************/ +void bl1_prepare_next_image(unsigned int image_id) +{ + unsigned int mode = MODE_EL1; + image_desc_t *desc; + entry_point_info_t *next_bl_ep; + +#if CTX_INCLUDE_AARCH32_REGS + /* + * Ensure that the build flag to save AArch32 system registers in CPU + * context is not set for AArch64-only platforms. + */ + if (el_implemented(1) == EL_IMPL_A64ONLY) { + ERROR("EL1 supports AArch64-only. Please set build flag %s", + "CTX_INCLUDE_AARCH32_REGS = 0\n"); + panic(); + } +#endif + + /* Get the image descriptor. */ + desc = bl1_plat_get_image_desc(image_id); + assert(desc != NULL); + + /* Get the entry point info. */ + next_bl_ep = &desc->ep_info; + + /* FVP-R is only secure */ + assert(GET_SECURITY_STATE(next_bl_ep->h.attr) == SECURE); + + /* Prepare the SPSR for the next BL image. */ + next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode, + (uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + + /* Allow platform to make change */ + bl1_plat_set_ep_info(image_id, next_bl_ep); + + /* Prepare context for the next EL */ + cm_prepare_el2_exit(); + + /* Indicate that image is in execution state. */ + desc->state = IMAGE_STATE_EXECUTED; + + print_entry_point_info(next_bl_ep); +} + +/******************************************************************************* + * Setup function for BL1. + ******************************************************************************/ +void bl1_setup(void) +{ + /* Perform early platform-specific setup */ + bl1_early_platform_setup(); + + /* Perform late platform-specific setup */ + bl1_plat_arch_setup(); +} + +/******************************************************************************* + * Function to perform late architectural and platform specific initialization. + * It also queries the platform to load and run next BL image. Only called + * by the primary cpu after a cold boot. + ******************************************************************************/ +void bl1_main(void) +{ + unsigned int image_id; + + /* Announce our arrival */ + NOTICE(FIRMWARE_WELCOME_STR); + NOTICE("BL1: %s\n", version_string); + NOTICE("BL1: %s\n", build_message); + + INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT); + + print_errata_status(); + +#if ENABLE_ASSERTIONS + u_register_t val; + /* + * Ensure that MMU/Caches and coherency are turned on + */ + val = read_sctlr_el2(); + + assert((val & SCTLR_M_BIT) != 0U); + assert((val & SCTLR_C_BIT) != 0U); + assert((val & SCTLR_I_BIT) != 0U); + /* + * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the + * provided platform value + */ + val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; + /* + * If CWG is zero, then no CWG information is available but we can + * at least check the platform value is less than the architectural + * maximum. + */ + if (val != 0) { + assert(SIZE_FROM_LOG2_WORDS(val) == CACHE_WRITEBACK_GRANULE); + } else { + assert(MAX_CACHE_LINE_SIZE >= CACHE_WRITEBACK_GRANULE); + } +#endif /* ENABLE_ASSERTIONS */ + + /* Perform remaining generic architectural setup from ELmax */ + bl1_arch_setup(); + +#if TRUSTED_BOARD_BOOT + /* Initialize authentication module */ + auth_mod_init(); +#endif /* TRUSTED_BOARD_BOOT */ + + /* Perform platform setup in BL1. */ + bl1_platform_setup(); + + /* Get the image id of next image to load and run. */ + image_id = bl1_plat_get_next_image_id(); + + /* + * We currently interpret any image id other than + * BL2_IMAGE_ID as the start of firmware update. + */ + if (image_id == BL33_IMAGE_ID) { + bl1_load_bl33(); + } else { + NOTICE("BL1-FWU: *******FWU Process Started*******\n"); + } + + bl1_prepare_next_image(image_id); + + console_flush(); + + bl1_transfer_bl33(); +} + +/******************************************************************************* + * Function called just before handing over to the next BL to inform the user + * about the boot progress. In debug mode, also print details about the BL + * image's execution context. + ******************************************************************************/ +void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) +{ + NOTICE("BL1: Booting BL31\n"); + print_entry_point_info(bl_ep_info); +} + +#if SPIN_ON_BL1_EXIT +void print_debug_loop_message(void) +{ + NOTICE("BL1: Debug loop, spinning forever\n"); + NOTICE("BL1: Please connect the debugger to continue\n"); +} +#endif + diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c new file mode 100644 index 0000000..1ac0a9c --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Use the xlat_tables_v2 data structures: */ +#define XLAT_TABLES_LIB_V2 1 + +#include + +#include +#include +#include +#include +#include +#include + +#include "fvp_r_private.h" +#include +#include +#include +#include +#include + +#define MAP_BL1_TOTAL MAP_REGION_FLAT( \ + bl1_tzram_layout.total_base, \ + bl1_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) +/* + * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section + * otherwise one region is defined containing both + */ +#if SEPARATE_CODE_AND_RODATA +#define MAP_BL1_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL1_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL1_RO_DATA_BASE, \ + BL1_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#else +#define MAP_BL1_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL1_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) +#endif + +/* Data structure which holds the extents of the trusted SRAM for BL1*/ +static meminfo_t bl1_tzram_layout; + +struct meminfo *bl1_plat_sec_mem_layout(void) +{ + return &bl1_tzram_layout; +} + +void arm_bl1_early_platform_setup(void) +{ + +#if !ARM_DISABLE_TRUSTED_WDOG + /* Enable watchdog */ + plat_arm_secure_wdt_start(); +#endif + + /* Initialize the console to provide early debug support */ + arm_console_boot_init(); + + /* Allow BL1 to see the whole Trusted RAM */ + bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; + bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; +} + +/* Boolean variable to hold condition whether firmware update needed or not */ +static bool is_fwu_needed; + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ +void bl1_early_platform_setup(void) +{ + arm_bl1_early_platform_setup(); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); + + /* + * Initialize Interconnect for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + fvp_interconnect_init(); + /* + * Enable coherency in Interconnect for the primary CPU's cluster. + */ + fvp_interconnect_enable(); +} + +void arm_bl1_plat_arch_setup(void) +{ + const mmap_region_t bl_regions[] = { + MAP_BL1_TOTAL, + MAP_BL1_RO, +#if USE_ROMLIB + ARM_MAP_ROMLIB_CODE, + ARM_MAP_ROMLIB_DATA, +#endif +#if ARM_CRYPTOCELL_INTEG + ARM_MAP_BL_COHERENT_RAM, +#endif + /* DRAM1_region: */ + MAP_REGION_FLAT( \ + PLAT_ARM_DRAM1_BASE, \ + PLAT_ARM_DRAM1_SIZE, \ + MT_MEMORY | MT_SECURE | MT_EXECUTE \ + | MT_RW | MT_NON_CACHEABLE), + /* NULL terminator: */ + {0} + }; + + setup_page_tables(bl_regions, plat_arm_get_mmap()); + enable_mpu_el2(0); + + arm_setup_romlib(); +} + +void plat_arm_secure_wdt_start(void) +{ + sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); +} + +void plat_arm_secure_wdt_stop(void) +{ + sp805_stop(ARM_SP805_TWDG_BASE); +} + +/* + * Perform the platform specific architecture setup shared between + * ARM standard platforms. + */ +void arm_bl1_platform_setup(void) +{ + uint32_t fw_config_max_size; + + /* Initialise the IO layer and register platform IO devices */ + plat_arm_io_setup(); + + /* Check if we need FWU before further processing */ + is_fwu_needed = plat_arm_bl1_fwu_needed(); + if (is_fwu_needed) { + ERROR("Skip platform setup as FWU detected\n"); + return; + } + + /* Set global DTB info for fixed fw_config information */ + fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE; + set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, + FW_CONFIG_ID); + + assert(bl1_plat_get_image_desc(BL33_IMAGE_ID) != NULL); + + /* + * Allow access to the System counter timer module and program + * counter frequency for non secure images during FWU + */ +#ifdef ARM_SYS_TIMCTL_BASE + arm_configure_sys_timer(); +#endif +#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER) + write_cntfrq_el0(plat_get_syscnt_freq2()); +#endif +} + +void bl1_platform_setup(void) +{ + arm_bl1_platform_setup(); + + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); +} + +__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) +{ + /* Setup the watchdog to reset the system as soon as possible */ + sp805_refresh(ARM_SP805_TWDG_BASE, 1U); + + while (true) { + wfi(); + } +} + +unsigned int bl1_plat_get_next_image_id(void) +{ + return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL33_IMAGE_ID; +} + +/* + * Returns BL33 image details. + */ +struct image_desc *bl1_plat_get_image_desc(unsigned int image_id) +{ + static image_desc_t bl33_img_desc = BL33_IMAGE_DESC; + + return &bl33_img_desc; +} + +/* + * This function populates the default arguments to BL33. + * The BL33 memory layout structure is allocated and the + * calculated layout is populated in arg1 to BL33. + */ +int bl1_plat_handle_post_image_load(unsigned int image_id) +{ + meminfo_t *bl33_secram_layout; + meminfo_t *bl1_secram_layout; + image_desc_t *image_desc; + entry_point_info_t *ep_info; + + if (image_id != BL33_IMAGE_ID) { + return 0; + } + /* Get the image descriptor */ + image_desc = bl1_plat_get_image_desc(BL33_IMAGE_ID); + assert(image_desc != NULL); + + /* Get the entry point info */ + ep_info = &image_desc->ep_info; + + /* Find out how much free trusted ram remains after BL1 load */ + bl1_secram_layout = bl1_plat_sec_mem_layout(); + + /* + * Create a new layout of memory for BL33 as seen by BL1 i.e. + * tell it the amount of total and free memory available. + * This layout is created at the first free address visible + * to BL33. BL33 will read the memory layout before using its + * memory for other purposes. + */ + bl33_secram_layout = (meminfo_t *) bl1_secram_layout->total_base; + + bl1_calc_bl2_mem_layout(bl1_secram_layout, bl33_secram_layout); + + ep_info->args.arg1 = (uintptr_t)bl33_secram_layout; + + VERBOSE("BL1: BL3 memory layout address = %p\n", + (void *) bl33_secram_layout); + return 0; +} diff --git a/plat/arm/board/fvp_r/fvp_r_common.c b/plat/arm/board/fvp_r/fvp_r_common.c new file mode 100644 index 0000000..edcf658 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_common.c @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This uses xlat_mpu, but tables are set up using V2 mmap_region_t */ +#define XLAT_TABLES_LIB_V2 1 + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fvp_r_private.h" +#include +#include +#include +#include + + +/* Defines for GIC Driver build time selection */ +#define FVP_R_GICV3 2 + +/******************************************************************************* + * arm_config holds the characteristics of the differences between the FVP_R + * platforms. It will be populated during cold boot at each boot stage by the + * primary before enabling the MPU (to allow interconnect configuration) & + * used thereafter. Each BL will have its own copy to allow independent + * operation. + ******************************************************************************/ +arm_config_t arm_config; + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ + DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Need to be mapped with write permissions in order to set a new non-volatile + * counter value. + */ +#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ + DEVICE2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Table of memory regions for various BL stages to map using the MPU. + * This doesn't include Trusted SRAM as setup_page_tables() already takes care + * of mapping it. + * + * The flash needs to be mapped as writable in order to erase the FIP's Table of + * Contents in case of unrecoverable error (see plat_error_handler()). + */ +#ifdef IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0_RW, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, +#if TRUSTED_BOARD_BOOT + /* To access the Root of Trust Public Key registers. */ + MAP_DEVICE2, +#endif + {0} +}; +#endif + +ARM_CASSERT_MMAP + +static const int fvp_cci400_map[] = { + PLAT_FVP_R_CCI400_CLUS0_SL_PORT, + PLAT_FVP_R_CCI400_CLUS1_SL_PORT, +}; + +static const int fvp_cci5xx_map[] = { + PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT, + PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT, +}; + +static unsigned int get_interconnect_master(void) +{ + unsigned int master; + u_register_t mpidr; + + mpidr = read_mpidr_el1(); + master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? + MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); + + assert(master < FVP_R_CLUSTER_COUNT); + return master; +} + +/******************************************************************************* + * Initialize the platform config for future decision making + ******************************************************************************/ +void __init fvp_config_setup(void) +{ + unsigned int rev, hbi, bld, arch, sys_id; + + arm_config.flags |= ARM_CONFIG_BASE_MMAP; + sys_id = mmio_read_32(V2M_FVP_R_SYSREGS_BASE + V2M_SYS_ID); + rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; + hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; + bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; + arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; + + if (arch != ARCH_MODEL) { + ERROR("This firmware is for FVP_R models\n"); + panic(); + } + + /* + * The build field in the SYS_ID tells which variant of the GIC + * memory is implemented by the model. + */ + switch (bld) { + case BLD_GIC_VE_MMAP: + ERROR("Legacy Versatile Express memory map for GIC %s", + "peripheral is not supported\n"); + panic(); + break; + case BLD_GIC_A53A57_MMAP: + break; + default: + ERROR("Unsupported board build %x\n", bld); + panic(); + } + + /* + * The hbi field in the SYS_ID is 0x020 for the Base FVP_R & 0x010 + * for the Foundation FVP_R. + */ + switch (hbi) { + case HBI_FOUNDATION_FVP_R: + arm_config.flags = 0; + + /* + * Check for supported revisions of Foundation FVP_R + * Allow future revisions to run but emit warning diagnostic + */ + switch (rev) { + case REV_FOUNDATION_FVP_R_V2_0: + case REV_FOUNDATION_FVP_R_V2_1: + case REV_FOUNDATION_FVP_R_v9_1: + case REV_FOUNDATION_FVP_R_v9_6: + break; + default: + WARN("Unrecognized Foundation FVP_R revision %x\n", rev); + break; + } + break; + case HBI_BASE_FVP_R: + arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); + + /* + * Check for supported revisions + * Allow future revisions to run but emit warning diagnostic + */ + switch (rev) { + case REV_BASE_FVP_R_V0: + arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; + break; + default: + WARN("Unrecognized Base FVP_R revision %x\n", rev); + break; + } + break; + default: + ERROR("Unsupported board HBI number 0x%x\n", hbi); + panic(); + } + + /* + * We assume that the presence of MT bit, and therefore shifted + * affinities, is uniform across the platform: either all CPUs, or no + * CPUs implement it. + */ + if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) { + arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; + } +} + + +void __init fvp_interconnect_init(void) +{ + uintptr_t cci_base = 0U; + const int *cci_map = NULL; + unsigned int map_size = 0U; + + /* Initialize the right interconnect */ + if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { + cci_base = PLAT_FVP_R_CCI5XX_BASE; + cci_map = fvp_cci5xx_map; + map_size = ARRAY_SIZE(fvp_cci5xx_map); + } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { + cci_base = PLAT_FVP_R_CCI400_BASE; + cci_map = fvp_cci400_map; + map_size = ARRAY_SIZE(fvp_cci400_map); + } else { + return; + } + + assert(cci_base != 0U); + assert(cci_map != NULL); + cci_init(cci_base, cci_map, map_size); +} + +void fvp_interconnect_enable(void) +{ + unsigned int master; + + if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | + ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { + master = get_interconnect_master(); + cci_enable_snoop_dvm_reqs(master); + } +} + +void fvp_interconnect_disable(void) +{ + unsigned int master; + + if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | + ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { + master = get_interconnect_master(); + cci_disable_snoop_dvm_reqs(master); + } +} + +#if TRUSTED_BOARD_BOOT +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + assert(heap_addr != NULL); + assert(heap_size != NULL); + + return arm_get_mbedtls_heap(heap_addr, heap_size); +} +#endif + +void fvp_timer_init(void) +{ +#if USE_SP804_TIMER + /* Enable the clock override for SP804 timer 0, which means that no + * clock dividers are applied and the raw (35MHz) clock will be used. + */ + mmio_write_32(V2M_SP810_BASE, FVP_R_SP810_CTRL_TIM0_OV); + + /* Initialize delay timer driver using SP804 dual timer 0 */ + sp804_timer_init(V2M_SP804_TIMER0_BASE, + SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); +#else + generic_delay_timer_init(); + + /* Enable System level generic timer */ + mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0U) | CNTCR_EN); +#endif /* USE_SP804_TIMER */ +} + +/* Get SOC version */ +int32_t plat_get_soc_version(void) +{ + return (int32_t) + ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT) + | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT) + | FVP_R_SOC_ID); +} + +/* Get SOC revision */ +int32_t plat_get_soc_revision(void) +{ + unsigned int sys_id; + + sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); + return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) & + V2M_SYS_ID_REV_MASK); +} diff --git a/plat/arm/board/fvp_r/fvp_r_context_mgmt.c b/plat/arm/board/fvp_r/fvp_r_context_mgmt.c new file mode 100644 index 0000000..d172d2d --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_context_mgmt.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/************************************************************ + * For R-class everything is in secure world. + * Prepare the CPU system registers for first entry into EL1 + ************************************************************/ +void cm_prepare_el2_exit(void) +{ + uint64_t hcr_el2 = 0U; + + /* + * The use of ARMv8.3 pointer authentication (PAuth) is governed + * by fields in HCR_EL2, which trigger a 'trap to EL2' if not + * enabled. This register initialized at boot up, update PAuth + * bits. + * + * HCR_API_BIT: Set to one to disable traps to EL2 if lower ELs + * access PAuth registers + * + * HCR_APK_BIT: Set to one to disable traps to EL2 if lower ELs + * access PAuth instructions + */ + hcr_el2 = read_hcr_el2(); + write_hcr_el2(hcr_el2 | HCR_API_BIT | HCR_APK_BIT); + + /* + * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN + * on reset and are set to zero except for field(s) listed below. + * + * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to EL2 + * if lower ELs accesses to the physical timer registers. + * + * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to EL2 + * if lower ELs access to the physical counter registers. + */ + write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); + + /* + * On Armv8-R, the EL1&0 memory system architecture is configurable + * as a VMSA or PMSA. All the fields architecturally UNKNOWN on reset + * and are set to zero except for field listed below. + * + * VCTR_EL2.MSA: Set to one to ensure the VMSA is enabled so that + * rich OS can boot. + */ + write_vtcr_el2(VTCR_RESET_VAL | VTCR_EL2_MSA); +} diff --git a/plat/arm/board/fvp_r/fvp_r_debug.S b/plat/arm/board/fvp_r/fvp_r_debug.S new file mode 100644 index 0000000..88f0a29 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_debug.S @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + + .globl el2_panic + + /*********************************************************** + * The common implementation of do_panic for all BL stages + ***********************************************************/ + +.section .rodata.panic_str, "aS" + panic_msg: .asciz "PANIC at PC : 0x" + +/* + * el2_panic will be redefined by the + * crash reporting mechanism (if enabled) + */ +el2_panic: + mov x6, x30 + bl plat_crash_console_init + + /* Check if the console is initialized */ + cbz x0, _panic_handler + + /* The console is initialized */ + adr x4, panic_msg + bl asm_print_str + mov x4, x6 + + /* The panic location is lr -4 */ + sub x4, x4, #4 + bl asm_print_hex + + bl plat_crash_console_flush + +_panic_handler: + /* Pass to plat_panic_handler the address from where el2_panic was + * called, not the address of the call from el2_panic. + */ + mov x30, x6 + b plat_panic_handler diff --git a/plat/arm/board/fvp_r/fvp_r_def.h b/plat/arm/board/fvp_r/fvp_r_def.h new file mode 100644 index 0000000..eda39cf --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_def.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_R_DEF_H +#define FVP_R_DEF_H + +#include + +/****************************************************************************** + * FVP-R topology constants + *****************************************************************************/ +#define FVP_R_CLUSTER_COUNT 2 +#define FVP_R_MAX_CPUS_PER_CLUSTER 4 +#define FVP_R_MAX_PE_PER_CPU 1 +#define FVP_R_PRIMARY_CPU 0x0 + +/****************************************************************************** + * Definition of platform soc id + *****************************************************************************/ +#define FVP_R_SOC_ID 0 + +/******************************************************************************* + * FVP_R memory map related constants + ******************************************************************************/ + +#define FLASH1_BASE UL(0x8c000000) +#define FLASH1_SIZE UL(0x04000000) + +#define PSRAM_BASE UL(0x94000000) +#define PSRAM_SIZE UL(0x04000000) + +#define VRAM_BASE UL(0x98000000) +#define VRAM_SIZE UL(0x02000000) + +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE UL(0xa0000000) +#define DEVICE0_SIZE UL(0x0c200000) + +/* + * In case of FVP_R models with CCN, the CCN register space overlaps into + * the NSRAM area. + */ +#define DEVICE1_BASE UL(0xae000000) +#define DEVICE1_SIZE UL(0x1A00000) + +#define NSRAM_BASE UL(0xae000000) +#define NSRAM_SIZE UL(0x10000) +/* Devices in the second GB */ +#define DEVICE2_BASE UL(0xffe00000) +#define DEVICE2_SIZE UL(0x00200000) + +#define PCIE_EXP_BASE UL(0xc0000000) +#define TZRNG_BASE UL(0x7fe60000) + +/* Non-volatile counters */ +#define TRUSTED_NVCTR_BASE UL(0xffe70000) +#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000)) +#define TFW_NVCTR_SIZE UL(4) +#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004)) +#define NTFW_CTR_SIZE UL(4) + +/* Keys */ +#define SOC_KEYS_BASE UL(0xffe80000) +#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000)) +#define TZ_PUB_KEY_HASH_SIZE UL(32) +#define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020)) +#define HU_KEY_SIZE UL(16) +#define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044)) +#define END_KEY_SIZE UL(32) + +/* Constants to distinguish FVP_R type */ +#define HBI_BASE_FVP_R U(0x020) +#define REV_BASE_FVP_R_V0 U(0x0) +#define REV_BASE_FVP_R_REVC U(0x2) + +#define HBI_FOUNDATION_FVP_R U(0x010) +#define REV_FOUNDATION_FVP_R_V2_0 U(0x0) +#define REV_FOUNDATION_FVP_R_V2_1 U(0x1) +#define REV_FOUNDATION_FVP_R_v9_1 U(0x2) +#define REV_FOUNDATION_FVP_R_v9_6 U(0x3) + +#define BLD_GIC_VE_MMAP U(0x0) +#define BLD_GIC_A53A57_MMAP U(0x1) + +#define ARCH_MODEL U(0x1) + +/* FVP_R Power controller base address*/ +#define PWRC_BASE UL(0x1c100000) + +/* FVP_R SP804 timer frequency is 35 MHz*/ +#define SP804_TIMER_CLKMULT 1 +#define SP804_TIMER_CLKDIV 35 + +/* SP810 controller. FVP_R specific flags */ +#define FVP_R_SP810_CTRL_TIM0_OV BIT_32(16) +#define FVP_R_SP810_CTRL_TIM1_OV BIT_32(18) +#define FVP_R_SP810_CTRL_TIM2_OV BIT_32(20) +#define FVP_R_SP810_CTRL_TIM3_OV BIT_32(22) + +#endif /* FVP_R_DEF_H */ diff --git a/plat/arm/board/fvp_r/fvp_r_err.c b/plat/arm/board/fvp_r/fvp_r_err.c new file mode 100644 index 0000000..7ee752b --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_err.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include + +/* + * FVP_R error handler + */ +__dead2 void plat_arm_error_handler(int err) +{ + int ret; + + switch (err) { + case -ENOENT: + case -EAUTH: + /* Image load or authentication error. Erase the ToC */ + INFO("Erasing FIP ToC from flash...\n"); + (void)nor_unlock(PLAT_ARM_FLASH_IMAGE_BASE); + ret = nor_word_program(PLAT_ARM_FLASH_IMAGE_BASE, 0); + if (ret != 0) { + ERROR("Cannot erase ToC\n"); + } else { + INFO("Done\n"); + } + break; + default: + /* Unexpected error */ + break; + } + + (void)console_flush(); + + /* Setup the watchdog to reset the system as soon as possible */ + sp805_refresh(ARM_SP805_TWDG_BASE, 1U); + + while (true) { + wfi(); + } +} diff --git a/plat/arm/board/fvp_r/fvp_r_helpers.S b/plat/arm/board/fvp_r/fvp_r_helpers.S new file mode 100644 index 0000000..ba85777 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_helpers.S @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include + + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * TODO: Should we read the PSYS register to make sure + * that the request has gone through. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* --------------------------------------------- + * Power down this cpu. + * TODO: Do we need to worry about powering the + * cluster down as well here? That will need + * locks which we won't have unless an elf- + * loader zeroes out the zi section. + * --------------------------------------------- + */ + mrs x0, mpidr_el1 + mov_imm x1, PWRC_BASE + str w0, [x1, #PPOFFR_OFF] + + /* --------------------------------------------- + * There is no sane reason to come out of this + * wfi so panic if we do. This cpu will be pow- + * ered on and reset by the cpu_on pm api + * --------------------------------------------- + */ + dsb sy + wfi + no_ret plat_panic_handler +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * uintptr_t plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On FVP_R, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, read the mailbox and return the address it contains. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* --------------------------------------------------------------------- + * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC + * WakeRequest signal" then it is a warm boot. + * --------------------------------------------------------------------- + */ + mrs x2, mpidr_el1 + mov_imm x1, PWRC_BASE + str w2, [x1, #PSYSR_OFF] + ldr w2, [x1, #PSYSR_OFF] + ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH + cmp w2, #WKUP_PPONR + beq warm_reset + cmp w2, #WKUP_GICREQ + beq warm_reset + + /* Cold reset */ + mov x0, #0 + ret + +warm_reset: + /* --------------------------------------------------------------------- + * A mailbox is maintained in the trusted SRAM. It is flushed out of the + * caches after every update using normal memory so it is safe to read + * it here with SO attributes. + * --------------------------------------------------------------------- + */ + mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE + ldr x0, [x0] + cbz x0, _panic_handler + ret + + /* --------------------------------------------------------------------- + * The power controller indicates this is a warm reset but the mailbox + * is empty. This should never happen! + * --------------------------------------------------------------------- + */ +_panic_handler: + no_ret plat_panic_handler +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + mov_imm x1, MPIDR_AFFINITY_MASK + and x0, x0, x1 + cmp x0, #FVP_R_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary diff --git a/plat/arm/board/fvp_r/fvp_r_io_storage.c b/plat/arm/board/fvp_r/fvp_r_io_storage.c new file mode 100644 index 0000000..3b44828 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_io_storage.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Semihosting filenames */ +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" +#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" +#endif /* TRUSTED_BOARD_BOOT */ + +/* IO devices */ +static const io_dev_connector_t *sh_dev_con; +static uintptr_t sh_dev_handle; + +static const io_file_spec_t sh_file_spec[] = { + [BL33_IMAGE_ID] = { + .path = BL33_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_KEY_CERT_ID] = { + .path = TRUSTED_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + .path = NT_FW_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + .path = NT_FW_CONTENT_CERT_NAME, + .mode = FOPEN_MODE_RB + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + + +static int open_semihosting(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if the file exists on semi-hosting.*/ + result = io_dev_init(sh_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(sh_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Semi-hosting IO\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_arm_io_setup(void) +{ + int io_result; + + io_result = arm_io_setup(); + if (io_result < 0) { + panic(); + } + + /* Register the additional IO devices on this platform */ + io_result = register_io_dev_sh(&sh_dev_con); + if (io_result < 0) { + panic(); + } + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle); + if (io_result < 0) { + panic(); + } +} + +/* + * FVP_R provides semihosting as an alternative to load images + */ +int plat_arm_get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]); + + if (result == 0) { + *dev_handle = sh_dev_handle; + *image_spec = (uintptr_t)&sh_file_spec[image_id]; + } + + return result; +} diff --git a/plat/arm/board/fvp_r/fvp_r_misc_helpers.S b/plat/arm/board/fvp_r/fvp_r_misc_helpers.S new file mode 100644 index 0000000..67ad164 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_misc_helpers.S @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + + .globl disable_mpu_el2 + .globl disable_mpu_icache_el2 + +/* --------------------------------------------------------------------------- + * Disable the MPU at EL2. + * --------------------------------------------------------------------------- + */ + +func disable_mpu_el2 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) +do_disable_mpu_el2: + mrs x0, sctlr_el2 + bic x0, x0, x1 + msr sctlr_el2, x0 + isb /* ensure MMU is off */ + dsb sy + ret +endfunc disable_mpu_el2 + + +func disable_mpu_icache_el2 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) + b do_disable_mpu_el2 +endfunc disable_mpu_icache_el2 diff --git a/plat/arm/board/fvp_r/fvp_r_private.h b/plat/arm/board/fvp_r/fvp_r_private.h new file mode 100644 index 0000000..48f6e89 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_private.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_R_PRIVATE_H +#define FVP_R_PRIVATE_H + +#include + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ + +void fvp_config_setup(void); + +void fvp_interconnect_init(void); +void fvp_interconnect_enable(void); +void fvp_interconnect_disable(void); +void fvp_timer_init(void); + +#endif /* FVP_R_PRIVATE_H */ diff --git a/plat/arm/board/fvp_r/fvp_r_stack_protector.c b/plat/arm/board/fvp_r/fvp_r_stack_protector.c new file mode 100644 index 0000000..69b6312 --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_stack_protector.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#define RANDOM_CANARY_VALUE ((u_register_t) 8092347823957523895ULL) + +u_register_t plat_get_stack_protector_canary(void) +{ + /* + * Ideally, a random number should be returned instead of the + * combination of a timer's value and a compile-time constant. As the + * FVP_R does not have any random number generator, this is better than + * nothing but not necessarily really secure. + */ + return RANDOM_CANARY_VALUE ^ read_cntpct_el0(); +} + diff --git a/plat/arm/board/fvp_r/fvp_r_trusted_boot.c b/plat/arm/board/fvp_r/fvp_r_trusted_boot.c new file mode 100644 index 0000000..de0b28f --- /dev/null +++ b/plat/arm/board/fvp_r/fvp_r_trusted_boot.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + + +/* + * Return the ROTPK hash in the following ASN.1 structure in DER format: + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + */ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + return arm_get_rotpk_info(cookie, key_ptr, key_len, flags); +} + +/* + * Store a new non-volatile counter value. + * + * On some FVP_R versions, the non-volatile counters are read-only so this + * function will always fail. + * + * Return: 0 = success, Otherwise = error + */ +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + const char *oid; + uintptr_t nv_ctr_addr; + + assert(cookie != NULL); + + oid = (const char *)cookie; + if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { + nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr, + TRUSTED_NV_CTR_ID); + } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { + nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr, + NON_TRUSTED_NV_CTR_ID); + } else { + return 1; + } + + mmio_write_32(nv_ctr_addr, nv_ctr); + + /* + * If the FVP_R models a locked counter then its value cannot be updated + * and the above write operation has been silently ignored. + */ + return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1; +} diff --git a/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h b/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h new file mode 100644 index 0000000..92bf484 --- /dev/null +++ b/plat/arm/board/fvp_r/include/fvp_r_arch_helpers.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_R_ARCH_HELPERS_H +#define FVP_R_ARCH_HELPERS_H + +#include + +/******************************************************************************* + * MPU register definitions + ******************************************************************************/ +#define MPUIR_EL2 S3_4_C0_C0_4 +#define PRBAR_EL2 S3_4_C6_C8_0 +#define PRLAR_EL2 S3_4_C6_C8_1 +#define PRSELR_EL2 S3_4_C6_C2_1 +#define PRENR_EL2 S3_4_C6_C1_1 + +/* v8-R64 MPU registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(mpuir_el2, MPUIR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(prenr_el2, PRENR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(prselr_el2, PRSELR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(prbar_el2, PRBAR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(prlar_el2, PRLAR_EL2) + +#endif /* FVP_R_ARCH_HELPERS_H */ diff --git a/plat/arm/board/fvp_r/include/platform_def.h b/plat/arm/board/fvp_r/include/platform_def.h new file mode 100644 index 0000000..ea3a258 --- /dev/null +++ b/plat/arm/board/fvp_r/include/platform_def.h @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_R_PLATFORM_DEF_H +#define FVP_R_PLATFORM_DEF_H + +#define PLAT_V2M_OFFSET 0x80000000 + +#define BL33_IMAGE_DESC { \ + .image_id = BL33_IMAGE_ID, \ + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ + VERSION_2, image_info_t, 0), \ + .image_info.image_base = PLAT_ARM_DRAM1_BASE + 0x1000, \ + .image_info.image_max_size = UL(0x3ffff000), \ + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ + .ep_info.pc = PLAT_ARM_DRAM1_BASE + 0x1000, \ + .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), \ +} + +#include "../fvp_r_def.h" +#include +#include +#include + +/* These are referenced by arm_def.h #included next, so #define first. */ +#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x80000000) +#define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x84000000) +#define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x86000000) +#define PLAT_ARM_DRAM1_BASE ULL(0x0) +#define PLAT_ARM_DRAM2_BASE ULL(0x080000000) + +#define PLAT_HW_CONFIG_DTB_BASE ULL(0x12000000) +#define PLAT_ARM_SYS_CNTCTL_BASE UL(0xaa430000) +#define PLAT_ARM_SYS_CNTREAD_BASE UL(0xaa800000) +#define PLAT_ARM_SYS_TIMCTL_BASE UL(0xaa810000) +#define PLAT_ARM_SYS_CNT_BASE_S UL(0xaa820000) +#define PLAT_ARM_SYS_CNT_BASE_NS UL(0xaa830000) +#define PLAT_ARM_SP805_TWDG_BASE UL(0xaa490000) + +#include +#include + + +/* Required to create plat_regions: */ +#define MIN_LVL_BLOCK_DESC U(1) + +/* Required platform porting definitions */ +#define PLATFORM_CORE_COUNT (U(FVP_R_CLUSTER_COUNT) * \ + U(FVP_R_MAX_CPUS_PER_CLUSTER) * \ + U(FVP_R_MAX_PE_PER_CPU)) + +#define PLAT_NUM_PWR_DOMAINS (U(FVP_R_CLUSTER_COUNT) + \ + PLATFORM_CORE_COUNT + U(1)) + +#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 + +/* + * Other platform porting definitions are provided by included headers + */ + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER_COUNT U(FVP_R_CLUSTER_COUNT) +#define PLAT_ARM_DRAM1_SIZE ULL(0x7fffffff) +#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ +#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ +#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ + +/* These two are defined thus in arm_def.h, but doesn't seem to see it... */ +#define PLAT_BL1_RO_LIMIT (BL1_RO_BASE \ + + PLAT_ARM_TRUSTED_ROM_SIZE) + +#define PLAT_ARM_SYS_CNTCTL_BASE UL(0xaa430000) +#define PLAT_ARM_SYS_CNTREAD_BASE UL(0xaa800000) +#define PLAT_ARM_SYS_TIMCTL_BASE UL(0xaa810000) +#define PLAT_ARM_SYS_CNT_BASE_S UL(0xaa820000) +#define PLAT_ARM_SYS_CNT_BASE_NS UL(0xaa830000) +#define PLAT_ARM_SP805_TWDG_BASE UL(0xaa490000) + +/* virtual address used by dynamic mem_protect for chunk_base */ +#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) + +/* No SCP in FVP_R */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) + +#define PLAT_ARM_DRAM2_SIZE UL(0x80000000) + +#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) + +#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ + PLAT_HW_CONFIG_DTB_BASE, \ + PLAT_HW_CONFIG_DTB_SIZE, \ + MT_MEMORY | MT_RO | MT_NS) + +#define V2M_FVP_R_SYSREGS_BASE UL(0x9c010000) + +/* + * Load address of BL33 for this platform port, + * U-Boot specifically must be loaded at a 4K aligned address. + */ +#define PLAT_ARM_NS_IMAGE_BASE (PLAT_ARM_DRAM1_BASE + 0x1000) + +/* + * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if !USE_ROMLIB +# define PLAT_ARM_MMAP_ENTRIES 11 +# define MAX_XLAT_TABLES 5 +#else +# define PLAT_ARM_MMAP_ENTRIES 12 +# define MAX_XLAT_TABLES 6 +#endif +# define N_MPU_REGIONS 16 /* number of MPU regions */ +# define ALL_MPU_EL2_REGIONS_USED 0xffffffff + /* this is the PRENR_EL2 value if all MPU regions are in use */ + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) + +/* + * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page + */ + +#if USE_ROMLIB +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) +#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0x6000) +#else +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) +#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0) +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#if COT_DESC_IN_DTB +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_R_BL2_ROMLIB_OPTIMIZATION) +#else +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_R_BL2_ROMLIB_OPTIMIZATION) +#endif +#else +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_R_BL2_ROMLIB_OPTIMIZATION) +#endif + +/* + * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is + * calculated using the current BL31 PROGBITS debug size plus the sizes of + * BL2 and BL1-RW + */ +#define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) + +/* + * Size of cacheable stacks + */ +#if defined(IMAGE_BL1) +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE UL(0x1000) +# else +# define PLATFORM_STACK_SIZE UL(0x500) +# endif +#endif + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* + * These nominally reserve the last block of flash for PSCI MEM PROTECT flag, + * but no PSCI in FVP_R platform, so reserve nothing: + */ +#define PLAT_ARM_FLASH_IMAGE_BASE (PLAT_ARM_DRAM1_BASE + UL(0x40000000)) +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (PLAT_ARM_DRAM1_SIZE - UL(0x40000000)) + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +/* + * PL011 related constants + */ +#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ + +#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ + +#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE +#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ + +/* CCI related constants */ +#define PLAT_FVP_R_CCI400_BASE UL(0xac090000) +#define PLAT_FVP_R_CCI400_CLUS0_SL_PORT 3 +#define PLAT_FVP_R_CCI400_CLUS1_SL_PORT 4 + +/* CCI-500/CCI-550 on Base platform */ +#define PLAT_FVP_R_CCI5XX_BASE UL(0xaa000000) +#define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT 5 +#define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT 6 + +/* System timer related constants */ +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +/* Mailbox base address */ +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE + + +/* TrustZone controller related constants + * + * Currently only filters 0 and 2 are connected on Base FVP_R. + * Filter 0 : CPU clusters (no access to DRAM by default) + * Filter 1 : not connected + * Filter 2 : LCDs (access to VRAM allowed by default) + * Filter 3 : not connected + * Programming unconnected filters will have no effect at the + * moment. These filter could, however, be connected in future. + * So care should be taken not to configure the unused filters. + * + * Allow only non-secure access to all DRAM to supported devices. + * Give access to the CPUs and Virtio. Some devices + * would normally use the default ID so allow that too. + */ +#define PLAT_ARM_TZC_BASE UL(0xaa4a0000) +#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) + +#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ + TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_DEFAULT) | \ + TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_PCI) | \ + TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_AP) | \ + TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO) | \ + TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO_OLD)) + +/* + * GIC related constants to cater for both GICv2 and GICv3 instances of an + * FVP_R. They could be overridden at runtime in case the FVP_R implements the + * legacy VE memory map. + */ +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICR_BASE BASE_GICR_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ + PLAT_SP_IMAGE_NS_BUF_SIZE) + +#define PLAT_SP_PRI PLAT_RAS_PRI + +/* + * Physical and virtual address space limits for MPU in AARCH64 & AARCH32 modes + */ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) + +#define ARM_SOC_CONTINUATION_SHIFT U(24) +#define ARM_SOC_IDENTIFICATION_SHIFT U(16) + +#endif /* FVP_R_PLATFORM_DEF_H */ diff --git a/plat/arm/board/fvp_r/platform.mk b/plat/arm/board/fvp_r/platform.mk new file mode 100644 index 0000000..93b5cf2 --- /dev/null +++ b/plat/arm/board/fvp_r/platform.mk @@ -0,0 +1,99 @@ +# +# Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Only aarch64 ARCH supported for FVP_R +ARCH := aarch64 + +# Override to exclude BL2, BL2U, BL31, and BL33 for FVP_R +override NEED_BL2 := no +override NEED_BL2U := no +override NEED_BL31 := no +NEED_BL32 := no + +override CTX_INCLUDE_AARCH32_REGS := 0 + +# Use MPU-based memory management: +XLAT_MPU_LIB_V1 := 1 + +# FVP R will not have more than 2 clusters so just use CCI interconnect +FVP_R_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c + + +include plat/arm/board/common/board_common.mk +include plat/arm/common/arm_common.mk + +PLAT_INCLUDES := -Iplat/arm/board/fvp_r/include + +FVP_R_BL_COMMON_SOURCES := plat/arm/board/fvp_r/fvp_r_common.c \ + plat/arm/board/fvp_r/fvp_r_context_mgmt.c \ + plat/arm/board/fvp_r/fvp_r_debug.S \ + plat/arm/board/fvp_r/fvp_r_err.c \ + plat/arm/board/fvp_r/fvp_r_helpers.S \ + plat/arm/board/fvp_r/fvp_r_misc_helpers.S + +FVP_R_BL1_SOURCES := plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c \ + plat/arm/board/fvp_r/fvp_r_bl1_setup.c \ + plat/arm/board/fvp_r/fvp_r_io_storage.c \ + plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S \ + plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S \ + plat/arm/board/fvp_r/fvp_r_bl1_main.c + +FVP_R_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S + +FVP_R_DYNC_CFG_SOURCES := common/fdt_wrappers.c \ + plat/arm/common/arm_dyn_cfg.c + +ifeq (${TRUSTED_BOARD_BOOT},1) +FVP_R_AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + lib/fconf/fconf_tbbr_getter.c \ + plat/common/tbbr/plat_tbbr.c \ + drivers/auth/tbbr/tbbr_cot_bl1_r64.c \ + drivers/auth/tbbr/tbbr_cot_common.c \ + plat/arm/board/common/board_arm_trusted_boot.c \ + plat/arm/board/common/rotpk/arm_dev_rotpk.S \ + plat/arm/board/fvp_r/fvp_r_trusted_boot.c + +FVP_R_BL1_SOURCES += ${MBEDTLS_SOURCES} \ + ${FVP_R_AUTH_SOURCES} +endif + +ifeq (${USE_SP804_TIMER},1) +FVP_R_BL_COMMON_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +else +FVP_R_BL_COMMON_SOURCES += drivers/delay_timer/generic_delay_timer.c +endif + +# Enable Activity Monitor Unit extensions by default +ENABLE_AMU := 1 + +ifneq (${ENABLE_STACK_PROTECTOR},0) +FVP_R_BL_COMMON_SOURCES += plat/arm/board/fvp_r/fvp_r_stack_protector.c +endif + +override BL1_SOURCES := drivers/arm/sp805/sp805.c \ + drivers/cfi/v2m/v2m_flash.c \ + drivers/delay_timer/delay_timer.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + drivers/io/io_semihosting.c \ + lib/cpus/aarch64/cpu_helpers.S \ + lib/fconf/fconf_dyn_cfg_getter.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + plat/arm/common/arm_bl1_setup.c \ + plat/arm/common/arm_err.c \ + plat/arm/common/arm_io_storage.c \ + plat/arm/common/fconf/arm_fconf_io.c \ + plat/common/plat_bl1_common.c \ + plat/common/aarch64/platform_up_stack.S \ + ${FVP_R_BL1_SOURCES} \ + ${FVP_R_BL_COMMON_SOURCES} \ + ${FVP_R_CPU_LIBS} \ + ${FVP_R_DYNC_CFG_SOURCES} \ + ${FVP_R_INTERCONNECT_SOURCES} -- cgit v1.2.3