From 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 28 Apr 2024 11:13:47 +0200 Subject: Adding upstream version 2.8.0+dfsg. Signed-off-by: Daniel Baumann --- plat/imx/imx8m/imx8m_caam.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 plat/imx/imx8m/imx8m_caam.c (limited to 'plat/imx/imx8m/imx8m_caam.c') diff --git a/plat/imx/imx8m/imx8m_caam.c b/plat/imx/imx8m/imx8m_caam.c new file mode 100644 index 0000000..a491550 --- /dev/null +++ b/plat/imx/imx8m/imx8m_caam.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2019-2022 NXP. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#define HAB_JR0_DID U(0x8011) + +void imx8m_caam_init(void) +{ + uint32_t sm_cmd; + + /* Dealloc part 0 and 2 with current DID */ + sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART); + mmio_write_32(SM_CMD, sm_cmd); + + sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART); + mmio_write_32(SM_CMD, sm_cmd); + + /* config CAAM JRaMID set MID to Cortex A */ + if (mmio_read_32(CAAM_JR0MID) == HAB_JR0_DID) { + NOTICE("Do not release JR0 to NS as it can be used by HAB\n"); + } else { + mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); + } + + mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); + mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); + + /* Alloc partition 0 writing SMPO and SMAGs */ + mmio_write_32(SM_P0_PERM, 0xff); + mmio_write_32(SM_P0_SMAG2, 0xffffffff); + mmio_write_32(SM_P0_SMAG1, 0xffffffff); + + /* Allocate page 0 and 1 to partition 0 with DID set */ + sm_cmd = (0 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT | + SMC_CMD_ALLOC_PAGE); + mmio_write_32(SM_CMD, sm_cmd); + + sm_cmd = (1 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT | + SMC_CMD_ALLOC_PAGE); + mmio_write_32(SM_CMD, sm_cmd); +} -- cgit v1.2.3