From 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 28 Apr 2024 11:13:47 +0200 Subject: Adding upstream version 2.8.0+dfsg. Signed-off-by: Daniel Baumann --- plat/intel/soc/common/socfpga_delay_timer.c | 49 +++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 plat/intel/soc/common/socfpga_delay_timer.c (limited to 'plat/intel/soc/common/socfpga_delay_timer.c') diff --git a/plat/intel/soc/common/socfpga_delay_timer.c b/plat/intel/soc/common/socfpga_delay_timer.c new file mode 100644 index 0000000..dcd51e2 --- /dev/null +++ b/plat/intel/soc/common/socfpga_delay_timer.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include "socfpga_plat_def.h" + +#define SOCFPGA_GLOBAL_TIMER 0xffd01000 +#define SOCFPGA_GLOBAL_TIMER_EN 0x3 + +static timer_ops_t plat_timer_ops; +/******************************************************************** + * The timer delay function + ********************************************************************/ +static uint32_t socfpga_get_timer_value(void) +{ + /* + * Generic delay timer implementation expects the timer to be a down + * counter. We apply bitwise NOT operator to the tick values returned + * by read_cntpct_el0() to simulate the down counter. The value is + * clipped from 64 to 32 bits. + */ + return (uint32_t)(~read_cntpct_el0()); +} + +void socfpga_delay_timer_init_args(void) +{ + plat_timer_ops.get_timer_value = socfpga_get_timer_value; + plat_timer_ops.clk_mult = 1; + plat_timer_ops.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ; + + timer_init(&plat_timer_ops); + +} + +void socfpga_delay_timer_init(void) +{ + socfpga_delay_timer_init_args(); + mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN); + + asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN)); + asm volatile("msr cntp_tval_el0, %0" : : "r" (~0)); + +} -- cgit v1.2.3