From 102b0d2daa97dae68d3eed54d8fe37a9cc38a892 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 28 Apr 2024 11:13:47 +0200 Subject: Adding upstream version 2.8.0+dfsg. Signed-off-by: Daniel Baumann --- .../intel/soc/stratix10/include/socfpga_plat_def.h | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 plat/intel/soc/stratix10/include/socfpga_plat_def.h (limited to 'plat/intel/soc/stratix10/include/socfpga_plat_def.h') diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h new file mode 100644 index 0000000..516cc75 --- /dev/null +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 +#define BOOT_SOURCE BOOT_SOURCE_SDMMC + +/* FPGA config helpers */ +#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 +#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000 + +/* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 +#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) + +#define SOCFPGA_MMC_REG_BASE 0xff808000 + +#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 +#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 + +/* Platform specific system counter */ +#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk() + +uint32_t get_cpu_clk(void); + +#endif /* PLATSOCFPGA_DEF_H */ + -- cgit v1.2.3