summaryrefslogtreecommitdiffstats
path: root/lib/cpus/aarch64/cortex_a78.S
blob: dd3487ab6c9f312e9f2d243025def12e69cf74d1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
/*
 * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <cortex_a78.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"

/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif

.globl cortex_a78_reset_func
.globl cortex_a78_core_pwr_dwn

#if WORKAROUND_CVE_2022_23960
	wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
#endif /* WORKAROUND_CVE_2022_23960 */

/* --------------------------------------------------
 * Errata Workaround for A78 Erratum 1688305.
 * This applies to revision r0p0 and r1p0 of A78.
 * Inputs:
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x17
 * --------------------------------------------------
 */
func errata_a78_1688305_wa
	/* Compare x0 against revision r1p0 */
	mov	x17, x30
	bl	check_errata_1688305
	cbz	x0, 1f
	mrs     x1, CORTEX_A78_ACTLR2_EL1
	orr	x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
	msr     CORTEX_A78_ACTLR2_EL1, x1
	isb
1:
	ret	x17
endfunc errata_a78_1688305_wa

func check_errata_1688305
	/* Applies to r0p0 and r1p0 */
	mov	x1, #0x10
	b	cpu_rev_var_ls
endfunc check_errata_1688305

/* --------------------------------------------------
 * Errata Workaround for Cortex A78 Errata #1941498.
 * This applies to revisions r0p0, r1p0, and r1p1.
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x17
 * --------------------------------------------------
 */
func errata_a78_1941498_wa
	/* Compare x0 against revision <= r1p1 */
	mov	x17, x30
	bl	check_errata_1941498
	cbz	x0, 1f

	/* Set bit 8 in ECTLR_EL1 */
	mrs	x1, CORTEX_A78_CPUECTLR_EL1
	orr	x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
	msr	CORTEX_A78_CPUECTLR_EL1, x1
	isb
1:
	ret	x17
endfunc errata_a78_1941498_wa

func check_errata_1941498
	/* Check for revision <= r1p1, might need to be updated later. */
	mov	x1, #0x11
	b	cpu_rev_var_ls
endfunc check_errata_1941498

/* --------------------------------------------------
 * Errata Workaround for A78 Erratum 1951500.
 * This applies to revisions r1p0 and r1p1 of A78.
 * The issue also exists in r0p0 but there is no fix
 * in that revision.
 * Inputs:
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x17
 * --------------------------------------------------
 */
func errata_a78_1951500_wa
	/* Compare x0 against revisions r1p0 - r1p1 */
	mov	x17, x30
	bl	check_errata_1951500
	cbz	x0, 1f

	msr	S3_6_c15_c8_0, xzr
	ldr	x0, =0x10E3900002
	msr	S3_6_c15_c8_2, x0
	ldr	x0, =0x10FFF00083
	msr	S3_6_c15_c8_3, x0
	ldr	x0, =0x2001003FF
	msr	S3_6_c15_c8_1, x0

	mov	x0, #1
	msr	S3_6_c15_c8_0, x0
	ldr	x0, =0x10E3800082
	msr	S3_6_c15_c8_2, x0
	ldr	x0, =0x10FFF00083
	msr	S3_6_c15_c8_3, x0
	ldr	x0, =0x2001003FF
	msr	S3_6_c15_c8_1, x0

	mov	x0, #2
	msr	S3_6_c15_c8_0, x0
	ldr	x0, =0x10E3800200
	msr	S3_6_c15_c8_2, x0
	ldr	x0, =0x10FFF003E0
	msr	S3_6_c15_c8_3, x0
	ldr	x0, =0x2001003FF
	msr	S3_6_c15_c8_1, x0

	isb
1:
	ret	x17
endfunc errata_a78_1951500_wa

func check_errata_1951500
	/* Applies to revisions r1p0 and r1p1. */
	mov	x1, #CPU_REV(1, 0)
	mov	x2, #CPU_REV(1, 1)
	b	cpu_rev_var_range
endfunc check_errata_1951500

/* --------------------------------------------------
 * Errata Workaround for Cortex A78 Errata #1821534.
 * This applies to revisions r0p0 and r1p0.
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x17
 * --------------------------------------------------
 */
func errata_a78_1821534_wa
	/* Check revision. */
	mov	x17, x30
	bl	check_errata_1821534
	cbz	x0, 1f

	/* Set bit 2 in ACTLR2_EL1 */
	mrs     x1, CORTEX_A78_ACTLR2_EL1
	orr	x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
	msr     CORTEX_A78_ACTLR2_EL1, x1
	isb
1:
	ret	x17
endfunc errata_a78_1821534_wa

func check_errata_1821534
	/* Applies to r0p0 and r1p0 */
	mov	x1, #0x10
	b	cpu_rev_var_ls
endfunc check_errata_1821534

/* --------------------------------------------------
 * Errata Workaround for Cortex A78 Errata 1952683.
 * This applies to revision r0p0.
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x17
 * --------------------------------------------------
 */
func errata_a78_1952683_wa
	/* Check revision. */
	mov	x17, x30
	bl	check_errata_1952683
	cbz	x0, 1f

	ldr	x0,=0x5
	msr	S3_6_c15_c8_0,x0
	ldr	x0,=0xEEE10A10
	msr	S3_6_c15_c8_2,x0
	ldr	x0,=0xFFEF0FFF
	msr	S3_6_c15_c8_3,x0
	ldr	x0,=0x0010F000
	msr	S3_6_c15_c8_4,x0
	ldr	x0,=0x0010F000
	msr	S3_6_c15_c8_5,x0
	ldr	x0,=0x40000080023ff
	msr	S3_6_c15_c8_1,x0
	ldr	x0,=0x6
	msr	S3_6_c15_c8_0,x0
	ldr	x0,=0xEE640F34
	msr	S3_6_c15_c8_2,x0
	ldr	x0,=0xFFEF0FFF
	msr	S3_6_c15_c8_3,x0
	ldr	x0,=0x40000080023ff
	msr	S3_6_c15_c8_1,x0
	isb
1:
	ret	x17
endfunc errata_a78_1952683_wa

func check_errata_1952683
	/* Applies to r0p0 only */
	mov	x1, #0x00
	b	cpu_rev_var_ls
endfunc check_errata_1952683

/* --------------------------------------------------
 * Errata Workaround for Cortex A78 Errata 2132060.
 * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
 * It is still open.
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x1, x17
 * --------------------------------------------------
 */
func errata_a78_2132060_wa
	/* Check revision. */
	mov	x17, x30
	bl	check_errata_2132060
	cbz	x0, 1f

	/* Apply the workaround. */
	mrs	x1, CORTEX_A78_CPUECTLR_EL1
	mov	x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
	bfi	x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
	msr	CORTEX_A78_CPUECTLR_EL1, x1
1:
	ret	x17
endfunc errata_a78_2132060_wa

func check_errata_2132060
	/* Applies to r0p0, r0p1, r1p1, and r1p2 */
	mov	x1, #0x12
	b	cpu_rev_var_ls
endfunc check_errata_2132060

/* --------------------------------------------------------------------
 * Errata Workaround for A78 Erratum 2242635.
 * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
 * processor and is still open.
 * The issue also exists in r0p0 but there is no fix in that revision.
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x17
 * --------------------------------------------------------------------
 */
func errata_a78_2242635_wa
	/* Compare x0 against revisions r1p0 - r1p2 */
	mov	x17, x30
	bl	check_errata_2242635
	cbz	x0, 1f

	ldr	x0, =0x5
	msr	S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
	ldr	x0, =0x10F600E000
	msr	S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
	ldr	x0, =0x10FF80E000
	msr	S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
	ldr	x0, =0x80000000003FF
	msr	S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */

	isb
1:
	ret	x17
endfunc errata_a78_2242635_wa

func check_errata_2242635
	/* Applies to revisions r1p0 through r1p2. */
	mov	x1, #CPU_REV(1, 0)
	mov	x2, #CPU_REV(1, 2)
	b	cpu_rev_var_range
endfunc check_errata_2242635

/* --------------------------------------------------
 * Errata Workaround for Cortex A78 Errata 2376745.
 * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
 * It is still open.
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x1, x17
 * --------------------------------------------------
 */
func errata_a78_2376745_wa
	/* Check revision. */
	mov	x17, x30
	bl	check_errata_2376745
	cbz	x0, 1f

	/* Apply the workaround. */
	mrs	x1, CORTEX_A78_ACTLR2_EL1
	orr	x1, x1, #BIT(0)
	msr	CORTEX_A78_ACTLR2_EL1, x1
1:
	ret	x17
endfunc errata_a78_2376745_wa

func check_errata_2376745
	/* Applies to r0p0, r0p1, r1p1, and r1p2 */
	mov	x1, #CPU_REV(1, 2)
	b	cpu_rev_var_ls
endfunc check_errata_2376745

/* --------------------------------------------------
 * Errata Workaround for Cortex A78 Errata 2395406.
 * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
 * It is still open.
 * x0: variant[4:7] and revision[0:3] of current cpu.
 * Shall clobber: x0-x1, x17
 * --------------------------------------------------
 */
func errata_a78_2395406_wa
	/* Check revision. */
	mov	x17, x30
	bl	check_errata_2395406
	cbz	x0, 1f

	/* Apply the workaround. */
	mrs	x1, CORTEX_A78_ACTLR2_EL1
	orr	x1, x1, #BIT(40)
	msr	CORTEX_A78_ACTLR2_EL1, x1
1:
	ret	x17
endfunc errata_a78_2395406_wa

func check_errata_2395406
	/* Applies to r0p0, r0p1, r1p1, and r1p2 */
	mov	x1, #CPU_REV(1, 2)
	b	cpu_rev_var_ls
endfunc check_errata_2395406

func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
	mov	x0, #ERRATA_APPLIES
#else
	mov	x0, #ERRATA_MISSING
#endif
	ret
endfunc check_errata_cve_2022_23960

	/* -------------------------------------------------
	 * The CPU Ops reset function for Cortex-A78
	 * -------------------------------------------------
	 */
func cortex_a78_reset_func
	mov	x19, x30
	bl	cpu_get_rev_var
	mov	x18, x0

#if ERRATA_A78_1688305
	mov     x0, x18
	bl	errata_a78_1688305_wa
#endif

#if ERRATA_A78_1941498
	mov     x0, x18
	bl	errata_a78_1941498_wa
#endif

#if ERRATA_A78_1951500
	mov	x0, x18
	bl	errata_a78_1951500_wa
#endif

#if ERRATA_A78_1821534
	mov	x0, x18
	bl	errata_a78_1821534_wa
#endif

#if ERRATA_A78_1952683
	mov	x0, x18
	bl	errata_a78_1952683_wa
#endif

#if ERRATA_A78_2132060
	mov	x0, x18
	bl	errata_a78_2132060_wa
#endif

#if ERRATA_A78_2242635
	mov	x0, x18
	bl	errata_a78_2242635_wa
#endif

#if ERRATA_A78_2376745
	mov	x0, x18
	bl	errata_a78_2376745_wa
#endif

#if ERRATA_A78_2395406
	mov	x0, x18
	bl	errata_a78_2395406_wa
#endif

#if ENABLE_AMU
	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
	mrs	x0, actlr_el3
	bic	x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
	msr	actlr_el3, x0

	/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
	mrs	x0, actlr_el2
	bic	x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
	msr	actlr_el2, x0

	/* Enable group0 counters */
	mov	x0, #CORTEX_A78_AMU_GROUP0_MASK
	msr	CPUAMCNTENSET0_EL0, x0

	/* Enable group1 counters */
	mov	x0, #CORTEX_A78_AMU_GROUP1_MASK
	msr	CPUAMCNTENSET1_EL0, x0
#endif

#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
	/*
	 * The Cortex-A78 generic vectors are overridden to apply errata
	 * mitigation on exception entry from lower ELs.
	 */
	adr	x0, wa_cve_vbar_cortex_a78
	msr	vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */

	isb
	ret	x19
endfunc cortex_a78_reset_func

	/* ---------------------------------------------
	 * HW will do the cache maintenance while powering down
	 * ---------------------------------------------
	 */
func cortex_a78_core_pwr_dwn
	/* ---------------------------------------------
	 * Enable CPU power down bit in power control register
	 * ---------------------------------------------
	 */
	mrs	x0, CORTEX_A78_CPUPWRCTLR_EL1
	orr	x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
	msr	CORTEX_A78_CPUPWRCTLR_EL1, x0
	isb
	ret
endfunc cortex_a78_core_pwr_dwn

	/*
	 * Errata printing function for cortex_a78. Must follow AAPCS.
	 */
#if REPORT_ERRATA
func cortex_a78_errata_report
	stp	x8, x30, [sp, #-16]!

	bl	cpu_get_rev_var
	mov	x8, x0

	/*
	 * Report all errata. The revision-variant information is passed to
	 * checking functions of each errata.
	 */
	report_errata ERRATA_A78_1688305, cortex_a78, 1688305
	report_errata ERRATA_A78_1941498, cortex_a78, 1941498
	report_errata ERRATA_A78_1951500, cortex_a78, 1951500
	report_errata ERRATA_A78_1821534, cortex_a78, 1821534
	report_errata ERRATA_A78_1952683, cortex_a78, 1952683
	report_errata ERRATA_A78_2132060, cortex_a78, 2132060
	report_errata ERRATA_A78_2242635, cortex_a78, 2242635
	report_errata ERRATA_A78_2376745, cortex_a78, 2376745
	report_errata ERRATA_A78_2395406, cortex_a78, 2395406
	report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960

	ldp	x8, x30, [sp], #16
	ret
endfunc cortex_a78_errata_report
#endif

	/* ---------------------------------------------
	 * This function provides cortex_a78 specific
	 * register information for crash reporting.
	 * It needs to return with x6 pointing to
	 * a list of register names in ascii and
	 * x8 - x15 having values of registers to be
	 * reported.
	 * ---------------------------------------------
	 */
.section .rodata.cortex_a78_regs, "aS"
cortex_a78_regs:  /* The ascii list of register names to be reported */
	.asciz	"cpuectlr_el1", ""

func cortex_a78_cpu_reg_dump
	adr	x6, cortex_a78_regs
	mrs	x8, CORTEX_A78_CPUECTLR_EL1
	ret
endfunc cortex_a78_cpu_reg_dump

declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
	cortex_a78_reset_func, \
	cortex_a78_core_pwr_dwn