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/*
* Copyright (c) 2022, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/****************************************************************
* Auto generated by DE, please DO NOT modify this file directly.
*****************************************************************/
#ifndef MT_SPM_PMIC_WRAP_H
#define MT_SPM_PMIC_WRAP_H
enum pmic_wrap_phase_id {
PMIC_WRAP_PHASE_ALLINONE = 0U,
NR_PMIC_WRAP_PHASE = 1U,
};
/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
enum {
CMD_0 = 0U, /* 0x0 */
CMD_1 = 1U, /* 0x1 */
CMD_2 = 2U, /* 0x2 */
CMD_3 = 3U, /* 0x3 */
CMD_4 = 4U, /* 0x4 */
CMD_5 = 5U, /* 0x5 */
CMD_6 = 6U, /* 0x6 */
CMD_7 = 7U, /* 0x7 */
CMD_8 = 8U, /* 0x8 */
NR_IDX_ALL = 9U,
};
/* APIs */
extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx, uint32_t cmd_wdata);
extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
uint32_t idx);
#endif /* MT_SPM_PMIC_WRAP_H */
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