blob: 92c71bcdd30240a6682ec1097796f2a33ed163f1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MTK_PTP3_H
#define MTK_PTP3_H
#include <lib/mmio.h>
#include <lib/utils_def.h>
/************************************************
* BIT Operation and REG r/w
************************************************/
#define ptp3_read(addr) mmio_read_32((uintptr_t)addr)
#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val)
/************************************************
* CPU info
************************************************/
#define NR_PTP3_CFG1_CPU U(8)
#define PTP3_CFG1_CPU_START_ID U(0)
#define PTP3_CFG1_MASK 0x00100000
#define NR_PTP3_CFG2_CPU U(4)
#define PTP3_CFG2_CPU_START_ID U(4)
#define NR_PTP3_CFG3_CPU U(4)
#define PTP3_CFG3_CPU_START_ID U(4)
/************************************************
* config enum
************************************************/
enum PTP3_CFG {
PTP3_CFG_ADDR,
PTP3_CFG_VALUE,
NR_PTP3_CFG,
};
/************************************
* prototype
************************************/
/* init trigger for ptp3 feature */
extern void ptp3_init(unsigned int core);
extern void ptp3_deinit(unsigned int core);
#endif /* MTK_PTP3_H */
|
