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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-29 04:40:20 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-29 04:40:20 +0000 |
commit | 2dba2525fb35dcfc79aad5bdf6c92e790d69635c (patch) | |
tree | ac8ac7d3960922094733bac6d9a5300da7171c56 /doc/man/nvme_register_offsets.2 | |
parent | Initial commit. (diff) | |
download | libnvme-upstream/1.3.tar.xz libnvme-upstream/1.3.zip |
Adding upstream version 1.3.upstream/1.3upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
-rw-r--r-- | doc/man/nvme_register_offsets.2 | 156 |
1 files changed, 156 insertions, 0 deletions
diff --git a/doc/man/nvme_register_offsets.2 b/doc/man/nvme_register_offsets.2 new file mode 100644 index 0000000..17d03b7 --- /dev/null +++ b/doc/man/nvme_register_offsets.2 @@ -0,0 +1,156 @@ +.TH "libnvme" 9 "enum nvme_register_offsets" "January 2023" "API Manual" LINUX +.SH NAME +enum nvme_register_offsets \- controller registers for all transports. This is the layout of BAR0/1 for PCIe, and properties for fabrics. +.SH SYNOPSIS +enum nvme_register_offsets { +.br +.BI " NVME_REG_CAP" +, +.br +.br +.BI " NVME_REG_VS" +, +.br +.br +.BI " NVME_REG_INTMS" +, +.br +.br +.BI " NVME_REG_INTMC" +, +.br +.br +.BI " NVME_REG_CC" +, +.br +.br +.BI " NVME_REG_CSTS" +, +.br +.br +.BI " NVME_REG_NSSR" +, +.br +.br +.BI " NVME_REG_AQA" +, +.br +.br +.BI " NVME_REG_ASQ" +, +.br +.br +.BI " NVME_REG_ACQ" +, +.br +.br +.BI " NVME_REG_CMBLOC" +, +.br +.br +.BI " NVME_REG_CMBSZ" +, +.br +.br +.BI " NVME_REG_BPINFO" +, +.br +.br +.BI " NVME_REG_BPRSEL" +, +.br +.br +.BI " NVME_REG_BPMBL" +, +.br +.br +.BI " NVME_REG_CMBMSC" +, +.br +.br +.BI " NVME_REG_CMBSTS" +, +.br +.br +.BI " NVME_REG_CRTO" +, +.br +.br +.BI " NVME_REG_PMRCAP" +, +.br +.br +.BI " NVME_REG_PMRCTL" +, +.br +.br +.BI " NVME_REG_PMRSTS" +, +.br +.br +.BI " NVME_REG_PMREBS" +, +.br +.br +.BI " NVME_REG_PMRSWTP" +, +.br +.br +.BI " NVME_REG_PMRMSCL" +, +.br +.br +.BI " NVME_REG_PMRMSCU" + +}; +.SH Constants +.IP "NVME_REG_CAP" 12 +Controller Capabilities +.IP "NVME_REG_VS" 12 +Version +.IP "NVME_REG_INTMS" 12 +Interrupt Mask Set +.IP "NVME_REG_INTMC" 12 +Interrupt Mask Clear +.IP "NVME_REG_CC" 12 +Controller Configuration +.IP "NVME_REG_CSTS" 12 +Controller Status +.IP "NVME_REG_NSSR" 12 +NVM Subsystem Reset +.IP "NVME_REG_AQA" 12 +Admin Queue Attributes +.IP "NVME_REG_ASQ" 12 +Admin SQ Base Address +.IP "NVME_REG_ACQ" 12 +Admin CQ Base Address +.IP "NVME_REG_CMBLOC" 12 +Controller Memory Buffer Location +.IP "NVME_REG_CMBSZ" 12 +Controller Memory Buffer Size +.IP "NVME_REG_BPINFO" 12 +Boot Partition Information +.IP "NVME_REG_BPRSEL" 12 +Boot Partition Read Select +.IP "NVME_REG_BPMBL" 12 +Boot Partition Memory Buffer Location +.IP "NVME_REG_CMBMSC" 12 +Controller Memory Buffer Memory Space Control +.IP "NVME_REG_CMBSTS" 12 +Controller Memory Buffer Status +.IP "NVME_REG_CRTO" 12 +Controller Ready Timeouts +.IP "NVME_REG_PMRCAP" 12 +Persistent Memory Capabilities +.IP "NVME_REG_PMRCTL" 12 +Persistent Memory Region Control +.IP "NVME_REG_PMRSTS" 12 +Persistent Memory Region Status +.IP "NVME_REG_PMREBS" 12 +Persistent Memory Region Elasticity Buffer Size +.IP "NVME_REG_PMRSWTP" 12 +Memory Region Sustained Write Throughput +.IP "NVME_REG_PMRMSCL" 12 +Persistent Memory Region Controller Memory Space Control Lower +.IP "NVME_REG_PMRMSCU" 12 +Persistent Memory Region Controller Memory Space Control Upper |