diff options
Diffstat (limited to 'doc/man/nvme_feat.2')
| -rw-r--r-- | doc/man/nvme_feat.2 | 526 |
1 files changed, 526 insertions, 0 deletions
diff --git a/doc/man/nvme_feat.2 b/doc/man/nvme_feat.2 new file mode 100644 index 0000000..8891682 --- /dev/null +++ b/doc/man/nvme_feat.2 @@ -0,0 +1,526 @@ +.TH "libnvme" 9 "enum nvme_feat" "January 2023" "API Manual" LINUX +.SH NAME +enum nvme_feat \- Features Access Shifts/Masks values +.SH SYNOPSIS +enum nvme_feat { +.br +.BI " NVME_FEAT_ARBITRATION_BURST_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ARBITRATION_BURST_MASK" +, +.br +.br +.BI " NVME_FEAT_ARBITRATION_LPW_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ARBITRATION_LPW_MASK" +, +.br +.br +.BI " NVME_FEAT_ARBITRATION_MPW_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ARBITRATION_MPW_MASK" +, +.br +.br +.BI " NVME_FEAT_ARBITRATION_HPW_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ARBITRATION_HPW_MASK" +, +.br +.br +.BI " NVME_FEAT_PWRMGMT_PS_SHIFT" +, +.br +.br +.BI " NVME_FEAT_PWRMGMT_PS_MASK" +, +.br +.br +.BI " NVME_FEAT_PWRMGMT_WH_SHIFT" +, +.br +.br +.BI " NVME_FEAT_PWRMGMT_WH_MASK" +, +.br +.br +.BI " NVME_FEAT_LBAR_NR_SHIFT" +, +.br +.br +.BI " NVME_FEAT_LBAR_NR_MASK" +, +.br +.br +.BI " NVME_FEAT_TT_TMPTH_SHIFT" +, +.br +.br +.BI " NVME_FEAT_TT_TMPTH_MASK" +, +.br +.br +.BI " NVME_FEAT_TT_TMPSEL_SHIFT" +, +.br +.br +.BI " NVME_FEAT_TT_TMPSEL_MASK" +, +.br +.br +.BI " NVME_FEAT_TT_THSEL_SHIFT" +, +.br +.br +.BI " NVME_FEAT_TT_THSEL_MASK" +, +.br +.br +.BI " NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ERROR_RECOVERY_TLER_MASK" +, +.br +.br +.BI " NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ERROR_RECOVERY_DULBE_MASK" +, +.br +.br +.BI " NVME_FEAT_VWC_WCE_SHIFT" +, +.br +.br +.BI " NVME_FEAT_VWC_WCE_MASK" +, +.br +.br +.BI " NVME_FEAT_NRQS_NSQR_SHIFT" +, +.br +.br +.BI " NVME_FEAT_NRQS_NSQR_MASK" +, +.br +.br +.BI " NVME_FEAT_NRQS_NCQR_SHIFT" +, +.br +.br +.BI " NVME_FEAT_NRQS_NCQR_MASK" +, +.br +.br +.BI " NVME_FEAT_IRQC_THR_SHIFT" +, +.br +.br +.BI " NVME_FEAT_IRQC_THR_MASK" +, +.br +.br +.BI " NVME_FEAT_IRQC_TIME_SHIFT" +, +.br +.br +.BI " NVME_FEAT_IRQC_TIME_MASK" +, +.br +.br +.BI " NVME_FEAT_ICFG_IV_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ICFG_IV_MASK" +, +.br +.br +.BI " NVME_FEAT_ICFG_CD_SHIFT" +, +.br +.br +.BI " NVME_FEAT_ICFG_CD_MASK" +, +.br +.br +.BI " NVME_FEAT_WA_DN_SHIFT" +, +.br +.br +.BI " NVME_FEAT_WA_DN_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_SMART_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_SMART_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_NAN_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_NAN_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_FW_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_FW_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_TELEM_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_TELEM_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_ANA_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_ANA_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_PLA_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_PLA_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_LBAS_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_LBAS_MASK" +, +.br +.br +.BI " NVME_FEAT_AE_EGA_SHIFT" +, +.br +.br +.BI " NVME_FEAT_AE_EGA_MASK" +, +.br +.br +.BI " NVME_FEAT_APST_APSTE_SHIFT" +, +.br +.br +.BI " NVME_FEAT_APST_APSTE_MASK" +, +.br +.br +.BI " NVME_FEAT_HMEM_EHM_SHIFT" +, +.br +.br +.BI " NVME_FEAT_HMEM_EHM_MASK" +, +.br +.br +.BI " NVME_FEAT_HCTM_TMT2_SHIFT" +, +.br +.br +.BI " NVME_FEAT_HCTM_TMT2_MASK" +, +.br +.br +.BI " NVME_FEAT_HCTM_TMT1_SHIFT" +, +.br +.br +.BI " NVME_FEAT_HCTM_TMT1_MASK" +, +.br +.br +.BI " NVME_FEAT_NOPS_NOPPME_SHIFT" +, +.br +.br +.BI " NVME_FEAT_NOPS_NOPPME_MASK" +, +.br +.br +.BI " NVME_FEAT_RRL_RRL_SHIFT" +, +.br +.br +.BI " NVME_FEAT_RRL_RRL_MASK" +, +.br +.br +.BI " NVME_FEAT_PLM_PLME_SHIFT" +, +.br +.br +.BI " NVME_FEAT_PLM_PLME_MASK" +, +.br +.br +.BI " NVME_FEAT_PLMW_WS_SHIFT" +, +.br +.br +.BI " NVME_FEAT_PLMW_WS_MASK" +, +.br +.br +.BI " NVME_FEAT_LBAS_LSIRI_SHIFT" +, +.br +.br +.BI " NVME_FEAT_LBAS_LSIRI_MASK" +, +.br +.br +.BI " NVME_FEAT_LBAS_LSIPI_SHIFT" +, +.br +.br +.BI " NVME_FEAT_LBAS_LSIPI_MASK" +, +.br +.br +.BI " NVME_FEAT_SC_NODRM_SHIFT" +, +.br +.br +.BI " NVME_FEAT_SC_NODRM_MASK" +, +.br +.br +.BI " NVME_FEAT_EG_ENDGID_SHIFT" +, +.br +.br +.BI " NVME_FEAT_EG_ENDGID_MASK" +, +.br +.br +.BI " NVME_FEAT_EG_EGCW_SHIFT" +, +.br +.br +.BI " NVME_FEAT_EG_EGCW_MASK" +, +.br +.br +.BI " NVME_FEAT_SPM_PBSLC_SHIFT" +, +.br +.br +.BI " NVME_FEAT_SPM_PBSLC_MASK" +, +.br +.br +.BI " NVME_FEAT_HOSTID_EXHID_SHIFT" +, +.br +.br +.BI " NVME_FEAT_HOSTID_EXHID_MASK" +, +.br +.br +.BI " NVME_FEAT_RM_REGPRE_SHIFT" +, +.br +.br +.BI " NVME_FEAT_RM_REGPRE_MASK" +, +.br +.br +.BI " NVME_FEAT_RM_RESREL_SHIFT" +, +.br +.br +.BI " NVME_FEAT_RM_RESREL_MASK" +, +.br +.br +.BI " NVME_FEAT_RM_RESPRE_SHIFT" +, +.br +.br +.BI " NVME_FEAT_RM_RESPRE_MASK" +, +.br +.br +.BI " NVME_FEAT_RP_PTPL_SHIFT" +, +.br +.br +.BI " NVME_FEAT_RP_PTPL_MASK" +, +.br +.br +.BI " NVME_FEAT_WP_WPS_SHIFT" +, +.br +.br +.BI " NVME_FEAT_WP_WPS_MASK" +, +.br +.br +.BI " NVME_FEAT_IOCSP_IOCSCI_SHIFT" +, +.br +.br +.BI " NVME_FEAT_IOCSP_IOCSCI_MASK" +, +.br +.br +.BI " NVME_FEAT_FDP_ENABLED_SHIFT" +, +.br +.br +.BI " NVME_FEAT_FDP_ENABLED_MASK" +, +.br +.br +.BI " NVME_FEAT_FDP_INDEX_SHIFT" +, +.br +.br +.BI " NVME_FEAT_FDP_INDEX_MASK" +, +.br +.br +.BI " NVME_FEAT_FDP_EVENTS_ENABLE_SHIFT" +, +.br +.br +.BI " NVME_FEAT_FDP_EVENTS_ENABLE_MASK" + +}; +.SH Constants +.IP "NVME_FEAT_ARBITRATION_BURST_SHIFT" 12 +.IP "NVME_FEAT_ARBITRATION_BURST_MASK" 12 +.IP "NVME_FEAT_ARBITRATION_LPW_SHIFT" 12 +.IP "NVME_FEAT_ARBITRATION_LPW_MASK" 12 +.IP "NVME_FEAT_ARBITRATION_MPW_SHIFT" 12 +.IP "NVME_FEAT_ARBITRATION_MPW_MASK" 12 +.IP "NVME_FEAT_ARBITRATION_HPW_SHIFT" 12 +.IP "NVME_FEAT_ARBITRATION_HPW_MASK" 12 +.IP "NVME_FEAT_PWRMGMT_PS_SHIFT" 12 +.IP "NVME_FEAT_PWRMGMT_PS_MASK" 12 +.IP "NVME_FEAT_PWRMGMT_WH_SHIFT" 12 +.IP "NVME_FEAT_PWRMGMT_WH_MASK" 12 +.IP "NVME_FEAT_LBAR_NR_SHIFT" 12 +.IP "NVME_FEAT_LBAR_NR_MASK" 12 +.IP "NVME_FEAT_TT_TMPTH_SHIFT" 12 +.IP "NVME_FEAT_TT_TMPTH_MASK" 12 +.IP "NVME_FEAT_TT_TMPSEL_SHIFT" 12 +.IP "NVME_FEAT_TT_TMPSEL_MASK" 12 +.IP "NVME_FEAT_TT_THSEL_SHIFT" 12 +.IP "NVME_FEAT_TT_THSEL_MASK" 12 +.IP "NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT" 12 +.IP "NVME_FEAT_ERROR_RECOVERY_TLER_MASK" 12 +.IP "NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT" 12 +.IP "NVME_FEAT_ERROR_RECOVERY_DULBE_MASK" 12 +.IP "NVME_FEAT_VWC_WCE_SHIFT" 12 +.IP "NVME_FEAT_VWC_WCE_MASK" 12 +.IP "NVME_FEAT_NRQS_NSQR_SHIFT" 12 +.IP "NVME_FEAT_NRQS_NSQR_MASK" 12 +.IP "NVME_FEAT_NRQS_NCQR_SHIFT" 12 +.IP "NVME_FEAT_NRQS_NCQR_MASK" 12 +.IP "NVME_FEAT_IRQC_THR_SHIFT" 12 +.IP "NVME_FEAT_IRQC_THR_MASK" 12 +.IP "NVME_FEAT_IRQC_TIME_SHIFT" 12 +.IP "NVME_FEAT_IRQC_TIME_MASK" 12 +.IP "NVME_FEAT_ICFG_IV_SHIFT" 12 +.IP "NVME_FEAT_ICFG_IV_MASK" 12 +.IP "NVME_FEAT_ICFG_CD_SHIFT" 12 +.IP "NVME_FEAT_ICFG_CD_MASK" 12 +.IP "NVME_FEAT_WA_DN_SHIFT" 12 +.IP "NVME_FEAT_WA_DN_MASK" 12 +.IP "NVME_FEAT_AE_SMART_SHIFT" 12 +.IP "NVME_FEAT_AE_SMART_MASK" 12 +.IP "NVME_FEAT_AE_NAN_SHIFT" 12 +.IP "NVME_FEAT_AE_NAN_MASK" 12 +.IP "NVME_FEAT_AE_FW_SHIFT" 12 +.IP "NVME_FEAT_AE_FW_MASK" 12 +.IP "NVME_FEAT_AE_TELEM_SHIFT" 12 +.IP "NVME_FEAT_AE_TELEM_MASK" 12 +.IP "NVME_FEAT_AE_ANA_SHIFT" 12 +.IP "NVME_FEAT_AE_ANA_MASK" 12 +.IP "NVME_FEAT_AE_PLA_SHIFT" 12 +.IP "NVME_FEAT_AE_PLA_MASK" 12 +.IP "NVME_FEAT_AE_LBAS_SHIFT" 12 +.IP "NVME_FEAT_AE_LBAS_MASK" 12 +.IP "NVME_FEAT_AE_EGA_SHIFT" 12 +.IP "NVME_FEAT_AE_EGA_MASK" 12 +.IP "NVME_FEAT_APST_APSTE_SHIFT" 12 +.IP "NVME_FEAT_APST_APSTE_MASK" 12 +.IP "NVME_FEAT_HMEM_EHM_SHIFT" 12 +.IP "NVME_FEAT_HMEM_EHM_MASK" 12 +.IP "NVME_FEAT_HCTM_TMT2_SHIFT" 12 +.IP "NVME_FEAT_HCTM_TMT2_MASK" 12 +.IP "NVME_FEAT_HCTM_TMT1_SHIFT" 12 +.IP "NVME_FEAT_HCTM_TMT1_MASK" 12 +.IP "NVME_FEAT_NOPS_NOPPME_SHIFT" 12 +.IP "NVME_FEAT_NOPS_NOPPME_MASK" 12 +.IP "NVME_FEAT_RRL_RRL_SHIFT" 12 +.IP "NVME_FEAT_RRL_RRL_MASK" 12 +.IP "NVME_FEAT_PLM_PLME_SHIFT" 12 +.IP "NVME_FEAT_PLM_PLME_MASK" 12 +.IP "NVME_FEAT_PLMW_WS_SHIFT" 12 +.IP "NVME_FEAT_PLMW_WS_MASK" 12 +.IP "NVME_FEAT_LBAS_LSIRI_SHIFT" 12 +.IP "NVME_FEAT_LBAS_LSIRI_MASK" 12 +.IP "NVME_FEAT_LBAS_LSIPI_SHIFT" 12 +.IP "NVME_FEAT_LBAS_LSIPI_MASK" 12 +.IP "NVME_FEAT_SC_NODRM_SHIFT" 12 +.IP "NVME_FEAT_SC_NODRM_MASK" 12 +.IP "NVME_FEAT_EG_ENDGID_SHIFT" 12 +.IP "NVME_FEAT_EG_ENDGID_MASK" 12 +.IP "NVME_FEAT_EG_EGCW_SHIFT" 12 +.IP "NVME_FEAT_EG_EGCW_MASK" 12 +.IP "NVME_FEAT_SPM_PBSLC_SHIFT" 12 +.IP "NVME_FEAT_SPM_PBSLC_MASK" 12 +.IP "NVME_FEAT_HOSTID_EXHID_SHIFT" 12 +.IP "NVME_FEAT_HOSTID_EXHID_MASK" 12 +.IP "NVME_FEAT_RM_REGPRE_SHIFT" 12 +.IP "NVME_FEAT_RM_REGPRE_MASK" 12 +.IP "NVME_FEAT_RM_RESREL_SHIFT" 12 +.IP "NVME_FEAT_RM_RESREL_MASK" 12 +.IP "NVME_FEAT_RM_RESPRE_SHIFT" 12 +.IP "NVME_FEAT_RM_RESPRE_MASK" 12 +.IP "NVME_FEAT_RP_PTPL_SHIFT" 12 +.IP "NVME_FEAT_RP_PTPL_MASK" 12 +.IP "NVME_FEAT_WP_WPS_SHIFT" 12 +.IP "NVME_FEAT_WP_WPS_MASK" 12 +.IP "NVME_FEAT_IOCSP_IOCSCI_SHIFT" 12 +.IP "NVME_FEAT_IOCSP_IOCSCI_MASK" 12 +.IP "NVME_FEAT_FDP_ENABLED_SHIFT" 12 +.IP "NVME_FEAT_FDP_ENABLED_MASK" 12 +.IP "NVME_FEAT_FDP_INDEX_SHIFT" 12 +.IP "NVME_FEAT_FDP_INDEX_MASK" 12 +.IP "NVME_FEAT_FDP_EVENTS_ENABLE_SHIFT" 12 +.IP "NVME_FEAT_FDP_EVENTS_ENABLE_MASK" 12 |