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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-04 10:10:17 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-04 10:10:17 +0000 |
| commit | 9db5397d87fc212863d4750c85ff8b9a6ed42b95 (patch) | |
| tree | 1bd4e8854203c575eabaa99e2c509f8886065733 /arch/x86/include/asm/msr-index.h | |
| parent | Adding upstream version 6.1.76. (diff) | |
| download | linux-upstream/6.1.82.tar.xz linux-upstream/6.1.82.zip | |
Adding upstream version 6.1.82.upstream/6.1.82
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ec955ab2f..005e41dc7 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -168,6 +168,14 @@ * CPU is not vulnerable to Gather * Data Sampling (GDS). */ +#define ARCH_CAP_RFDS_NO BIT(27) /* + * Not susceptible to Register + * File Data Sampling. + */ +#define ARCH_CAP_RFDS_CLEAR BIT(28) /* + * VERW clears CPU Register + * File. + */ #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* * IA32_XAPIC_DISABLE_STATUS MSR |