diff options
Diffstat (limited to 'arch/arm/mach-s5pv210')
| -rw-r--r-- | arch/arm/mach-s5pv210/Kconfig | 30 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv210/Makefile | 7 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv210/common.h | 19 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv210/pm.c | 214 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv210/regs-clock.h | 196 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv210/s5pv210.c | 71 | ||||
| -rw-r--r-- | arch/arm/mach-s5pv210/sleep.S | 32 |
7 files changed, 569 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig new file mode 100644 index 000000000..055de578b --- /dev/null +++ b/arch/arm/mach-s5pv210/Kconfig @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ + +# Configuration options for the S5PV210/S5PC110 + +config ARCH_S5PV210 + bool "Samsung S5PV210/S5PC110" + depends on ARCH_MULTI_V7 + select ARM_VIC + select CLKSRC_SAMSUNG_PWM + select COMMON_CLK_SAMSUNG + select GPIOLIB + select PINCTRL + select PINCTRL_EXYNOS + select SOC_SAMSUNG + help + Samsung S5PV210/S5PC110 series based systems + +if ARCH_S5PV210 + +config CPU_S5PV210 + def_bool y + select ARM_AMBA + select PL330_DMA if DMADEVICES + help + Enable S5PV210 CPU support + +endif diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile new file mode 100644 index 000000000..aa0a1f091 --- /dev/null +++ b/arch/arm/mach-s5pv210/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ + +obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o +obj-y += s5pv210.o diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h new file mode 100644 index 000000000..cb36058bc --- /dev/null +++ b/arch/arm/mach-s5pv210/common.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Common Header for S5PV210 machines + */ + +#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H +#define __ARCH_ARM_MACH_S5PV210_COMMON_H + +#ifdef CONFIG_PM_SLEEP +void s5pv210_cpu_resume(void); +void s5pv210_pm_init(void); +#else +static inline void s5pv210_pm_init(void) {} +#endif + +#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */ diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c new file mode 100644 index 000000000..d59c094cd --- /dev/null +++ b/arch/arm/mach-s5pv210/pm.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2010-2014 Samsung Electronics Co., Ltd. +// http://www.samsung.com +// +// S5PV210 - Power Management support +// +// Based on arch/arm/mach-s3c2410/pm.c +// Copyright (c) 2006 Simtec Electronics +// Ben Dooks <ben@simtec.co.uk> + +#include <linux/init.h> +#include <linux/suspend.h> +#include <linux/syscore_ops.h> +#include <linux/io.h> +#include <linux/soc/samsung/s3c-pm.h> + +#include <asm/cacheflush.h> +#include <asm/suspend.h> + +#include "common.h" +#include "regs-clock.h" + +/* helper functions to save and restore register state */ +struct sleep_save { + void __iomem *reg; + unsigned long val; +}; + +#define SAVE_ITEM(x) \ + { .reg = (x) } + +/** + * s3c_pm_do_save() - save a set of registers for restoration on resume. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Run through the list of registers given, saving their contents in the + * array for later restoration when we wakeup. + */ +static void s3c_pm_do_save(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + ptr->val = readl_relaxed(ptr->reg); + S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); + } +} + +/** + * s3c_pm_do_restore() - restore register values from the save list. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Restore the register values saved from s3c_pm_do_save(). + * + * WARNING: Do not put any debug in here that may effect memory or use + * peripherals, as things may be changing! +*/ + +static void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) + writel_relaxed(ptr->val, ptr->reg); +} + +static struct sleep_save s5pv210_core_save[] = { + /* Clock ETC */ + SAVE_ITEM(S5P_MDNIE_SEL), +}; + +/* + * VIC wake-up support (TODO) + */ +static u32 s5pv210_irqwake_intmask = 0xffffffff; + +static u32 s5pv210_read_eint_wakeup_mask(void) +{ + return __raw_readl(S5P_EINT_WAKEUP_MASK); +} + +/* + * Suspend helpers. + */ +static int s5pv210_cpu_suspend(unsigned long arg) +{ + unsigned long tmp; + + /* issue the standby signal into the pm unit. Note, we + * issue a write-buffer drain just in case */ + + tmp = 0; + + asm("b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "mcr p15, 0, %0, c7, c10, 5\n\t" + "mcr p15, 0, %0, c7, c10, 4\n\t" + "wfi" : : "r" (tmp)); + + pr_info("Failed to suspend the system\n"); + return 1; /* Aborting suspend */ +} + +static void s5pv210_pm_prepare(void) +{ + unsigned int tmp; + + /* + * Set wake-up mask registers + * S5P_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend. + */ + __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK); + + /* ensure at least INFORM0 has the resume address */ + __raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0); + + tmp = __raw_readl(S5P_SLEEP_CFG); + tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); + __raw_writel(tmp, S5P_SLEEP_CFG); + + /* WFI for SLEEP mode configuration by SYSCON */ + tmp = __raw_readl(S5P_PWR_CFG); + tmp &= S5P_CFG_WFI_CLEAN; + tmp |= S5P_CFG_WFI_SLEEP; + __raw_writel(tmp, S5P_PWR_CFG); + + /* SYSCON interrupt handling disable */ + tmp = __raw_readl(S5P_OTHERS); + tmp |= S5P_OTHER_SYSC_INTOFF; + __raw_writel(tmp, S5P_OTHERS); + + s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); +} + +/* + * Suspend operations. + */ +static int s5pv210_suspend_enter(suspend_state_t state) +{ + u32 eint_wakeup_mask = s5pv210_read_eint_wakeup_mask(); + int ret; + + S3C_PMDBG("%s: suspending the system...\n", __func__); + + S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, + s5pv210_irqwake_intmask, eint_wakeup_mask); + + if (s5pv210_irqwake_intmask == -1U + && eint_wakeup_mask == -1U) { + pr_err("%s: No wake-up sources!\n", __func__); + pr_err("%s: Aborting sleep\n", __func__); + return -EINVAL; + } + + s3c_pm_save_uarts(false); + s5pv210_pm_prepare(); + flush_cache_all(); + s3c_pm_check_store(); + + ret = cpu_suspend(0, s5pv210_cpu_suspend); + if (ret) + return ret; + + s3c_pm_restore_uarts(false); + + S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, + __raw_readl(S5P_WAKEUP_STAT)); + + s3c_pm_check_restore(); + + S3C_PMDBG("%s: resuming the system...\n", __func__); + + return 0; +} + +static int s5pv210_suspend_prepare(void) +{ + s3c_pm_check_prepare(); + + return 0; +} + +static void s5pv210_suspend_finish(void) +{ + s3c_pm_check_cleanup(); +} + +static const struct platform_suspend_ops s5pv210_suspend_ops = { + .enter = s5pv210_suspend_enter, + .prepare = s5pv210_suspend_prepare, + .finish = s5pv210_suspend_finish, + .valid = suspend_valid_only_mem, +}; + +/* + * Syscore operations used to delay restore of certain registers. + */ +static void s5pv210_pm_resume(void) +{ + s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); +} + +static struct syscore_ops s5pv210_pm_syscore_ops = { + .resume = s5pv210_pm_resume, +}; + +/* + * Initialization entry point. + */ +void __init s5pv210_pm_init(void) +{ + register_syscore_ops(&s5pv210_pm_syscore_ops); + suspend_set_ops(&s5pv210_suspend_ops); +} diff --git a/arch/arm/mach-s5pv210/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h new file mode 100644 index 000000000..9cad2306e --- /dev/null +++ b/arch/arm/mach-s5pv210/regs-clock.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5PV210 - Clock register definitions + */ + +#ifndef __ASM_ARCH_REGS_CLOCK_H +#define __ASM_ARCH_REGS_CLOCK_H __FILE__ + +#define S3C_ADDR_BASE 0xF6000000 +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#define S3C_VA_SYS S3C_ADDR(0x00100000) + +#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S5P_APLL_LOCK S5P_CLKREG(0x00) +#define S5P_MPLL_LOCK S5P_CLKREG(0x08) +#define S5P_EPLL_LOCK S5P_CLKREG(0x10) +#define S5P_VPLL_LOCK S5P_CLKREG(0x20) + +#define S5P_APLL_CON S5P_CLKREG(0x100) +#define S5P_MPLL_CON S5P_CLKREG(0x108) +#define S5P_EPLL_CON S5P_CLKREG(0x110) +#define S5P_EPLL_CON1 S5P_CLKREG(0x114) +#define S5P_VPLL_CON S5P_CLKREG(0x120) + +#define S5P_CLK_SRC0 S5P_CLKREG(0x200) +#define S5P_CLK_SRC1 S5P_CLKREG(0x204) +#define S5P_CLK_SRC2 S5P_CLKREG(0x208) +#define S5P_CLK_SRC3 S5P_CLKREG(0x20C) +#define S5P_CLK_SRC4 S5P_CLKREG(0x210) +#define S5P_CLK_SRC5 S5P_CLKREG(0x214) +#define S5P_CLK_SRC6 S5P_CLKREG(0x218) + +#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) +#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) + +#define S5P_CLK_DIV0 S5P_CLKREG(0x300) +#define S5P_CLK_DIV1 S5P_CLKREG(0x304) +#define S5P_CLK_DIV2 S5P_CLKREG(0x308) +#define S5P_CLK_DIV3 S5P_CLKREG(0x30C) +#define S5P_CLK_DIV4 S5P_CLKREG(0x310) +#define S5P_CLK_DIV5 S5P_CLKREG(0x314) +#define S5P_CLK_DIV6 S5P_CLKREG(0x318) +#define S5P_CLK_DIV7 S5P_CLKREG(0x31C) + +#define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400) +#define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404) +#define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408) + +#define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420) +#define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424) + +#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440) +#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444) +#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460) +#define S5P_CLKGATE_IP1 S5P_CLKREG(0x464) +#define S5P_CLKGATE_IP2 S5P_CLKREG(0x468) +#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) +#define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) + +#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) +#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) +#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) +#define S5P_CLK_OUT S5P_CLKREG(0x500) + +/* DIV/MUX STATUS */ +#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) +#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) +#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) +#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) + +/* CLKSRC0 */ +#define S5P_CLKSRC0_MUX200_SHIFT (16) +#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) +#define S5P_CLKSRC0_MUX166_MASK (0x1<<20) +#define S5P_CLKSRC0_MUX133_MASK (0x1<<24) + +/* CLKSRC2 */ +#define S5P_CLKSRC2_G3D_SHIFT (0) +#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) +#define S5P_CLKSRC2_MFC_SHIFT (4) +#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) + +/* CLKSRC6*/ +#define S5P_CLKSRC6_ONEDRAM_SHIFT (24) +#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT) + +/* CLKDIV0 */ +#define S5P_CLKDIV0_APLL_SHIFT (0) +#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) +#define S5P_CLKDIV0_A2M_SHIFT (4) +#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) +#define S5P_CLKDIV0_HCLK200_SHIFT (8) +#define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT) +#define S5P_CLKDIV0_PCLK100_SHIFT (12) +#define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT) +#define S5P_CLKDIV0_HCLK166_SHIFT (16) +#define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT) +#define S5P_CLKDIV0_PCLK83_SHIFT (20) +#define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT) +#define S5P_CLKDIV0_HCLK133_SHIFT (24) +#define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT) +#define S5P_CLKDIV0_PCLK66_SHIFT (28) +#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) + +/* CLKDIV2 */ +#define S5P_CLKDIV2_G3D_SHIFT (0) +#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) +#define S5P_CLKDIV2_MFC_SHIFT (4) +#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) + +/* CLKDIV6 */ +#define S5P_CLKDIV6_ONEDRAM_SHIFT (28) +#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) + +#define S5P_SWRESET S5P_CLKREG(0x2000) + +#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) + +/* Registers related to power management */ +#define S5P_PWR_CFG S5P_CLKREG(0xC000) +#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) +#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) +#define S5P_PWR_MODE S5P_CLKREG(0xC00C) +#define S5P_NORMAL_CFG S5P_CLKREG(0xC010) +#define S5P_IDLE_CFG S5P_CLKREG(0xC020) +#define S5P_STOP_CFG S5P_CLKREG(0xC030) +#define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034) +#define S5P_SLEEP_CFG S5P_CLKREG(0xC040) + +#define S5P_OSC_FREQ S5P_CLKREG(0xC100) +#define S5P_OSC_STABLE S5P_CLKREG(0xC104) +#define S5P_PWR_STABLE S5P_CLKREG(0xC108) +#define S5P_MTC_STABLE S5P_CLKREG(0xC110) +#define S5P_CLAMP_STABLE S5P_CLKREG(0xC114) + +#define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) +#define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) + +#define S5P_OTHERS S5P_CLKREG(0xE000) +#define S5P_OM_STAT S5P_CLKREG(0xE100) +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) +#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) +#define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810) + +#define S5P_INFORM0 S5P_CLKREG(0xF000) +#define S5P_INFORM1 S5P_CLKREG(0xF004) +#define S5P_INFORM2 S5P_CLKREG(0xF008) +#define S5P_INFORM3 S5P_CLKREG(0xF00C) +#define S5P_INFORM4 S5P_CLKREG(0xF010) +#define S5P_INFORM5 S5P_CLKREG(0xF014) +#define S5P_INFORM6 S5P_CLKREG(0xF018) +#define S5P_INFORM7 S5P_CLKREG(0xF01C) + +#define S5P_RST_STAT S5P_CLKREG(0xA000) +#define S5P_OSC_CON S5P_CLKREG(0x8000) +#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) +#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) +#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) + +#define S5P_IDLE_CFG_TL_MASK (3 << 30) +#define S5P_IDLE_CFG_TM_MASK (3 << 28) +#define S5P_IDLE_CFG_TL_ON (2 << 30) +#define S5P_IDLE_CFG_TM_ON (2 << 28) +#define S5P_IDLE_CFG_DIDLE (1 << 0) + +#define S5P_CFG_WFI_CLEAN (~(3 << 8)) +#define S5P_CFG_WFI_IDLE (1 << 8) +#define S5P_CFG_WFI_STOP (2 << 8) +#define S5P_CFG_WFI_SLEEP (3 << 8) + +#define S5P_OTHER_SYS_INT 24 +#define S5P_OTHER_STA_TYPE 23 +#define S5P_OTHER_SYSC_INTOFF (1 << 0) +#define STA_TYPE_EXPON 0 +#define STA_TYPE_SFR 1 + +#define S5P_PWR_STA_EXP_SCALE 0 +#define S5P_PWR_STA_CNT 4 + +#define S5P_PWR_STABLE_COUNT 85500 + +#define S5P_SLEEP_CFG_OSC_EN (1 << 0) +#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1) + +/* OTHERS Resgister */ +#define S5P_OTHERS_USB_SIG_MASK (1 << 16) + +/* S5P_DAC_CONTROL */ +#define S5P_DAC_ENABLE (1) +#define S5P_DAC_DISABLE (0) + +#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c new file mode 100644 index 000000000..a21ed3bb9 --- /dev/null +++ b/arch/arm/mach-s5pv210/s5pv210.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Samsung's S5PC110/S5PV210 flattened device tree enabled machine. +// +// Copyright (c) 2013-2014 Samsung Electronics Co., Ltd. +// Mateusz Krawczuk <m.krawczuk@partner.samsung.com> +// Tomasz Figa <t.figa@samsung.com> + +#include <linux/of_fdt.h> +#include <linux/of_platform.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/system_misc.h> + +#include "common.h" +#include "regs-clock.h" + +static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname, + int depth, void *data) +{ + struct map_desc iodesc; + const __be32 *reg; + int len; + + if (!of_flat_dt_is_compatible(node, "samsung,s5pv210-clock")) + return 0; + + reg = of_get_flat_dt_prop(node, "reg", &len); + if (reg == NULL || len != (sizeof(unsigned long) * 2)) + return 0; + + iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); + iodesc.length = be32_to_cpu(reg[1]) - 1; + iodesc.virtual = (unsigned long)S3C_VA_SYS; + iodesc.type = MT_DEVICE; + iotable_init(&iodesc, 1); + + return 1; +} + +static void __init s5pv210_dt_map_io(void) +{ + debug_ll_io_init(); + + of_scan_flat_dt(s5pv210_fdt_map_sys, NULL); +} + +static void s5pv210_dt_restart(enum reboot_mode mode, const char *cmd) +{ + __raw_writel(0x1, S5P_SWRESET); +} + +static void __init s5pv210_dt_init_late(void) +{ + platform_device_register_simple("s5pv210-cpufreq", -1, NULL, 0); + s5pv210_pm_init(); +} + +static char const *const s5pv210_dt_compat[] __initconst = { + "samsung,s5pc110", + "samsung,s5pv210", + NULL +}; + +DT_MACHINE_START(S5PV210_DT, "Samsung S5PC110/S5PV210-based board") + .dt_compat = s5pv210_dt_compat, + .map_io = s5pv210_dt_map_io, + .restart = s5pv210_dt_restart, + .init_late = s5pv210_dt_init_late, +MACHINE_END diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S new file mode 100644 index 000000000..81568767f --- /dev/null +++ b/arch/arm/mach-s5pv210/sleep.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PV210 Sleep Code + * Based on S3C64XX sleep code by: + * Ben Dooks, (c) 2008 Simtec Electronics + */ + +#include <linux/linkage.h> + + .text + .align + + /* + * sleep magic, to allow the bootloader to check for an valid + * image to resume to. Must be the first word before the + * s3c_cpu_resume entry. + */ + + .word 0x2bedf00d + + /* + * s3c_cpu_resume + * + * resume code entry for bootloader to call + */ + +ENTRY(s5pv210_cpu_resume) + b cpu_resume +ENDPROC(s5pv210_cpu_resume) |