diff options
Diffstat (limited to 'arch/mips/include/asm/mach-pic32')
| -rw-r--r-- | arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h | 32 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-pic32/irq.h | 14 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-pic32/pic32.h | 36 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-pic32/spaces.h | 15 |
4 files changed, 97 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h new file mode 100644 index 000000000..468230834 --- /dev/null +++ b/arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h @@ -0,0 +1,32 @@ +/* + * Joshua Henderson <joshua.henderson@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H + +/* + * CPU feature overrides for PIC32 boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_vint 1 +#define cpu_has_veic 0 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +#define cpu_has_fpu 0 +#define cpu_has_counter 1 +#define cpu_has_llsc 1 +#define cpu_has_nofpuex 0 +#define cpu_icache_snoops_remote_store 1 +#endif + +#ifdef CONFIG_CPU_MIPS64 +#error This platform does not support 64bit. +#endif + +#endif /* __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-pic32/irq.h b/arch/mips/include/asm/mach-pic32/irq.h new file mode 100644 index 000000000..ddaf999bc --- /dev/null +++ b/arch/mips/include/asm/mach-pic32/irq.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Joshua Henderson <joshua.henderson@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + */ +#ifndef __ASM_MACH_PIC32_IRQ_H +#define __ASM_MACH_PIC32_IRQ_H + +#define NR_IRQS 256 +#define MIPS_CPU_IRQ_BASE 0 + +#include <asm/mach-generic/irq.h> + +#endif /* __ASM_MACH_PIC32_IRQ_H */ diff --git a/arch/mips/include/asm/mach-pic32/pic32.h b/arch/mips/include/asm/mach-pic32/pic32.h new file mode 100644 index 000000000..53918a671 --- /dev/null +++ b/arch/mips/include/asm/mach-pic32/pic32.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Joshua Henderson <joshua.henderson@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + */ +#ifndef _ASM_MACH_PIC32_H +#define _ASM_MACH_PIC32_H + +#include <linux/io.h> + +/* + * PIC32 register offsets for SET/CLR/INV where supported. + */ +#define PIC32_CLR(_reg) ((_reg) + 0x04) +#define PIC32_SET(_reg) ((_reg) + 0x08) +#define PIC32_INV(_reg) ((_reg) + 0x0C) + +/* + * PIC32 Base Register Offsets + */ +#define PIC32_BASE_CONFIG 0x1f800000 +#define PIC32_BASE_OSC 0x1f801200 +#define PIC32_BASE_RESET 0x1f801240 +#define PIC32_BASE_PPS 0x1f801400 +#define PIC32_BASE_UART 0x1f822000 +#define PIC32_BASE_PORT 0x1f860000 +#define PIC32_BASE_DEVCFG2 0x1fc4ff44 + +/* + * Register unlock sequence required for some register access. + */ +void pic32_syskey_unlock_debug(const char *fn, const ulong ln); +#define pic32_syskey_unlock() \ + pic32_syskey_unlock_debug(__func__, __LINE__) + +#endif /* _ASM_MACH_PIC32_H */ diff --git a/arch/mips/include/asm/mach-pic32/spaces.h b/arch/mips/include/asm/mach-pic32/spaces.h new file mode 100644 index 000000000..eb557b52c --- /dev/null +++ b/arch/mips/include/asm/mach-pic32/spaces.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Joshua Henderson <joshua.henderson@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + */ +#ifndef _ASM_MACH_PIC32_SPACES_H +#define _ASM_MACH_PIC32_SPACES_H + +#ifdef CONFIG_PIC32MZDA +#define PHYS_OFFSET _AC(0x08000000, UL) +#endif + +#include <asm/mach-generic/spaces.h> + +#endif /* __ASM_MACH_PIC32_SPACES_H */ |