From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 65 ++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi (limited to 'arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi') diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi new file mode 100644 index 000000000..e180a955b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/ { + aliases { + serial1 = &scif2; + i2c3 = &i2c3; + }; +}; + +&cpu_dai { + sound-dai = <&ssi0>; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +/* + * To enable SCIF2 (SER0) on PMOD1 (CN7) + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if PMOD1_SER0 +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif + +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3